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[/] [s1_core/] [trunk/] [hdl/] [rtl/] [sparc_core/] [sparc_exu_ecl_eccctl.v] - Diff between revs 105 and 113

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Line 16... Line 16... 
// You should have received a copy of the GNU General Public
 
// You should have received a copy of the GNU General Public
 
// License along with this work; if not, write to the Free Software
 
// License along with this work; if not, write to the Free Software
 
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
 
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
 
// 
// 
// ========== Copyright Header End ============================================
 
// ========== Copyright Header End ============================================
 
 
 
`ifdef SIMPLY_RISC_TWEAKS
 
 
 
`define SIMPLY_RISC_SCANIN .si(0)
 
 
 
`else
 
 
 
`define SIMPLY_RISC_SCANIN .si()
 
 
 
`endif
 
////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////
 
/*
 
/*
 
//  Module Name: sparc_exu_ecl_eccctl
 
//  Module Name: sparc_exu_ecl_eccctl
 
//      Description:  Implements the control logic for ecc checking.
 
//      Description:  Implements the control logic for ecc checking.
 
//              This includes picking which error to fix (only one fixed per instruction),
 
//              This includes picking which error to fix (only one fixed per instruction),
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   wire        rs2_sel_rf_e;
 
   wire        rs2_sel_rf_e;
 
   wire        rs3_sel_rf_e;
 
   wire        rs3_sel_rf_e;
 
   wire        vld_rs3_ce_e;
 
   wire        vld_rs3_ce_e;
 
   wire        vld_rs3_ue_e;
 
   wire        vld_rs3_ue_e;
 
 
 
 
 
 
 
`ifdef SIMPLY_RISC_TWEAKS
 
 
 
wire nceen_m;
 
 
 
`endif
 
 
 
 
 
   // Store whether rf value was used for ecc checking
 
   // Store whether rf value was used for ecc checking
 
   assign      ecl_ecc_rs1_use_rf_e = rs1_sel_rf_e & rs1_vld_e & ifu_exu_inst_vld_e;
 
   assign      ecl_ecc_rs1_use_rf_e = rs1_sel_rf_e & rs1_vld_e & ifu_exu_inst_vld_e;
 
   assign      ecl_ecc_rs2_use_rf_e = rs2_sel_rf_e & rs2_vld_e & ifu_exu_inst_vld_e;
 
   assign      ecl_ecc_rs2_use_rf_e = rs2_sel_rf_e & rs2_vld_e & ifu_exu_inst_vld_e;
 
   assign      ecl_ecc_rs3_use_rf_e = rs3_sel_rf_e & rs3_vld_e & ifu_exu_inst_vld_e;
 
   assign      ecl_ecc_rs3_use_rf_e = rs3_sel_rf_e & rs3_vld_e & ifu_exu_inst_vld_e;
 
 
 
 
 
   dff rs1_rf_dff(.din(ecl_byp_rcc_mux2_sel_rf), .clk(clk),
 
   dff_s rs1_rf_dff(.din(ecl_byp_rcc_mux2_sel_rf), .clk(clk),
 
                  .q(rs1_sel_rf_e), .se(se), .si(), .so());
 
                  .q(rs1_sel_rf_e), .se(se), `SIMPLY_RISC_SCANIN, .so());
 
   dff rs2_rf_dff(.din(ecl_byp_rs2_mux2_sel_rf), .clk(clk),
 
   dff_s rs2_rf_dff(.din(ecl_byp_rs2_mux2_sel_rf), .clk(clk),
 
                  .q(rs2_sel_rf_e), .se(se), .si(), .so());
 
                  .q(rs2_sel_rf_e), .se(se), `SIMPLY_RISC_SCANIN, .so());
 
   dff rs3_rf_dff(.din(ecl_byp_rs3_mux2_sel_rf), .clk(clk),
 
   dff_s rs3_rf_dff(.din(ecl_byp_rs3_mux2_sel_rf), .clk(clk),
 
                  .q(rs3_sel_rf_e), .se(se), .si(), .so());
 
                  .q(rs3_sel_rf_e), .se(se), `SIMPLY_RISC_SCANIN, .so());
 
 
 
 
 
   assign      vld_rs3_ce_e = ecc_ecl_rs3_ce & ~cancel_rs3_ecc_e;
 
   assign      vld_rs3_ce_e = ecc_ecl_rs3_ce & ~cancel_rs3_ecc_e;
 
   assign      vld_rs3_ue_e = ecc_ecl_rs3_ue & ~cancel_rs3_ecc_e;
 
   assign      vld_rs3_ue_e = ecc_ecl_rs3_ue & ~cancel_rs3_ecc_e;
 
   assign    detect_ce_e = (ecc_ecl_rs1_ce | ecc_ecl_rs2_ce | vld_rs3_ce_e);
 
   assign    detect_ce_e = (ecc_ecl_rs1_ce | ecc_ecl_rs2_ce | vld_rs3_ce_e);
 
   assign    detect_ue_e = (ecc_ecl_rs1_ue | ecc_ecl_rs2_ue | vld_rs3_ue_e);
 
   assign    detect_ue_e = (ecc_ecl_rs1_ue | ecc_ecl_rs2_ue | vld_rs3_ue_e);
Line 141... Line 150... 
   assign    flag_ecc_ue_e = (detect_ue_e |
 
   assign    flag_ecc_ue_e = (detect_ue_e |
 
                                    detect_ce_e & ifu_exu_disable_ce_e); // convert ce to ue
 
                                    detect_ce_e & ifu_exu_disable_ce_e); // convert ce to ue
 
   assign    flag_ecc_ce_e = detect_ce_e & ~ifu_exu_disable_ce_e;
 
   assign    flag_ecc_ce_e = detect_ce_e & ~ifu_exu_disable_ce_e;
 
 
 
 
 
   // Pass along signal to fix errors
 
   // Pass along signal to fix errors
 
   dff byp_sel_ecc_e2m(.din(flag_ecc_ce_e), .clk(clk), .q(ecl_byp_sel_ecc_m),
 
   dff_s byp_sel_ecc_e2m(.din(flag_ecc_ce_e), .clk(clk), .q(ecl_byp_sel_ecc_m),
 
                       .se(se), .si(), .so());
 
                       .se(se), `SIMPLY_RISC_SCANIN, .so());
 
   dff ecc_ue_e2m(.din(flag_ecc_ue_e), .clk(clk), .q(exu_ifu_ecc_ue_m),
 
   dff_s ecc_ue_e2m(.din(flag_ecc_ue_e), .clk(clk), .q(exu_ifu_ecc_ue_m),
 
                  .se(se), .si(), .so());
 
                  .se(se), `SIMPLY_RISC_SCANIN, .so());
 
   dff nceen_e2m(.din(ifu_exu_nceen_e), .clk(clk), .q(nceen_m), .se(se), .si(), .so());
 
   dff_s nceen_e2m(.din(ifu_exu_nceen_e), .clk(clk), .q(nceen_m), .se(se), `SIMPLY_RISC_SCANIN, .so());
 
   assign    ue_trap_m = exu_ifu_ecc_ue_m & nceen_m;
 
   assign    ue_trap_m = exu_ifu_ecc_ue_m & nceen_m;
 
   // only report ce (and replay) if no ue
 
   // only report ce (and replay) if no ue
 
   assign      exu_ifu_ecc_ce_m = ecl_byp_sel_ecc_m & ~exu_ifu_ecc_ue_m;
 
   assign      exu_ifu_ecc_ce_m = ecl_byp_sel_ecc_m & ~exu_ifu_ecc_ue_m;
 
   // if globals then report %gl.  otherwise log %cwp
 
   // if globals then report %gl.  otherwise log %cwp
 
   assign      exu_ifu_err_reg_m[7:5] = (~log_rs_m[4] & ~log_rs_m[3])? {1'b0,gl_m[1:0]}: cwp_m[2:0];
 
   assign      exu_ifu_err_reg_m[7:5] = (~log_rs_m[4] & ~log_rs_m[3])? {1'b0,gl_m[1:0]}: cwp_m[2:0];
Line 158... Line 167... 
   // Control for mux to ecc decoder (just ce)
 
   // Control for mux to ecc decoder (just ce)
 
   assign      sel_rs1_e = ecc_ecl_rs1_ce;
 
   assign      sel_rs1_e = ecc_ecl_rs1_ce;
 
   assign      sel_rs2_e = ~ecc_ecl_rs1_ce & ecc_ecl_rs2_ce;
 
   assign      sel_rs2_e = ~ecc_ecl_rs1_ce & ecc_ecl_rs2_ce;
 
   assign      sel_rs3_e = ~(ecc_ecl_rs1_ce | ecc_ecl_rs2_ce);
 
   assign      sel_rs3_e = ~(ecc_ecl_rs1_ce | ecc_ecl_rs2_ce);
 
 
 
 
 
   dff ecc_sel_rs1_dff(.din(sel_rs1_e), .clk(clk), .q(sel_rs1_m),
 
   dff_s ecc_sel_rs1_dff(.din(sel_rs1_e), .clk(clk), .q(sel_rs1_m),
 
                       .se(se), .si(), .so());
 
                       .se(se), `SIMPLY_RISC_SCANIN, .so());
 
   dff ecc_sel_rs2_dff(.din(sel_rs2_e), .clk(clk), .q(sel_rs2_m),
 
   dff_s ecc_sel_rs2_dff(.din(sel_rs2_e), .clk(clk), .q(sel_rs2_m),
 
                       .se(se), .si(), .so());
 
                       .se(se), `SIMPLY_RISC_SCANIN, .so());
 
   dff ecc_sel_rs3_dff(.din(sel_rs3_e), .clk(clk), .q(sel_rs3_m),
 
   dff_s ecc_sel_rs3_dff(.din(sel_rs3_e), .clk(clk), .q(sel_rs3_m),
 
                       .se(se), .si(), .so());
 
                       .se(se), `SIMPLY_RISC_SCANIN, .so());
 
   // Make selects one hot
 
   // Make selects one hot
 
   assign      safe_sel_rs1_m = sel_rs1_m | rst_tri_en;
 
   assign      safe_sel_rs1_m = sel_rs1_m | rst_tri_en;
 
   assign      safe_sel_rs2_m = sel_rs2_m & ~rst_tri_en;
 
   assign      safe_sel_rs2_m = sel_rs2_m & ~rst_tri_en;
 
   assign      safe_sel_rs3_m = sel_rs3_m & ~rst_tri_en;
 
   assign      safe_sel_rs3_m = sel_rs3_m & ~rst_tri_en;
 
   assign      ecl_ecc_sel_rs1_m_l = ~safe_sel_rs1_m;
 
   assign      ecl_ecc_sel_rs1_m_l = ~safe_sel_rs1_m;
Line 194... Line 203... 
                          .in2(ifu_exu_rs3_m[4:0]),
 
                          .in2(ifu_exu_rs3_m[4:0]),
 
                          .sel0(ecl_ecc_log_rs1_m),
 
                          .sel0(ecl_ecc_log_rs1_m),
 
                          .sel1(ecl_ecc_log_rs2_m),
 
                          .sel1(ecl_ecc_log_rs2_m),
 
                          .sel2(ecl_ecc_log_rs3_m));
 
                          .sel2(ecl_ecc_log_rs3_m));
 
 
 
 
 
   dff #(3) cwp_d2e(.din(rml_ecl_cwp_d[2:0]), .clk(clk), .q(cwp_e[2:0]),
 
   dff_s #(3) cwp_d2e(.din(rml_ecl_cwp_d[2:0]), .clk(clk), .q(cwp_e[2:0]),
 
                    .se(se), .si(), .so());
 
                    .se(se), `SIMPLY_RISC_SCANIN, .so());
 
   dff #(3) cwp_e2m(.din(cwp_e[2:0]), .clk(clk), .q(cwp_m[2:0]),
 
   dff_s #(3) cwp_e2m(.din(cwp_e[2:0]), .clk(clk), .q(cwp_m[2:0]),
 
                    .se(se), .si(), .so());
 
                    .se(se), `SIMPLY_RISC_SCANIN, .so());
 
   dff #(2) gl_e2m(.din(rml_ecl_gl_e[1:0]), .clk(clk), .q(gl_m[1:0]),
 
   dff_s #(2) gl_e2m(.din(rml_ecl_gl_e[1:0]), .clk(clk), .q(gl_m[1:0]),
 
                   .se(se), .si(), .so());
 
                   .se(se), `SIMPLY_RISC_SCANIN, .so());
 
 
 
 
 
   // Syndrome needs to know if it was really a ce or ue
 
   // Syndrome needs to know if it was really a ce or ue
 
   mux3ds ecc_synd7_mux(.dout(exu_ifu_err_synd_7_m),
 
   mux3ds ecc_synd7_mux(.dout(exu_ifu_err_synd_7_m),
 
                        .in0(rs1_ce_m),
 
                        .in0(rs1_ce_m),
 
                        .in1(rs2_ce_m),
 
                        .in1(rs2_ce_m),
Line 216... Line 225... 
   // signals for injecting errors
 
   // signals for injecting errors
 
   // inject error if it is enabled and a write will probably happen
 
   // inject error if it is enabled and a write will probably happen
 
   // (don't bother to check kill_w
 
   // (don't bother to check kill_w
 
   assign      inj_irferr_m = wb_eccctl_spec_wen_next & ifu_exu_inj_irferr;
 
   assign      inj_irferr_m = wb_eccctl_spec_wen_next & ifu_exu_inj_irferr;
 
   assign      ecl_byp_ecc_mask_m_l = ~(ifu_exu_ecc_mask[7:0] & {8{inj_irferr_m}});
 
   assign      ecl_byp_ecc_mask_m_l = ~(ifu_exu_ecc_mask[7:0] & {8{inj_irferr_m}});
 
   dff inj_irferr_m2w(.din(inj_irferr_m), .clk(clk), .q(inj_irferr_w),
 
   dff_s inj_irferr_m2w(.din(inj_irferr_m), .clk(clk), .q(inj_irferr_w),
 
                      .se(se), .si(), .so());
 
                      .se(se), `SIMPLY_RISC_SCANIN, .so());
 
   assign      exu_ifu_inj_ack = inj_irferr_w;
 
   assign      exu_ifu_inj_ack = inj_irferr_w;
 
 
 
 
 
   // Pipeline Flops
 
   // Pipeline Flops
 
   dff rs1_ue_e2m(.din(ecc_ecl_rs1_ue), .clk(clk), .q(rs1_ue_m), .se(se), .si(), .so());
 
   dff_s rs1_ue_e2m(.din(ecc_ecl_rs1_ue), .clk(clk), .q(rs1_ue_m), .se(se), `SIMPLY_RISC_SCANIN, .so());
 
   dff rs1_ce_e2m(.din(ecc_ecl_rs1_ce), .clk(clk), .q(rs1_ce_m), .se(se), .si(), .so());
 
   dff_s rs1_ce_e2m(.din(ecc_ecl_rs1_ce), .clk(clk), .q(rs1_ce_m), .se(se), `SIMPLY_RISC_SCANIN, .so());
 
   dff rs2_ue_e2m(.din(ecc_ecl_rs2_ue), .clk(clk), .q(rs2_ue_m), .se(se), .si(), .so());
 
   dff_s rs2_ue_e2m(.din(ecc_ecl_rs2_ue), .clk(clk), .q(rs2_ue_m), .se(se), `SIMPLY_RISC_SCANIN, .so());
 
   dff rs2_ce_e2m(.din(ecc_ecl_rs2_ce), .clk(clk), .q(rs2_ce_m), .se(se), .si(), .so());
 
   dff_s rs2_ce_e2m(.din(ecc_ecl_rs2_ce), .clk(clk), .q(rs2_ce_m), .se(se), `SIMPLY_RISC_SCANIN, .so());
 
   dff rs3_ue_e2m(.din(vld_rs3_ue_e), .clk(clk), .q(rs3_ue_m), .se(se), .si(), .so());
 
   dff_s rs3_ue_e2m(.din(vld_rs3_ue_e), .clk(clk), .q(rs3_ue_m), .se(se), `SIMPLY_RISC_SCANIN, .so());
 
 
 
 
 
endmodule // sparc_exu_ecl_eccctl
 
endmodule // sparc_exu_ecl_eccctl
 
 
 
 
 
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