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// You should have received a copy of the GNU General Public
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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//
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// ========== Copyright Header End ============================================
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// ========== Copyright Header End ============================================
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`ifdef SIMPLY_RISC_TWEAKS
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`define SIMPLY_RISC_SCANIN .si(0)
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`else
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`define SIMPLY_RISC_SCANIN .si()
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`endif
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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/*
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/*
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// Module Name: sparc_exu_ecl_mdqctl
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// Module Name: sparc_exu_ecl_mdqctl
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// Description: This block is the control logic for the multiply/divide
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// Description: This block is the control logic for the multiply/divide
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// input buffer. It generates the select lines for both the output
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// input buffer. It generates the select lines for both the output
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Line 37... |
// of the mdq, but may cause a lost cycle as the kill won't affect the logic
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// of the mdq, but may cause a lost cycle as the kill won't affect the logic
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// which chooses the output until the next cycle. The block also
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// which chooses the output until the next cycle. The block also
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// stores the thr, rd, setcc and other control bits for each entry.
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// stores the thr, rd, setcc and other control bits for each entry.
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*/
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*/
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`define MULS 10
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`define IS64 9
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`define SIGNED 8
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`define SET_CC 7
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module sparc_exu_ecl_mdqctl (/*AUTOARG*/
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module sparc_exu_ecl_mdqctl (/*AUTOARG*/
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// Outputs
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// Outputs
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mdqctl_divcntl_input_vld, mdqctl_divcntl_reset_div,
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mdqctl_divcntl_input_vld, mdqctl_divcntl_reset_div,
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mdqctl_divcntl_muldone, ecl_div_div64, ecl_div_signed_div,
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mdqctl_divcntl_muldone, ecl_div_div64, ecl_div_signed_div,
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| Line 170... |
Line 175... |
.in0({curr_div_vld, div_data[10:0]}),
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.in0({curr_div_vld, div_data[10:0]}),
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.in1(div_input_data_d[11:0]),
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.in1(div_input_data_d[11:0]),
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.sel0(~new_div_vld),
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.sel0(~new_div_vld),
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.sel1(new_div_vld));
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.sel1(new_div_vld));
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dffr #(12) div_data_dff(.din(div_data_next[11:0]), .clk(clk), .q(div_data[11:0]),
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dffr_s #(12) div_data_dff(.din(div_data_next[11:0]), .clk(clk), .q(div_data[11:0]),
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.se(se), .si(), .so(), .rst(reset));
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.se(se), `SIMPLY_RISC_SCANIN, .so(), .rst(reset));
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//div kill logic (kills on div by zero exception or if there isn't an outstanding div)
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//div kill logic (kills on div by zero exception or if there isn't an outstanding div)
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assign div_zero_e = isdiv_e & div_ecl_detect_zero_high & div_ecl_detect_zero_low & ~div_data[10];
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assign div_zero_e = isdiv_e & div_ecl_detect_zero_high & div_ecl_detect_zero_low & ~div_data[`MULS];
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assign invalid_div_w = isdiv_w & (~ifu_exu_inst_vld_w | ifu_tlu_flush_w | early_flush_w);
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assign invalid_div_w = isdiv_w & (~ifu_exu_inst_vld_w | ifu_tlu_flush_w | early_flush_w);
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assign kill_thr_div = ~(div_data[1] ^ tid_w1[1]) & ~(div_data[0] ^ tid_w1[0]);
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assign kill_thr_div = ~(div_data[1] ^ tid_w1[1]) & ~(div_data[0] ^ tid_w1[0]);
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assign div_kill = (flush_w1 & kill_thr_div) | invalid_div_w | new_div_vld;
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assign div_kill = (flush_w1 & kill_thr_div) | invalid_div_w | new_div_vld;
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assign curr_div_vld = div_data[11] & ~div_zero_m & ~div_kill & ~div_used;
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assign curr_div_vld = div_data[11] & ~div_zero_m & ~div_kill & ~div_used;
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wire div_zero_unqual_m;
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wire div_zero_unqual_m;
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assign div_zero_m = div_zero_unqual_m & isdiv_m;
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assign div_zero_m = div_zero_unqual_m & isdiv_m;
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dff div_zero_e2m(.din(div_zero_e), .clk(clk), .q(div_zero_unqual_m), .se(se), .si(), .so());
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dff_s div_zero_e2m(.din(div_zero_e), .clk(clk), .q(div_zero_unqual_m), .se(se), `SIMPLY_RISC_SCANIN, .so());
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// pipeling for divide valid signal (for inst_vld checking)
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// pipeling for divide valid signal (for inst_vld checking)
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dff isdiv_d2e(.din(new_div_vld), .clk(clk), .q(isdiv_e),
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dff_s isdiv_d2e(.din(new_div_vld), .clk(clk), .q(isdiv_e),
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.se(se), .si(), .so());
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.se(se), `SIMPLY_RISC_SCANIN, .so());
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dff isdiv_e2m(.din(isdiv_e_valid), .clk(clk), .q(isdiv_m),
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dff_s isdiv_e2m(.din(isdiv_e_valid), .clk(clk), .q(isdiv_m),
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.se(se), .si(), .so());
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.se(se), `SIMPLY_RISC_SCANIN, .so());
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dff isdiv_m2w(.din(isdiv_m_valid), .clk(clk), .q(isdiv_w),
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dff_s isdiv_m2w(.din(isdiv_m_valid), .clk(clk), .q(isdiv_w),
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.se(se), .si(), .so());
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.se(se), `SIMPLY_RISC_SCANIN, .so());
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assign isdiv_e_valid = isdiv_e & ~div_kill;
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assign isdiv_e_valid = isdiv_e & ~div_kill;
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assign isdiv_m_valid = isdiv_m & ~div_kill;
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assign isdiv_m_valid = isdiv_m & ~div_kill;
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// control for div state machine
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// control for div state machine
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assign mdqctl_divcntl_reset_div = (~div_data[11] | div_kill);
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assign mdqctl_divcntl_reset_div = (~div_data[11] | div_kill);
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assign mdqctl_divcntl_input_vld = isdiv_e;
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assign mdqctl_divcntl_input_vld = isdiv_e;
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// control signals for div
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// control signals for div
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assign ecl_div_div64 = div_data[9];
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assign ecl_div_div64 = div_data[`IS64];
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assign ecl_div_signed_div = div_data[8];
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assign ecl_div_signed_div = div_data[`SIGNED];
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assign ecl_div_muls = div_data[10];
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assign ecl_div_muls = div_data[`MULS];
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// control for writeback on completion
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// control for writeback on completion
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assign mdqctl_wb_divrd_g[4:0] = div_data[6:2];
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assign mdqctl_wb_divrd_g[4:0] = div_data[6:2];
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assign mdqctl_wb_divthr_g[1:0] = div_data[1:0];
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assign mdqctl_wb_divthr_g[1:0] = div_data[1:0];
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assign mdqctl_wb_divsetcc_g = div_data[7] | div_data[10];
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assign mdqctl_wb_divsetcc_g = div_data[`SET_CC] | div_data[`MULS];
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assign mdqctl_wb_yreg_shift_g = div_used & div_data[10];
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assign mdqctl_wb_yreg_shift_g = div_used & div_data[`MULS];
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////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////
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// Multiply control
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// Multiply control
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//----------------------
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//----------------------
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// The multiply will drop the current operation if a new request is issued.
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// The multiply will drop the current operation if a new request is issued.
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// This requires addition checking to make sure that the kills are for the
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// This requires addition checking to make sure that the kills are for the
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// proper operation.
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// proper operation.
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////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////
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dff ismul_d2e(.din(ifu_exu_muldivop_d[4]), .clk(clk), .q(ismul_e),
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dff_s ismul_d2e(.din(ifu_exu_muldivop_d[4]), .clk(clk), .q(ismul_e),
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.se(se), .si(), .so());
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.se(se), `SIMPLY_RISC_SCANIN, .so());
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dff ismul_e2m(.din(ismul_e_valid), .clk(clk), .q(ismul_m),
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dff_s ismul_e2m(.din(ismul_e_valid), .clk(clk), .q(ismul_m),
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.se(se), .si(), .so());
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.se(se), `SIMPLY_RISC_SCANIN, .so());
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dff ismul_m2w(.din(ismul_m_valid), .clk(clk), .q(ismul_w),
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dff_s ismul_m2w(.din(ismul_m_valid), .clk(clk), .q(ismul_w),
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.se(se), .si(), .so());
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.se(se), `SIMPLY_RISC_SCANIN, .so());
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assign ismul_e_valid = ismul_e & ~mul_kill;
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assign ismul_e_valid = ismul_e & ~mul_kill;
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assign ismul_m_valid = ismul_m & ~mul_kill & ~ismul_e;
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assign ismul_m_valid = ismul_m & ~mul_kill & ~ismul_e;
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// store control signals
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// store control signals
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// assign mul_used = divcntl_wb_req_g & wb_divcntl_ack_g & ~ecl_div_sel_div;
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// assign mul_used = divcntl_wb_req_g & wb_divcntl_ack_g & ~ecl_div_sel_div;
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Line 242... |
ifu_exu_muldivop_d[0], // setcc
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ifu_exu_muldivop_d[0], // setcc
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ifu_exu_rd_d[4:0],
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ifu_exu_rd_d[4:0],
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tid_d[1:0]};
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tid_d[1:0]};
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assign mul_data_next[9:0] = (new_mul_d)? mul_input_data_d[9:0]: mul_data[9:0];
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assign mul_data_next[9:0] = (new_mul_d)? mul_input_data_d[9:0]: mul_data[9:0];
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dff #(10) mul_data_dff(.din(mul_data_next[9:0]), .clk(clk), .q(mul_data[9:0]),
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dff_s #(10) mul_data_dff(.din(mul_data_next[9:0]), .clk(clk), .q(mul_data[9:0]),
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.se(se), .si(), .so());
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.se(se), `SIMPLY_RISC_SCANIN, .so());
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// mul kill logic
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// mul kill logic
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assign kill_thr_mul = ~(mul_data[1] ^ tid_w1[1]) & ~(mul_data[0] ^ tid_w1[0]);
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assign kill_thr_mul = ~(mul_data[1] ^ tid_w1[1]) & ~(mul_data[0] ^ tid_w1[0]);
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assign mul_kill = (flush_w1 & kill_thr_mul) | reset;
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assign mul_kill = (flush_w1 & kill_thr_mul) | reset;
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assign invalid_mul_w = ismul_w & ~ifu_exu_inst_vld_w;
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assign invalid_mul_w = ismul_w & ~ifu_exu_inst_vld_w;
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// control signals for mul data in div unit
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// control signals for mul data in div unit
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assign ecl_div_mul_keep_data = ~ismul_e;
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assign ecl_div_mul_keep_data = ~ismul_e;
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assign ecl_div_mul_get_new_data = ismul_e & mul_data[9];
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assign ecl_div_mul_get_new_data = ismul_e & mul_data[`IS64];
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assign ecl_div_mul_get_32bit_data = ismul_e & ~mul_data[9];
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assign ecl_div_mul_get_32bit_data = ismul_e & ~mul_data[`IS64];
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assign ecl_div_mul_sext_rs1_e = byp_alu_rs1_data_31_e & mul_data[8];
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assign ecl_div_mul_sext_rs1_e = byp_alu_rs1_data_31_e & mul_data[`SIGNED];
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assign ecl_div_mul_sext_rs2_e = byp_alu_rs2_data_31_e & mul_data[8];
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assign ecl_div_mul_sext_rs2_e = byp_alu_rs2_data_31_e & mul_data[`SIGNED];
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// control for writeback on completion
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// control for writeback on completion
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assign mdqctl_wb_yreg_wen_g = ~mul_data[9] & ecl_div_mul_wen;
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assign mdqctl_wb_yreg_wen_g = ~mul_data[`IS64] & ecl_div_mul_wen;
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assign mdqctl_wb_multhr_g[1:0] = mul_data[1:0];
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assign mdqctl_wb_multhr_g[1:0] = mul_data[1:0];
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assign mdqctl_wb_mulsetcc_g = mul_data[7];
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assign mdqctl_wb_mulsetcc_g = mul_data[`SET_CC];
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assign mdqctl_wb_mulrd_g[4:0] = mul_data[6:2];
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assign mdqctl_wb_mulrd_g[4:0] = mul_data[6:2];
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// interface with mul and state of pending mul
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// interface with mul and state of pending mul
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assign mul_ready_next = ismul_e_valid | (mul_ready & ~mul_exu_ack & ~mul_kill & ~ismul_e & ~invalid_mul_w);
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assign mul_ready_next = ismul_e_valid | (mul_ready & ~mul_exu_ack & ~mul_kill & ~ismul_e & ~invalid_mul_w);
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dff mul_ready_dff(.din(mul_ready_next), .clk(clk), .q(mul_ready), .se(se), .si(), .so());
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dff_s mul_ready_dff(.din(mul_ready_next), .clk(clk), .q(mul_ready), .se(se), `SIMPLY_RISC_SCANIN, .so());
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assign exu_mul_input_vld = mul_ready;
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assign exu_mul_input_vld = mul_ready;
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// If there was a valid request and an ack then start passing down pipe
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// If there was a valid request and an ack then start passing down pipe
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assign mul_done_ack = mul_ready & ~mul_kill & ~ismul_e & mul_exu_ack & ~invalid_mul_w;
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assign mul_done_ack = mul_ready & ~mul_kill & ~ismul_e & mul_exu_ack & ~invalid_mul_w;
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dff dff_done_ack2c0(.din(mul_done_ack), .clk(clk), .q(mul_done_c0),
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dff_s dff_done_ack2c0(.din(mul_done_ack), .clk(clk), .q(mul_done_c0),
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.se(se), .si(), .so());
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.se(se), `SIMPLY_RISC_SCANIN, .so());
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// need to check here cause this could be w
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// need to check here cause this could be w
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assign mul_done_valid_c0 = mul_done_c0 & ~mul_kill & ~invalid_mul_w & ~ismul_e;
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assign mul_done_valid_c0 = mul_done_c0 & ~mul_kill & ~invalid_mul_w & ~ismul_e;
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dff dff_done_c02c1(.din(mul_done_valid_c0), .clk(clk), .q(mul_done_c1),
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dff_s dff_done_c02c1(.din(mul_done_valid_c0), .clk(clk), .q(mul_done_c1),
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.se(se), .si(), .so());
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.se(se), `SIMPLY_RISC_SCANIN, .so());
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// need to check here cause this could be w1
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// need to check here cause this could be w1
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assign mul_done_valid_c1 = mul_done_c1 & ~mul_kill & ~ismul_e;
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assign mul_done_valid_c1 = mul_done_c1 & ~mul_kill & ~ismul_e;
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dff dff_done_c1c2(.din(mul_done_valid_c1), .clk(clk), .q(mul_done_c2),
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dff_s dff_done_c1c2(.din(mul_done_valid_c1), .clk(clk), .q(mul_done_c2),
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.se(se), .si(), .so());
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.se(se), `SIMPLY_RISC_SCANIN, .so());
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dff dff_done_c22c3(.din(mul_done_c2), .clk(clk), .q(mul_done_c3),
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dff_s dff_done_c22c3(.din(mul_done_c2), .clk(clk), .q(mul_done_c3),
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.se(se), .si(), .so());
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.se(se), `SIMPLY_RISC_SCANIN, .so());
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dff dff_done_c32c4(.din(mul_done_c3), .clk(clk), .q(ecl_div_mul_wen),
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dff_s dff_done_c32c4(.din(mul_done_c3), .clk(clk), .q(ecl_div_mul_wen),
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.se(se), .si(), .so());
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.se(se), `SIMPLY_RISC_SCANIN, .so());
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// Mul result state machine
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// Mul result state machine
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assign go_mul_done = ~mul_done & ecl_div_mul_wen;
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assign go_mul_done = ~mul_done & ecl_div_mul_wen;
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assign stay_mul_done = mul_done & (~wb_divcntl_ack_g | ecl_div_sel_div);
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assign stay_mul_done = mul_done & (~wb_divcntl_ack_g | ecl_div_sel_div);
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assign next_mul_done = ~reset & (go_mul_done | stay_mul_done);
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assign next_mul_done = ~reset & (go_mul_done | stay_mul_done);
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assign mdqctl_divcntl_muldone = mul_done;
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assign mdqctl_divcntl_muldone = mul_done;
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// mul state flop
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// mul state flop
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dff mulstate_dff(.din(next_mul_done), .clk(clk), .q(mul_done), .se(se), .si(),
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dff_s mulstate_dff(.din(next_mul_done), .clk(clk), .q(mul_done), .se(se), `SIMPLY_RISC_SCANIN,
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.so());
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.so());
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/////////////////////////////////////////
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/////////////////////////////////////////
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// Pipeline registers for control signals
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// Pipeline registers for control signals
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/////////////////////////////////////////
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/////////////////////////////////////////
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