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// You should have received a copy of the GNU General Public
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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//
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// ========== Copyright Header End ============================================
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// ========== Copyright Header End ============================================
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`ifdef SIMPLY_RISC_TWEAKS
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`define SIMPLY_RISC_SCANIN .si(0)
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`else
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`define SIMPLY_RISC_SCANIN .si()
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`endif
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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/*
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/*
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// Module Name: sparc_exu_eclccr
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// Module Name: sparc_exu_eclccr
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// Description: 4 bit condition code registers with forwarding. Takes
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// Description: 4 bit condition code registers with forwarding. Takes
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// the e_stage result and writes on the w stage.
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// the e_stage result and writes on the w stage.
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wire [7:0] ccr_m;
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wire [7:0] ccr_m;
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// D2E flops
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// D2E flops
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dff dff_setcc_d2e(.din(ifu_exu_setcc_d), .clk(clk), .q(setcc_e),
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dff_s dff_setcc_d2e(.din(ifu_exu_setcc_d), .clk(clk), .q(setcc_e),
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.se(se), .si(), .so());
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.se(se), `SIMPLY_RISC_SCANIN, .so());
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// E stage
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// E stage
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assign alu_cc_e = {alu_xcc_e, alu_icc_e};
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assign alu_cc_e = {alu_xcc_e, alu_icc_e};
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assign valid_setcc_e = setcc_e & ~ifu_exu_kill_e;
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assign valid_setcc_e = setcc_e & ~ifu_exu_kill_e;
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dff #(8) dff_cc_e2m(.din(alu_cc_e[7:0]), .clk(clk), .q(alu_cc_m[7:0]),
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dff_s #(8) dff_cc_e2m(.din(alu_cc_e[7:0]), .clk(clk), .q(alu_cc_m[7:0]),
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.se(se), .si(), .so());
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.se(se), `SIMPLY_RISC_SCANIN, .so());
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dff dff_setcc_e2m(.din(valid_setcc_e), .clk(clk), .q(setcc_m),
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dff_s dff_setcc_e2m(.din(valid_setcc_e), .clk(clk), .q(setcc_m),
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.se(se), .si(), .so());
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.se(se), `SIMPLY_RISC_SCANIN, .so());
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// M stage
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// M stage
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assign valid_setcc_m = setcc_m | tlu_exu_cwpccr_update_m;
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assign valid_setcc_m = setcc_m | tlu_exu_cwpccr_update_m;
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mux2ds #(8) mux_ccr_m(.dout(ccr_m[7:0]),
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mux2ds #(8) mux_ccr_m(.dout(ccr_m[7:0]),
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.in0(alu_cc_m[7:0]),
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.in0(alu_cc_m[7:0]),
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.in1(tlu_exu_ccr_m[7:0]),
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.in1(tlu_exu_ccr_m[7:0]),
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.sel0(~tlu_exu_cwpccr_update_m),
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.sel0(~tlu_exu_cwpccr_update_m),
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.sel1(tlu_exu_cwpccr_update_m));
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.sel1(tlu_exu_cwpccr_update_m));
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dff #(8) dff_cc_m2w(.din(ccr_m[7:0]), .clk(clk), .q(alu_cc_w[7:0]),
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dff_s #(8) dff_cc_m2w(.din(ccr_m[7:0]), .clk(clk), .q(alu_cc_w[7:0]),
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.se(se), .si(), .so());
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.se(se), `SIMPLY_RISC_SCANIN, .so());
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dff dff_setcc_m2w(.din(valid_setcc_m), .clk(clk), .q(setcc_w),
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dff_s dff_setcc_m2w(.din(valid_setcc_m), .clk(clk), .q(setcc_w),
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.se(se), .si(), .so());
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.se(se), `SIMPLY_RISC_SCANIN, .so());
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// W stage
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// W stage
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assign bypass_cc_w = ifu_exu_inst_vld_w & setcc_w;
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assign bypass_cc_w = ifu_exu_inst_vld_w & setcc_w;
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assign valid_setcc_w = ~ifu_tlu_flush_w & ~early_flush_w & ifu_exu_inst_vld_w & (setcc_w | wb_ccr_wrccr_w);
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assign valid_setcc_w = ~ifu_tlu_flush_w & ~early_flush_w & ifu_exu_inst_vld_w & (setcc_w | wb_ccr_wrccr_w);
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Line 156... |
mux2ds #(8) mux_ccrin_cc(.dout(exu_ifu_cc_w[7:0]), .sel0(wb_ccr_wrccr_w),
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mux2ds #(8) mux_ccrin_cc(.dout(exu_ifu_cc_w[7:0]), .sel0(wb_ccr_wrccr_w),
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.sel1(use_alu_cc),
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.sel1(use_alu_cc),
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.in0(byp_ecl_wrccr_data_w[7:0]),
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.in0(byp_ecl_wrccr_data_w[7:0]),
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.in1(alu_cc_w[7:0]));
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.in1(alu_cc_w[7:0]));
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dff #(3) setcc_g2w2 (.din({wb_ccr_setcc_g, wb_ccr_thr_g[1:0]}), .clk(clk),
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dff_s #(3) setcc_g2w2 (.din({wb_ccr_setcc_g, wb_ccr_thr_g[1:0]}), .clk(clk),
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.q({setcc_w2, thr_w2[1:0]}),
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.q({setcc_w2, thr_w2[1:0]}),
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.se(se), .si(), .so());
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.se(se), `SIMPLY_RISC_SCANIN, .so());
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/////////////////////////
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/////////////////////////
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// Storage of ccr
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// Storage of ccr
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/////////////////////////
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/////////////////////////
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`ifdef FPGA_SYN_1THREAD
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assign thr0_w2 = ~thr_w2[1] & ~thr_w2[0];
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assign wen_thr0_w = (thr_w[0] & valid_setcc_w & ~wen_thr0_w2);
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assign wen_thr0_w2 = thr0_w2 & setcc_w2;
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assign wen_thr0_l = ~(wen_thr0_w | wen_thr0_w2);
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// mux between cc_w, cc_w2, old value, tlu value
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mux3ds #(8) mux_ccrin0(.dout(ccrin_thr0[7:0]), .sel0(wen_thr0_w),
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.sel1(wen_thr0_w2), .sel2(wen_thr0_l),
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.in0(exu_ifu_cc_w[7:0]),
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.in1(divcntl_ccr_cc_w2[7:0]), .in2(ccr_thr0[7:0]));
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// store new value
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dff_s #(8) dff_ccr_thr0(.din(ccrin_thr0[7:0]), .clk(clk), .q(ccr_thr0[7:0]),
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.se(se), `SIMPLY_RISC_SCANIN, .so());
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assign ccr_d[7:0] = ccr_thr0[7:0];
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`else // !`ifdef FPGA_SYN_1THREAD
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// !`ifdef FPGA_SYN_1THREAD
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// decode thr_w2 for mux select
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// decode thr_w2 for mux select
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assign thr0_w2 = ~thr_w2[1] & ~thr_w2[0];
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assign thr0_w2 = ~thr_w2[1] & ~thr_w2[0];
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assign thr1_w2 = ~thr_w2[1] & thr_w2[0];
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assign thr1_w2 = ~thr_w2[1] & thr_w2[0];
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assign thr2_w2 = thr_w2[1] & ~thr_w2[0];
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assign thr2_w2 = thr_w2[1] & ~thr_w2[0];
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| Line 215... |
Line 220... |
.sel1(wen_thr3_w2), .sel2(wen_thr3_l),
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.sel1(wen_thr3_w2), .sel2(wen_thr3_l),
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.in0(exu_ifu_cc_w[7:0]),
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.in0(exu_ifu_cc_w[7:0]),
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.in1(divcntl_ccr_cc_w2[7:0]), .in2(ccr_thr3[7:0]));
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.in1(divcntl_ccr_cc_w2[7:0]), .in2(ccr_thr3[7:0]));
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// store new value
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// store new value
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dff #(8) dff_ccr_thr0(.din(ccrin_thr0[7:0]), .clk(clk), .q(ccr_thr0[7:0]),
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dff_s #(8) dff_ccr_thr0(.din(ccrin_thr0[7:0]), .clk(clk), .q(ccr_thr0[7:0]),
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.se(se), .si(), .so());
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.se(se), `SIMPLY_RISC_SCANIN, .so());
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dff #(8) dff_ccr_thr1(.din(ccrin_thr1[7:0]), .clk(clk), .q(ccr_thr1[7:0]),
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dff_s #(8) dff_ccr_thr1(.din(ccrin_thr1[7:0]), .clk(clk), .q(ccr_thr1[7:0]),
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.se(se), .si(), .so());
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.se(se), `SIMPLY_RISC_SCANIN, .so());
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dff #(8) dff_ccr_thr2(.din(ccrin_thr2[7:0]), .clk(clk), .q(ccr_thr2[7:0]),
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dff_s #(8) dff_ccr_thr2(.din(ccrin_thr2[7:0]), .clk(clk), .q(ccr_thr2[7:0]),
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.se(se), .si(), .so());
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.se(se), `SIMPLY_RISC_SCANIN, .so());
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dff #(8) dff_ccr_thr3(.din(ccrin_thr3[7:0]), .clk(clk), .q(ccr_thr3[7:0]),
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dff_s #(8) dff_ccr_thr3(.din(ccrin_thr3[7:0]), .clk(clk), .q(ccr_thr3[7:0]),
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.se(se), .si(), .so());
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.se(se), `SIMPLY_RISC_SCANIN, .so());
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// mux between the 4 sets of ccrs
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// mux between the 4 sets of ccrs
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mux4ds #(8) mux_ccr_out(.dout(ccr_d[7:0]), .sel0(thrdec_d[0]),
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mux4ds #(8) mux_ccr_out(.dout(ccr_d[7:0]), .sel0(thrdec_d[0]),
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.sel1(thrdec_d[1]), .sel2(thrdec_d[2]),
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.sel1(thrdec_d[1]), .sel2(thrdec_d[2]),
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.sel3(thrdec_d[3]), .in0(ccr_thr0[7:0]),
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.sel3(thrdec_d[3]), .in0(ccr_thr0[7:0]),
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.in1(ccr_thr1[7:0]), .in2(ccr_thr2[7:0]),
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.in1(ccr_thr1[7:0]), .in2(ccr_thr2[7:0]),
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.in3(ccr_thr3[7:0]));
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.in3(ccr_thr3[7:0]));
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// !`ifdef FPGA_SYN_1THREAD
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`endif // !`ifdef FPGA_SYN_1THREAD
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// bypass the ccs to the output. Only alu result needs to be bypassed
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// bypass the ccs to the output. Only alu result needs to be bypassed
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assign exu_ifu_cc_d[7:0] = (use_cc_e)? alu_cc_e[7:0]: partial_cc_d[7:0];
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assign exu_ifu_cc_d[7:0] = (use_cc_e)? alu_cc_e[7:0]: partial_cc_d[7:0];
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mux3ds #(8) mux_ccr_bypass1(.dout(partial_cc_d[7:0]),
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mux3ds #(8) mux_ccr_bypass1(.dout(partial_cc_d[7:0]),
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.sel0(use_ccr),
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.sel0(use_ccr),
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