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// You should have received a copy of the GNU General Public
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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//
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// ========== Copyright Header End ============================================
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// ========== Copyright Header End ============================================
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`ifdef SIMPLY_RISC_TWEAKS
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`define SIMPLY_RISC_SCANIN .si(0)
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`else
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`define SIMPLY_RISC_SCANIN .si()
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`endif
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module sparc_exu_reg (/*AUTOARG*/
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module sparc_exu_reg (/*AUTOARG*/
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// Outputs
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// Outputs
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data_out,
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data_out,
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// Inputs
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// Inputs
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clk, se, thr_out, wen_w, thr_w, data_in_w
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clk, se, thr_out, wen_w, thr_w, data_in_w
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wire wen_thr3_w;
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wire wen_thr3_w;
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//////////////////////////////////
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//////////////////////////////////
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// Output selection for reg
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// Output selection for reg
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//////////////////////////////////
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//////////////////////////////////
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`ifdef FPGA_SYN_1THREAD
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assign data_out[SIZE -1:0] = data_thr0[SIZE -1:0];
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assign wen_thr0_w = (thr_w[0] & wen_w);
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// mux between new and current value
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mux2ds #(SIZE) data_next0_mux(.dout(data_thr0_next[SIZE -1:0]),
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.in0(data_thr0[SIZE -1:0]),
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.in1(data_in_w[SIZE -1:0]),
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.sel0(~wen_thr0_w),
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.sel1(wen_thr0_w));
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dff_s #(SIZE) dff_reg_thr0(.din(data_thr0_next[SIZE -1:0]), .clk(clk), .q(data_thr0[SIZE -1:0]),
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.se(se), `SIMPLY_RISC_SCANIN, .so());
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// !`ifdef FPGA_SYN_1THREAD
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`else // !`ifdef FPGA_SYN_1THREAD
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// mux between the 4 regs
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// mux between the 4 regs
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mux4ds #(SIZE) mux_data_out1(.dout(data_out[SIZE -1:0]), .sel0(thr_out[0]),
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mux4ds #(SIZE) mux_data_out1(.dout(data_out[SIZE -1:0]), .sel0(thr_out[0]),
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.sel1(thr_out[1]), .sel2(thr_out[2]),
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.sel1(thr_out[1]), .sel2(thr_out[2]),
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.sel3(thr_out[3]), .in0(data_thr0[SIZE -1:0]),
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.sel3(thr_out[3]), .in0(data_thr0[SIZE -1:0]),
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.in1(data_in_w[SIZE -1:0]),
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.in1(data_in_w[SIZE -1:0]),
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.sel0(~wen_thr3_w),
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.sel0(~wen_thr3_w),
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.sel1(wen_thr3_w));
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.sel1(wen_thr3_w));
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// store new value
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// store new value
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dff #(SIZE) dff_reg_thr0(.din(data_thr0_next[SIZE -1:0]), .clk(clk), .q(data_thr0[SIZE -1:0]),
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dff_s #(SIZE) dff_reg_thr0(.din(data_thr0_next[SIZE -1:0]), .clk(clk), .q(data_thr0[SIZE -1:0]),
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.se(se), .si(), .so());
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.se(se), `SIMPLY_RISC_SCANIN, .so());
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dff #(SIZE) dff_reg_thr1(.din(data_thr1_next[SIZE -1:0]), .clk(clk), .q(data_thr1[SIZE -1:0]),
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dff_s #(SIZE) dff_reg_thr1(.din(data_thr1_next[SIZE -1:0]), .clk(clk), .q(data_thr1[SIZE -1:0]),
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.se(se), .si(), .so());
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.se(se), `SIMPLY_RISC_SCANIN, .so());
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dff #(SIZE) dff_reg_thr2(.din(data_thr2_next[SIZE -1:0]), .clk(clk), .q(data_thr2[SIZE -1:0]),
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dff_s #(SIZE) dff_reg_thr2(.din(data_thr2_next[SIZE -1:0]), .clk(clk), .q(data_thr2[SIZE -1:0]),
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.se(se), .si(), .so());
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.se(se), `SIMPLY_RISC_SCANIN, .so());
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dff #(SIZE) dff_reg_thr3(.din(data_thr3_next[SIZE -1:0]), .clk(clk), .q(data_thr3[SIZE -1:0]),
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dff_s #(SIZE) dff_reg_thr3(.din(data_thr3_next[SIZE -1:0]), .clk(clk), .q(data_thr3[SIZE -1:0]),
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.se(se), .si(), .so());
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.se(se), `SIMPLY_RISC_SCANIN, .so());
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// !`ifdef FPGA_SYN_1THREAD
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`endif // !`ifdef FPGA_SYN_1THREAD
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endmodule // sparc_exu_reg
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endmodule // sparc_exu_reg
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