Line 17... |
Line 17... |
// License along with this work; if not, write to the Free Software
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// License along with this work; if not, write to the Free Software
|
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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//
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// ========== Copyright Header End ============================================
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// ========== Copyright Header End ============================================
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
|
|
`ifdef SIMPLY_RISC_TWEAKS
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|
`define SIMPLY_RISC_SCANIN .si(0)
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`else
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`define SIMPLY_RISC_SCANIN .si()
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`endif
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/*
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/*
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// Module Name: sparc_ffu_ctl
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// Module Name: sparc_ffu_ctl
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// Description: This is the ffu control block.
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// Description: This is the ffu control block.
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*/
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*/
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/*
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`include "iop.h"
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/* ========== Copyright Header Begin ==========================================
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`define FSR_NVA 9
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*
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`define FSR_OFA 8
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* OpenSPARC T1 Processor File: iop.h
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`define FSR_UFA 7
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* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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`define FSR_DZA 6
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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`define FSR_NXA 5
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*
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`define FSR_NVC 4
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* The above named program is free software; you can redistribute it and/or
|
`define FSR_OFC 3
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* modify it under the terms of the GNU General Public
|
`define FSR_UFC 2
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* License version 2 as published by the Free Software Foundation.
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`define FSR_DZC 1
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*
|
`define FSR_NXC 0
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* The above named program is distributed in the hope that it will be
|
|
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
|
* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public
|
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* License along with this work; if not, write to the Free Software
|
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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*
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* ========== Copyright Header End ============================================
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*/
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//-*- verilog -*-
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////////////////////////////////////////////////////////////////////////
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/*
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//
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// Description: Global header file that contain definitions that
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// are common/shared at the IOP chip level
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*/
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////////////////////////////////////////////////////////////////////////
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// Address Map Defines
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// ===================
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// CMP space
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// IOP space
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//`define ENET_ING_CSR 8'h84
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//`define ENET_EGR_CMD_CSR 8'h85
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// L2 space
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// More IOP space
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//Cache Crossbar Width and Field Defines
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//======================================
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//bits 133:128 are shared by different fields
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//for different packet types.
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//End cache crossbar defines
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// Number of COS supported by EECU
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//
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// BSC bus sizes
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// =============
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//
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// General
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// CTags
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// reinstated temporarily
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// CoS
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// L2$ Bank
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// L2$ Req
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// L2$ Ack
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// Enet Egress Command Unit
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// Enet Egress Packet Unit
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// This is cleaved in between Egress Datapath Ack's
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// Enet Egress Datapath
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// In-Order / Ordered Queue: EEPU
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// Tag is: TLEN, SOF, EOF, QID = 15
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// Nack + Tag Info + CTag
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// ENET Ingress Queue Management Req
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// ENET Ingress Queue Management Ack
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// Enet Ingress Packet Unit
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// ENET Ingress Packet Unit Ack
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// In-Order / Ordered Queue: PCI
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// Tag is: CTAG
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// PCI-X Request
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// PCI_X Acknowledge
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//
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// BSC array sizes
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//================
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//
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// ECC syndrome bits per memory element
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//
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// BSC Port Definitions
|
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// ====================
|
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//
|
|
// Bits 7 to 4 of curr_port_id
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// Number of ports of each type
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// Bits needed to represent above
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// How wide the linked list pointers are
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// 60b for no payload (2CoS)
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// 80b for payload (2CoS)
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|
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//`define BSC_OBJ_PTR 80
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//`define BSC_HD1_HI 69
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//`define BSC_HD1_LO 60
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//`define BSC_TL1_HI 59
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//`define BSC_TL1_LO 50
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//`define BSC_CT1_HI 49
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//`define BSC_CT1_LO 40
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//`define BSC_HD0_HI 29
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//`define BSC_HD0_LO 20
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//`define BSC_TL0_HI 19
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//`define BSC_TL0_LO 10
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//`define BSC_CT0_HI 9
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//`define BSC_CT0_LO 0
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// I2C STATES in DRAMctl
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//
|
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// IOB defines
|
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// ===========
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//
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//`define IOB_INT_STAT_WIDTH 32
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//`define IOB_INT_STAT_HI 31
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//`define IOB_INT_STAT_LO 0
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// fixme - double check address mapping
|
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// CREG in `IOB_INT_CSR space
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// CREG in `IOB_MAN_CSR space
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// Address map for TAP access of SPARC ASI
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//
|
|
// CIOP UCB Bus Width
|
|
// ==================
|
|
//
|
|
//`define IOB_EECU_WIDTH 16 // ethernet egress command
|
|
//`define EECU_IOB_WIDTH 16
|
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|
|
//`define IOB_NRAM_WIDTH 16 // NRAM (RLDRAM previously)
|
|
//`define NRAM_IOB_WIDTH 4
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//`define IOB_ENET_ING_WIDTH 32 // ethernet ingress
|
|
//`define ENET_ING_IOB_WIDTH 8
|
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|
|
//`define IOB_ENET_EGR_WIDTH 4 // ethernet egress
|
|
//`define ENET_EGR_IOB_WIDTH 4
|
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|
//`define IOB_ENET_MAC_WIDTH 4 // ethernet MAC
|
|
//`define ENET_MAC_IOB_WIDTH 4
|
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//`define IOB_BSC_WIDTH 4 // BSC
|
|
//`define BSC_IOB_WIDTH 4
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//`define IOB_CLSP_WIDTH 4 // clk spine unit
|
|
//`define CLSP_IOB_WIDTH 4
|
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//
|
|
// CIOP UCB Buf ID Type
|
|
// ====================
|
|
//
|
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|
|
//
|
|
// Interrupt Device ID
|
|
// ===================
|
|
//
|
|
// Caution: DUMMY_DEV_ID has to be 9 bit wide
|
|
// for fields to line up properly in the IOB.
|
|
|
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|
//
|
|
// Soft Error related definitions
|
|
// ==============================
|
|
//
|
|
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|
|
//
|
|
// CMP clock
|
|
// =========
|
|
//
|
|
|
|
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|
|
//
|
|
// NRAM/IO Interface
|
|
// =================
|
|
//
|
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//
|
|
// NRAM/ENET Interface
|
|
// ===================
|
|
//
|
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//
|
|
// IO/FCRAM Interface
|
|
// ==================
|
|
//
|
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|
|
|
//
|
|
// PCI Interface
|
|
// ==================
|
|
// Load/store size encodings
|
|
// -------------------------
|
|
// Size encoding
|
|
// 000 - byte
|
|
// 001 - half-word
|
|
// 010 - word
|
|
// 011 - double-word
|
|
// 100 - quad
|
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|
//
|
|
// JBI<->SCTAG Interface
|
|
// =======================
|
|
// Outbound Header Format
|
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|
// Inbound Header Format
|
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//
|
|
// JBI->IOB Mondo Header Format
|
|
// ============================
|
|
//
|
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|
|
// JBI->IOB Mondo Bus Width/Cycle
|
|
// ==============================
|
|
// Cycle 1 Header[15:8]
|
|
// Cycle 2 Header[ 7:0]
|
|
// Cycle 3 J_AD[127:120]
|
|
// Cycle 4 J_AD[119:112]
|
|
// .....
|
|
// Cycle 18 J_AD[ 7: 0]
|
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|
|
module sparc_ffu_ctl (/*AUTOARG*/
|
module sparc_ffu_ctl (/*AUTOARG*/
|
// Outputs
|
// Outputs
|
ffu_exu_rsr_data_mid_m, ffu_exu_rsr_data_lo_m,
|
ffu_exu_rsr_data_mid_m, ffu_exu_rsr_data_lo_m,
|
Line 1484... |
Line 651... |
assign clk = rclk;
|
assign clk = rclk;
|
// Reset flop
|
// Reset flop
|
dffrl_async rstff(.din (grst_l),
|
dffrl_async rstff(.din (grst_l),
|
.q (ffu_reset_l),
|
.q (ffu_reset_l),
|
.clk (clk),
|
.clk (clk),
|
.rst_l (arst_l), .si(), .so(), .se(se));
|
.rst_l (arst_l), `SIMPLY_RISC_SCANIN, .so(), .se(se));
|
assign ctl_dp_rst_l = ffu_reset_l;
|
assign ctl_dp_rst_l = ffu_reset_l;
|
assign reset = ~ffu_reset_l;
|
assign reset = ~ffu_reset_l;
|
// Stage cpx data by one cycle
|
// Stage cpx data by one cycle
|
dff #(13) cpx_dff(.din({cpx_vld, cpx_fcmp, cpx_req[3:0], cpx_fccval[1:0], cpx_fpexc[4:0]}),
|
dff_s #(13) cpx_dff(.din({cpx_vld, cpx_fcmp, cpx_req[3:0], cpx_fccval[1:0], cpx_fpexc[4:0]}),
|
.q({cpx_vld_d1, cpx_fcmp_d1, cpx_req_d1[3:0], cpx_fccval_d1[1:0], cpx_fpexc_d1[4:0]}),
|
.q({cpx_vld_d1, cpx_fcmp_d1, cpx_req_d1[3:0], cpx_fccval_d1[1:0], cpx_fpexc_d1[4:0]}),
|
.clk(clk), .se(se), .si(), .so());
|
.clk(clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff #(3) lsu_bld_cnt1_dff(.din({lsu_ffu_bld_cnt_w[2:0]}), .clk(clk),
|
dff_s #(3) lsu_bld_cnt1_dff(.din({lsu_ffu_bld_cnt_w[2:0]}), .clk(clk),
|
.q({bld_cnt_d1[2:0]}), .se(se), .si(), .so());
|
.q({bld_cnt_d1[2:0]}), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff #(3) lsu_bld_cnt2_dff(.din({bld_cnt_d1[2:0]}), .clk(clk),
|
dff_s #(3) lsu_bld_cnt2_dff(.din({bld_cnt_d1[2:0]}), .clk(clk),
|
.q({bld_cnt_d2[2:0]}), .se(se), .si(), .so());
|
.q({bld_cnt_d2[2:0]}), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff #(3) lsu_bld_cnt3_dff(.din({bld_cnt_d2[2:0]}), .clk(clk),
|
dff_s #(3) lsu_bld_cnt3_dff(.din({bld_cnt_d2[2:0]}), .clk(clk),
|
.q({bld_cnt_d3[2:0]}), .se(se), .si(), .so());
|
.q({bld_cnt_d3[2:0]}), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
//----------------------------------------
|
//----------------------------------------
|
// Decode Instruction From IFU
|
// Decode Instruction From IFU
|
//----------------------------------------
|
//----------------------------------------
|
dff #(3) fpop_d2e(.din({ifu_ffu_fpop1_d, ifu_ffu_fpop2_d, ifu_ffu_visop_d}), .clk(clk),
|
dff_s #(3) fpop_d2e(.din({ifu_ffu_fpop1_d, ifu_ffu_fpop2_d, ifu_ffu_visop_d}), .clk(clk),
|
.q({fpop1_e, fpop2_e, visop_e}), .se(se), .si(), .so());
|
.q({fpop1_e, fpop2_e, visop_e}), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
assign fpop1_next = (any_op_e | reset)? fpop1_e: fpop1;
|
assign fpop1_next = (any_op_e | reset)? fpop1_e: fpop1;
|
assign fpop2_next = (any_op_e | reset)? fpop2_e: fpop2;
|
assign fpop2_next = (any_op_e | reset)? fpop2_e: fpop2;
|
assign visop_next = (any_op_e | reset)? visop_e: visop;
|
assign visop_next = (any_op_e | reset)? visop_e: visop;
|
dff #(3) fpop_dff(.din({fpop1_next,fpop2_next,visop_next}),
|
dff_s #(3) fpop_dff(.din({fpop1_next,fpop2_next,visop_next}),
|
.q({fpop1,fpop2,visop}),
|
.q({fpop1,fpop2,visop}),
|
.clk(clk), .se(se), .si(), .so());
|
.clk(clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign fpop_size_0 = ~opf[1] & ~opf[0];
|
assign fpop_size_0 = ~opf[1] & ~opf[0];
|
assign fpop_size_1 = ~opf[1] & opf[0];
|
assign fpop_size_1 = ~opf[1] & opf[0];
|
|
|
assign fpop_low_1 = ~opf[3] & ~opf[2] & ~opf[1] & opf[0];
|
assign fpop_low_1 = ~opf[3] & ~opf[2] & ~opf[1] & opf[0];
|
Line 1583... |
Line 750... |
(fst_e | fld_e) & ldst_single_e);
|
(fst_e | fld_e) & ldst_single_e);
|
|
|
assign unimpl_op_all_e = (unimpl_op_e | ifu_ffu_quad_op_e |
|
assign unimpl_op_all_e = (unimpl_op_e | ifu_ffu_quad_op_e |
|
illegal_rs1_e | illegal_field_e);
|
illegal_rs1_e | illegal_field_e);
|
|
|
dff #1 qopm_ff(.din (unimpl_op_all_e),
|
dff_s #1 qopm_ff(.din (unimpl_op_all_e),
|
.q (unimpl_op_m),
|
.q (unimpl_op_m),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff #1 qopw_ff(.din (unimpl_op_m),
|
dff_s #1 qopw_ff(.din (unimpl_op_m),
|
.q (unimpl_op_w),
|
.q (unimpl_op_w),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
assign unimpl_qual_w = unimpl_op_w & ~kill_unimpl_w;
|
assign unimpl_qual_w = unimpl_op_w & ~kill_unimpl_w;
|
assign unimpl_qual_w2 = unimpl_op_w2 & ~flush_w2;
|
assign unimpl_qual_w2 = unimpl_op_w2 & ~flush_w2;
|
|
|
dff #1 qopw2_ff(.din (unimpl_qual_w),
|
dff_s #1 qopw2_ff(.din (unimpl_qual_w),
|
.q (unimpl_op_w2),
|
.q (unimpl_op_w2),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
|
|
// Decode register encoding (bit[5] wrapped to bit[0] for non singles)
|
// Decode register encoding (bit[5] wrapped to bit[0] for non singles)
|
// Also the storage is flopped around so odd regs are at even addresses
|
// Also the storage is flopped around so odd regs are at even addresses
|
// in the regfile for singles. this helps because everything external
|
// in the regfile for singles. this helps because everything external
|
Line 1656... |
Line 823... |
// >>>>> added ~kill_fp
|
// >>>>> added ~kill_fp
|
// set these in e so that kill_fp doesn't kill spuriously
|
// set these in e so that kill_fp doesn't kill spuriously
|
assign load_pending_next = fld_e | // set
|
assign load_pending_next = fld_e | // set
|
(load_pending & ~lsu_ffu_ld_vld & ~kill_fp & ~blk_ld_m);
|
(load_pending & ~lsu_ffu_ld_vld & ~kill_fp & ~blk_ld_m);
|
assign fld_done = lsu_ffu_ld_vld & ~kill_fp & load_pending;
|
assign fld_done = lsu_ffu_ld_vld & ~kill_fp & load_pending;
|
dffr ldpend_dff(.din (load_pending_next),
|
dffr_s ldpend_dff(.din (load_pending_next),
|
.q (load_pending),
|
.q (load_pending),
|
.clk (clk),
|
.clk (clk),
|
.rst (reset),
|
.rst (reset),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign blk_ld_m = fld_m & blk_asi_m;
|
assign blk_ld_m = fld_m & blk_asi_m;
|
assign blk_ld_done = lsu_ffu_ld_vld & ~kill_fp & (bld_cnt_d1[2:0] == 3'b111) & blk_load_pending;
|
assign blk_ld_done = lsu_ffu_ld_vld & ~kill_fp & (bld_cnt_d1[2:0] == 3'b111) & blk_load_pending;
|
assign blk_load_pending_next = (blk_ld_m & ~kill_m) | // set
|
assign blk_load_pending_next = (blk_ld_m & ~kill_m) | // set
|
(blk_load_pending & ~kill_fp & ~ffu_ifu_fpop_done_w2);
|
(blk_load_pending & ~kill_fp & ~ffu_ifu_fpop_done_w2);
|
dffr blk_ldpend_dff(.din(blk_load_pending_next),
|
dffr_s blk_ldpend_dff(.din(blk_load_pending_next),
|
.q(blk_load_pending),
|
.q(blk_load_pending),
|
.clk(clk),
|
.clk(clk),
|
.rst(reset),
|
.rst(reset),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign fp_pending_next = fpu_op_e | // set
|
assign fp_pending_next = fpu_op_e | // set
|
(fp_pending & ~is_fpu_result & ~kill_fp);
|
(fp_pending & ~is_fpu_result & ~kill_fp);
|
dffr fppend_dff(.din(fp_pending_next),
|
dffr_s fppend_dff(.din(fp_pending_next),
|
.q(fp_pending),
|
.q(fp_pending),
|
.clk(clk),
|
.clk(clk),
|
.rst (reset),
|
.rst (reset),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// rs1
|
// rs1
|
dff #(5) rs1_d2e(.din(ifu_ffu_frs1_d[4:0]), .clk(clk), .q(frs1_e[4:0]), .se(se), .si(), .so());
|
dff_s #(5) rs1_d2e(.din(ifu_ffu_frs1_d[4:0]), .clk(clk), .q(frs1_e[4:0]), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
mux2ds #(6) rs1_mux(.dout (rs1_next[5:0]),
|
mux2ds #(6) rs1_mux(.dout (rs1_next[5:0]),
|
.in0 (rs1[5:0]),
|
.in0 (rs1[5:0]),
|
.in1 (rs1_e[5:0]),
|
.in1 (rs1_e[5:0]),
|
.sel0 (~any_op_e),
|
.sel0 (~any_op_e),
|
.sel1 (any_op_e));
|
.sel1 (any_op_e));
|
dff #(6) rs1_dff(.din(rs1_next[5:0]),
|
dff_s #(6) rs1_dff(.din(rs1_next[5:0]),
|
.clk(clk),
|
.clk(clk),
|
.q(rs1[5:0]),
|
.q(rs1[5:0]),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
// rs2
|
// rs2
|
dff #(5) rs2_d2e(.din(ifu_ffu_frs2_d[4:0]), .clk(clk), .q(frs2_e[4:0]), .se(se), .si(), .so());
|
dff_s #(5) rs2_d2e(.din(ifu_ffu_frs2_d[4:0]), .clk(clk), .q(frs2_e[4:0]), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
mux2ds #(6) rs2_mux(.dout(rs2_next[5:0]),
|
mux2ds #(6) rs2_mux(.dout(rs2_next[5:0]),
|
.in0 (rs2[5:0]),
|
.in0 (rs2[5:0]),
|
.in1 (rs2_e[5:0]),
|
.in1 (rs2_e[5:0]),
|
.sel0(~any_op_e),
|
.sel0(~any_op_e),
|
.sel1 (any_op_e));
|
.sel1 (any_op_e));
|
dff #(6) rs2_dff(.din (rs2_next[5:0]),
|
dff_s #(6) rs2_dff(.din (rs2_next[5:0]),
|
.clk (clk),
|
.clk (clk),
|
.q (rs2[5:0]),
|
.q (rs2[5:0]),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
// rd
|
// rd
|
dff #(6) rd_d2e(.din({ifu_ffu_ldst_single_d,ifu_ffu_frd_d[4:0]}), .clk(clk),
|
dff_s #(6) rd_d2e(.din({ifu_ffu_ldst_single_d,ifu_ffu_frd_d[4:0]}), .clk(clk),
|
.q({ldst_single_e,frd_e[4:0]}),
|
.q({ldst_single_e,frd_e[4:0]}),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
mux2ds #(6) rd_mux(.dout (rd_next[5:0]),
|
mux2ds #(6) rd_mux(.dout (rd_next[5:0]),
|
.in0 (rd[5:0]),
|
.in0 (rd[5:0]),
|
.in1 (rd_e[5:0]),
|
.in1 (rd_e[5:0]),
|
.sel0 (~any_op_e),
|
.sel0 (~any_op_e),
|
.sel1 (any_op_e));
|
.sel1 (any_op_e));
|
dff #(6) rd_dff(.din (rd_next[5:0]),
|
dff_s #(6) rd_dff(.din (rd_next[5:0]),
|
.clk (clk),
|
.clk (clk),
|
.q (rd[5:0]),
|
.q (rd[5:0]),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
// rs size
|
// rs size
|
mux2ds source_single_mux(.dout (source_single_next),
|
mux2ds source_single_mux(.dout (source_single_next),
|
.in0 (source_single),
|
.in0 (source_single),
|
.in1 (source_single_e),
|
.in1 (source_single_e),
|
.sel0(~any_op_e),
|
.sel0(~any_op_e),
|
.sel1 (any_op_e));
|
.sel1 (any_op_e));
|
dff source_single_dff(.din(source_single_next),
|
dff_s source_single_dff(.din(source_single_next),
|
.clk(clk),
|
.clk(clk),
|
.q(source_single),
|
.q(source_single),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
// rd size
|
// rd size
|
assign dest_single_next = (any_op_e)? dest_single_e: dest_single;
|
assign dest_single_next = (any_op_e)? dest_single_e: dest_single;
|
dff dest_single_dff(.din (dest_single_next),
|
dff_s dest_single_dff(.din (dest_single_next),
|
.clk (clk),
|
.clk (clk),
|
.q (dest_single),
|
.q (dest_single),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
// thread
|
// thread
|
mux2ds #(2) tid_mux(.dout (tid_next[1:0]),
|
mux2ds #(2) tid_mux(.dout (tid_next[1:0]),
|
.in0 (tid[1:0]),
|
.in0 (tid[1:0]),
|
.in1 (tid_e[1:0]),
|
.in1 (tid_e[1:0]),
|
.sel0 (~any_op_e),
|
.sel0 (~any_op_e),
|
.sel1 (any_op_e));
|
.sel1 (any_op_e));
|
dff #(2) tid_dff(.din(tid_next[1:0]),
|
dff_s #(2) tid_dff(.din(tid_next[1:0]),
|
.clk(clk),
|
.clk(clk),
|
.q(tid[1:0]),
|
.q(tid[1:0]),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
// extra tid to help fanout for critical signals
|
// extra tid to help fanout for critical signals
|
dff #(2) extra_tid_dff(.din(tid_next[1:0]),
|
dff_s #(2) extra_tid_dff(.din(tid_next[1:0]),
|
.clk(clk), .q(extra_tid[1:0]), .se(se), .si(), .so());
|
.clk(clk), .q(extra_tid[1:0]), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
// fcc num
|
// fcc num
|
mux2ds #(2) fcc_mux(.dout (fcc_num_next[1:0]),
|
mux2ds #(2) fcc_mux(.dout (fcc_num_next[1:0]),
|
.in0 (fcc_num[1:0]),
|
.in0 (fcc_num[1:0]),
|
.in1 (ifu_ffu_fcc_num_d[1:0]),
|
.in1 (ifu_ffu_fcc_num_d[1:0]),
|
.sel0 (~is_fpop_d),
|
.sel0 (~is_fpop_d),
|
.sel1 (is_fpop_d));
|
.sel1 (is_fpop_d));
|
dff #(2) fcc_dff(.din (fcc_num_next[1:0]),
|
dff_s #(2) fcc_dff(.din (fcc_num_next[1:0]),
|
.clk (clk),
|
.clk (clk),
|
.q (fcc_num[1:0]),
|
.q (fcc_num[1:0]),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// ldfsr
|
// ldfsr
|
mux2ds #(2) ldfsr_mux(.dout (ldfsr_next[1:0]),
|
mux2ds #(2) ldfsr_mux(.dout (ldfsr_next[1:0]),
|
.in0 ({ldfsr, ldxfsr}),
|
.in0 ({ldfsr, ldxfsr}),
|
.in1 ({ifu_ffu_ldfsr_d, ifu_ffu_ldxfsr_d}),
|
.in1 ({ifu_ffu_ldfsr_d, ifu_ffu_ldxfsr_d}),
|
.sel0 (~ifu_ffu_fld_d),
|
.sel0 (~ifu_ffu_fld_d),
|
.sel1 (ifu_ffu_fld_d));
|
.sel1 (ifu_ffu_fld_d));
|
dff #(2) ldfsr_dff(.din (ldfsr_next[1:0]),
|
dff_s #(2) ldfsr_dff(.din (ldfsr_next[1:0]),
|
.clk (clk),
|
.clk (clk),
|
.q ({ldfsr, ldxfsr}),
|
.q ({ldfsr, ldxfsr}),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// op code
|
// op code
|
mux2ds #(9) opf_mux(.dout (opf_next[8:0]),
|
mux2ds #(9) opf_mux(.dout (opf_next[8:0]),
|
.in0 (opf[8:0]),
|
.in0 (opf[8:0]),
|
.in1 (ifu_ffu_fpopcode_d[8:0]),
|
.in1 (ifu_ffu_fpopcode_d[8:0]),
|
.sel0 (~is_fpop_d),
|
.sel0 (~is_fpop_d),
|
.sel1 (is_fpop_d));
|
.sel1 (is_fpop_d));
|
dff #(9) opf_dff(.din(opf_next[8:0]),
|
dff_s #(9) opf_dff(.din(opf_next[8:0]),
|
.clk(clk),
|
.clk(clk),
|
.q(opf[8:0]),
|
.q(opf[8:0]),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
//----------
|
//----------
|
// FP Pipe
|
// FP Pipe
|
//----------
|
//----------
|
dff fop_e2m(.din(any_op_e), .clk(clk),
|
dff_s fop_e2m(.din(any_op_e), .clk(clk),
|
.q(any_op_m),
|
.q(any_op_m),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff fop_m2w(.din(any_op_m_valid), .clk(clk),
|
dff_s fop_m2w(.din(any_op_m_valid), .clk(clk),
|
.q(any_op_w),
|
.q(any_op_w),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff fop_w2w2(.din(any_op_w), .clk(clk),
|
dff_s fop_w2w2(.din(any_op_w), .clk(clk),
|
.q(any_op_w2),
|
.q(any_op_w2),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff fst_d2e(.din(ifu_ffu_fst_d), .clk(clk),
|
dff_s fst_d2e(.din(ifu_ffu_fst_d), .clk(clk),
|
.q (fst_e),
|
.q (fst_e),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff fst_e2m(.din(fst_e), .clk(clk),
|
dff_s fst_e2m(.din(fst_e), .clk(clk),
|
.q (fst_m),
|
.q (fst_m),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff fst_m2w(.din(fst_m), .clk(clk),
|
dff_s fst_m2w(.din(fst_m), .clk(clk),
|
.q (fst_w),
|
.q (fst_w),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff fld_d2e(.din(ifu_ffu_fld_d), .clk(clk),
|
dff_s fld_d2e(.din(ifu_ffu_fld_d), .clk(clk),
|
.q (fld_e),
|
.q (fld_e),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff fld_e2m(.din(fld_e), .clk(clk),
|
dff_s fld_e2m(.din(fld_e), .clk(clk),
|
.q (fld_m),
|
.q (fld_m),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff ren_rs2_e2m(.din(ren_rs2_e_vld), .clk(clk),
|
dff_s ren_rs2_e2m(.din(ren_rs2_e_vld), .clk(clk),
|
.q(ren_rs2_m),
|
.q(ren_rs2_m),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff ren_rs2_m2w(.din(ren_rs2_m_vld), .clk(clk),
|
dff_s ren_rs2_m2w(.din(ren_rs2_m_vld), .clk(clk),
|
.q(ren_rs2_w),
|
.q(ren_rs2_w),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff ren_rs2_w2w2(.din(ren_rs2_w), .clk(clk),
|
dff_s ren_rs2_w2w2(.din(ren_rs2_w), .clk(clk),
|
.q(ren_rs2_w2),
|
.q(ren_rs2_w2),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff ren_rs2_w22w3(.din(ren_rs2_w2), .clk(clk),
|
dff_s ren_rs2_w22w3(.din(ren_rs2_w2), .clk(clk),
|
.q(ren_rs2_w3),
|
.q(ren_rs2_w3),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff ren_rs2_w32w4(.din(ren_rs2_w3), .clk(clk),
|
dff_s ren_rs2_w32w4(.din(ren_rs2_w3), .clk(clk),
|
.q(ren_rs2_w4),
|
.q(ren_rs2_w4),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff ren_rs1_e2m(.din(ren_rs1_e), .clk(clk),
|
dff_s ren_rs1_e2m(.din(ren_rs1_e), .clk(clk),
|
.q(ren_rs1_m),
|
.q(ren_rs1_m),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff ren_rs1_m2w(.din(ren_rs1_m), .clk(clk),
|
dff_s ren_rs1_m2w(.din(ren_rs1_m), .clk(clk),
|
.q(ren_rs1_w),
|
.q(ren_rs1_w),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff ren_rs1_w2w2(.din(ren_rs1_w_vld), .clk(clk),
|
dff_s ren_rs1_w2w2(.din(ren_rs1_w_vld), .clk(clk),
|
.q(ren_rs1_w2),
|
.q(ren_rs1_w2),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff ren_rs1_w22w3(.din(ren_rs1_w2_vld), .clk(clk),
|
dff_s ren_rs1_w22w3(.din(ren_rs1_w2_vld), .clk(clk),
|
.q(ren_rs1_w3),
|
.q(ren_rs1_w3),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff ren_rs1_w32w4(.din(ren_rs1_w3), .clk(clk),
|
dff_s ren_rs1_w32w4(.din(ren_rs1_w3), .clk(clk),
|
.q(ren_rs1_w4),
|
.q(ren_rs1_w4),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff ren_rs1_w42w5(.din(ren_rs1_w4), .clk(clk),
|
dff_s ren_rs1_w42w5(.din(ren_rs1_w4), .clk(clk),
|
.q(ren_rs1_w5),
|
.q(ren_rs1_w5),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff cond_move_e2m(.din(cond_move_e), .clk(clk),
|
dff_s cond_move_e2m(.din(cond_move_e), .clk(clk),
|
.q(cond_move_m),
|
.q(cond_move_m),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff move_e2m(.din(move_e), .clk(clk),
|
dff_s move_e2m(.din(move_e), .clk(clk),
|
.q(move_m),
|
.q(move_m),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff move_m2w(.din(move_m_valid), .clk(clk),
|
dff_s move_m2w(.din(move_m_valid), .clk(clk),
|
.q(move_w),
|
.q(move_w),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff move_wen_m2w(.din(move_wen_m), .clk(clk), .q(move_wen_w),
|
dff_s move_wen_m2w(.din(move_wen_m), .clk(clk), .q(move_wen_w),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff move_wen_w2w2(.din(move_wen_w), .clk(clk), .q(move_wen_w2),
|
dff_s move_wen_w2w2(.din(move_wen_w), .clk(clk), .q(move_wen_w2),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff move_wdff(.din(move_w_valid), .clk(clk), .q(move_w2), .se(se), .si(), .so());
|
dff_s move_wdff(.din(move_w_valid), .clk(clk), .q(move_w2), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff stfsr_d2e(.din(ifu_ffu_stfsr_d),
|
dff_s stfsr_d2e(.din(ifu_ffu_stfsr_d),
|
.q(stfsr_e),
|
.q(stfsr_e),
|
.clk(clk),
|
.clk(clk),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff fpu_op_e2m(.din(fpu_op_e), .clk(clk),
|
dff_s fpu_op_e2m(.din(fpu_op_e), .clk(clk),
|
.q(fpu_op_m),
|
.q(fpu_op_m),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff fpu_op_m2w(.din(fpu_op_m), .clk(clk),
|
dff_s fpu_op_m2w(.din(fpu_op_m), .clk(clk),
|
.q(fpu_op_w),
|
.q(fpu_op_w),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff fpu_op_w2w2(.din(fpu_op_w_vld), .clk(clk),
|
dff_s fpu_op_w2w2(.din(fpu_op_w_vld), .clk(clk),
|
.q(fpu_op_w2),
|
.q(fpu_op_w2),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff fpu_op_w22w3(.din(fpu_op_w2_vld), .clk(clk),
|
dff_s fpu_op_w22w3(.din(fpu_op_w2_vld), .clk(clk),
|
.q(fpu_op_w3),
|
.q(fpu_op_w3),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff #(2) tid_d2e(.din(ifu_ffu_tid_d[1:0]),
|
dff_s #(2) tid_d2e(.din(ifu_ffu_tid_d[1:0]),
|
.clk(clk),
|
.clk(clk),
|
.q(tid_e[1:0]),
|
.q(tid_e[1:0]),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff #(2) tid_e2m(.din(tid_e[1:0]),
|
dff_s #(2) tid_e2m(.din(tid_e[1:0]),
|
.clk(clk),
|
.clk(clk),
|
.q(tid_m[1:0]),
|
.q(tid_m[1:0]),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff #(2) tid_m2w(.din(tid_m[1:0]),
|
dff_s #(2) tid_m2w(.din(tid_m[1:0]),
|
.clk(clk),
|
.clk(clk),
|
.q(tid_w[1:0]),
|
.q(tid_w[1:0]),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff #(2) tid_w2w2(.din(tid_w[1:0]),
|
dff_s #(2) tid_w2w2(.din(tid_w[1:0]),
|
.clk(clk),
|
.clk(clk),
|
.q(tid_w2[1:0]),
|
.q(tid_w2[1:0]),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff dff_killed_w(.din(kill_m),
|
dff_s dff_killed_w(.din(kill_m),
|
.clk(clk),
|
.clk(clk),
|
.q(killed_w),
|
.q(killed_w),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff dff_flush_w2(.din(flush_w), .clk(clk), .q(flush_w2), .se(se), .si(), .so());
|
dff_s dff_flush_w2(.din(flush_w), .clk(clk), .q(flush_w2), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign thr_match_mw2 = ~((tid_m[1] ^ tid_w2[1]) |
|
assign thr_match_mw2 = ~((tid_m[1] ^ tid_w2[1]) |
|
(tid_m[0] ^ tid_w2[0]));
|
(tid_m[0] ^ tid_w2[0]));
|
assign thr_match_ww2 = ~((tid_w[1] ^ tid_w2[1]) |
|
assign thr_match_ww2 = ~((tid_w[1] ^ tid_w2[1]) |
|
(tid_w[0] ^ tid_w2[0]));
|
(tid_w[0] ^ tid_w2[0]));
|
Line 1974... |
Line 1141... |
|
|
// fpu expects lower 32 bits to be zero on single operands
|
// fpu expects lower 32 bits to be zero on single operands
|
assign zero_lower_data_next = ((source_single & ~rs1[0] & fpu_op_w_vld) |
|
assign zero_lower_data_next = ((source_single & ~rs1[0] & fpu_op_w_vld) |
|
(source_single & ~rs2[0] & fpu_op_m));
|
(source_single & ~rs2[0] & fpu_op_m));
|
|
|
dff shift_frf_right_dff(.din(shift_frf_right_next), .clk(clk), .q(shift_frf_right),
|
dff_s shift_frf_right_dff(.din(shift_frf_right_next), .clk(clk), .q(shift_frf_right),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff shift_frf_left_dff(.din(shift_frf_left_next), .clk(clk), .q(shift_frf_left),
|
dff_s shift_frf_left_dff(.din(shift_frf_left_next), .clk(clk), .q(shift_frf_left),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff noshift64_dff(.din(noshift64_frf_next), .clk(clk), .q(noshift64_frf),
|
dff_s noshift64_dff(.din(noshift64_frf_next), .clk(clk), .q(noshift64_frf),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff noshift32_dff(.din(zero_lower_data_next), .clk(clk), .q(ctl_dp_zero_low32_frf),
|
dff_s noshift32_dff(.din(zero_lower_data_next), .clk(clk), .q(ctl_dp_zero_low32_frf),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
wire flip_fpu;
|
wire flip_fpu;
|
wire flip_lsu;
|
wire flip_lsu;
|
// mux for rearranging data from fpu
|
// mux for rearranging data from fpu
|
// data comes in with msb always at b63. This means that singles with an odd
|
// data comes in with msb always at b63. This means that singles with an odd
|
Line 2020... |
Line 1187... |
// Resolved with Sanjay:
|
// Resolved with Sanjay:
|
// Will never receive ack in the same cycle req was first made
|
// Will never receive ack in the same cycle req was first made
|
assign fpop1_ready_w2_next = (fpu_op_w3_vld |
|
assign fpop1_ready_w2_next = (fpu_op_w3_vld |
|
(fpop1_ready_w2 & ~lsu_ffu_ack));
|
(fpop1_ready_w2 & ~lsu_ffu_ack));
|
|
|
dffr #1 fpop1_w2_dff(.din (fpop1_ready_w2_next),
|
dffr_s #1 fpop1_w2_dff(.din (fpop1_ready_w2_next),
|
.q (fpop1_ready_w2),
|
.q (fpop1_ready_w2),
|
.rst (reset),
|
.rst (reset),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// once op1 has been accepted, move to w2, and in the next cycle op2 is ready
|
// once op1 has been accepted, move to w2, and in the next cycle op2 is ready
|
//
|
//
|
// C1 -- recv ack, send op1 (fpop1_ready_w2)
|
// C1 -- recv ack, send op1 (fpop1_ready_w2)
|
// C2 -- send op2 (fpop2_ready_w3)
|
// C2 -- send op2 (fpop2_ready_w3)
|
assign fpop2_ready_w3_next = fpop1_ready_w2 & lsu_ffu_ack;
|
assign fpop2_ready_w3_next = fpop1_ready_w2 & lsu_ffu_ack;
|
|
|
dff fpop2_w22w3(.din (fpop2_ready_w3_next),
|
dff_s fpop2_w22w3(.din (fpop2_ready_w3_next),
|
.q (fpop2_ready_w3),
|
.q (fpop2_ready_w3),
|
.clk(clk), .se(se), .si(), .so());
|
.clk(clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
|
|
// request in W2 and wait till an ack is received
|
// request in W2 and wait till an ack is received
|
// Will never receive ack in the same cycle req was first made
|
// Will never receive ack in the same cycle req was first made
|
assign ffu_lsu_fpop_rq_vld = fpu_op_w3_vld;
|
assign ffu_lsu_fpop_rq_vld = fpu_op_w3_vld;
|
Line 2070... |
Line 1237... |
assign output_sel_rs2_next = ~(fpop2_ready_w3_next | fst_e | bst_issue_c3_next);
|
assign output_sel_rs2_next = ~(fpop2_ready_w3_next | fst_e | bst_issue_c3_next);
|
assign ctl_dp_output_sel_rs1 = output_sel_rs1 & ~rst_tri_en;
|
assign ctl_dp_output_sel_rs1 = output_sel_rs1 & ~rst_tri_en;
|
assign ctl_dp_output_sel_frf = output_sel_frf & ~rst_tri_en;
|
assign ctl_dp_output_sel_frf = output_sel_frf & ~rst_tri_en;
|
assign ctl_dp_output_sel_fsr = output_sel_fsr & ~rst_tri_en;
|
assign ctl_dp_output_sel_fsr = output_sel_fsr & ~rst_tri_en;
|
assign ctl_dp_output_sel_rs2 = output_sel_rs2 | rst_tri_en;
|
assign ctl_dp_output_sel_rs2 = output_sel_rs2 | rst_tri_en;
|
dff #(4) output_sel_dff(.din({output_sel_rs1_next,output_sel_rs2_next,output_sel_frf_next,output_sel_fsr_next}),
|
dff_s #(4) output_sel_dff(.din({output_sel_rs1_next,output_sel_rs2_next,output_sel_frf_next,output_sel_fsr_next}),
|
.q({output_sel_rs1,output_sel_rs2,output_sel_frf,output_sel_fsr}),
|
.q({output_sel_rs1,output_sel_rs2,output_sel_frf,output_sel_fsr}),
|
.clk(clk), .se(se), .si(), .so());
|
.clk(clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
|
|
dff #1 sfsrw_ff(.din (ctl_dp_output_sel_fsr),
|
dff_s #1 sfsrw_ff(.din (ctl_dp_output_sel_fsr),
|
.q (stfsr_w),
|
.q (stfsr_w),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff stfsr_wdff(.din(stfsr_qual_w), .clk(clk), .q(stfsr_w2), .se(se), .si(), .so());
|
dff_s stfsr_wdff(.din(stfsr_qual_w), .clk(clk), .q(stfsr_w2), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
assign stfsr_qual_w = (stfsr_w & ~kill_w);
|
assign stfsr_qual_w = (stfsr_w & ~kill_w);
|
assign stfsr_w2_vld = stfsr_w2 & ~flush_w2;
|
assign stfsr_w2_vld = stfsr_w2 & ~flush_w2;
|
|
|
|
|
//------------------------------------------------------
|
//------------------------------------------------------
|
Line 2119... |
Line 1286... |
// sotheas,9/14/04: fixed eco 6910, suppress block store start on dtlb perr
|
// sotheas,9/14/04: fixed eco 6910, suppress block store start on dtlb perr
|
// using registered version of lsu_ffu_st_dtlb_perr_g
|
// using registered version of lsu_ffu_st_dtlb_perr_g
|
// WAS:
|
// WAS:
|
// assign bst_issue_c2_next = ((bst_issue_c1 & ~(any_op_w2 & flush_w2)) | (bst_issue_c2 & ~can_issue_bst_c2)) & ~reset;
|
// assign bst_issue_c2_next = ((bst_issue_c1 & ~(any_op_w2 & flush_w2)) | (bst_issue_c2 & ~can_issue_bst_c2)) & ~reset;
|
// IS:
|
// IS:
|
dff #1 st_dtlbperr_ff(.din (!lsu_ffu_st_dtlb_perr_g),
|
dff_s #1 st_dtlbperr_ff(.din (!lsu_ffu_st_dtlb_perr_g),
|
.q (st_dtlb_perr_w2_l),
|
.q (st_dtlb_perr_w2_l),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
assign bst_issue_c2_next = ((bst_issue_c1 & ~(any_op_w2 & flush_w2) & st_dtlb_perr_w2_l)
|
assign bst_issue_c2_next = ((bst_issue_c1 & ~(any_op_w2 & flush_w2) & st_dtlb_perr_w2_l)
|
| (bst_issue_c2 & ~can_issue_bst_c2)) & ~reset;
|
| (bst_issue_c2 & ~can_issue_bst_c2)) & ~reset;
|
assign bst_issue_c3_next = bst_issue_c2 & can_issue_bst_c2 & ~reset;
|
assign bst_issue_c3_next = bst_issue_c2 & can_issue_bst_c2 & ~reset;
|
assign bst_issue_c4_next = bst_issue_c3 & ~reset;
|
assign bst_issue_c4_next = bst_issue_c3 & ~reset;
|
assign bst_issue_c5_next = bst_issue_c4 & bst_ce_c4 & ~reset;
|
assign bst_issue_c5_next = bst_issue_c4 & bst_ce_c4 & ~reset;
|
Line 2155... |
Line 1322... |
// if a ce occurs even after correction then it is converted to a ue
|
// if a ce occurs even after correction then it is converted to a ue
|
assign bst_ue_c4 = bst_issue_c4 & (previous_ue | (fixed_bst_ce & |previous_ce[1:0]));
|
assign bst_ue_c4 = bst_issue_c4 & (previous_ue | (fixed_bst_ce & |previous_ce[1:0]));
|
assign bst_ce_c4 = bst_issue_c4 & |previous_ce[1:0] & ~fixed_bst_ce & ~previous_ue;
|
assign bst_ce_c4 = bst_issue_c4 & |previous_ce[1:0] & ~fixed_bst_ce & ~previous_ue;
|
assign fixed_bst_ce_next = bst_ce_c4 | (fixed_bst_ce & ~bst_issue_c4);
|
assign fixed_bst_ce_next = bst_ce_c4 | (fixed_bst_ce & ~bst_issue_c4);
|
|
|
dff #(4) stb_full_dff(.din({lsu_ffu_stb_full0,lsu_ffu_stb_full1,lsu_ffu_stb_full2,lsu_ffu_stb_full3}),
|
dff_s #(4) stb_full_dff(.din({lsu_ffu_stb_full0,lsu_ffu_stb_full1,lsu_ffu_stb_full2,lsu_ffu_stb_full3}),
|
.q({stb_full0, stb_full1, stb_full2, stb_full3}),
|
.q({stb_full0, stb_full1, stb_full2, stb_full3}),
|
.clk(clk), .se(se), .si(), .so());
|
.clk(clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff blk_asi_dff(.din(lsu_ffu_blk_asi_e), .clk(clk), .q(blk_asi_m),
|
dff_s blk_asi_dff(.din(lsu_ffu_blk_asi_e), .clk(clk), .q(blk_asi_m),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
dffr bst_fix_ce_dff(.din(fixed_bst_ce_next), .clk(clk), .q(fixed_bst_ce),
|
dffr_s bst_fix_ce_dff(.din(fixed_bst_ce_next), .clk(clk), .q(fixed_bst_ce),
|
.se(se), .si(), .so(), .rst(reset));
|
.se(se), `SIMPLY_RISC_SCANIN, .so(), .rst(reset));
|
dff #(3) bst_cnt_dff(.din(bst_cnt_next[2:0]), .clk(clk), .q(bst_cnt[2:0]),
|
dff_s #(3) bst_cnt_dff(.din(bst_cnt_next[2:0]), .clk(clk), .q(bst_cnt[2:0]),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff bst_m2w(.din(bst_m), .clk(clk), .q(bst_w), .se(se), .si(), .so());
|
dff_s bst_m2w(.din(bst_m), .clk(clk), .q(bst_w), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff bst_issue_c1_dff(.din(bst_issue_c1_next), .clk(clk), .q(bst_issue_c1), .se(se),
|
dff_s bst_issue_c1_dff(.din(bst_issue_c1_next), .clk(clk), .q(bst_issue_c1), .se(se),
|
.si(), .so());
|
`SIMPLY_RISC_SCANIN, .so());
|
dff bst_issue_c2_dff(.din(bst_issue_c2_next), .clk(clk), .q(bst_issue_c2), .se(se),
|
dff_s bst_issue_c2_dff(.din(bst_issue_c2_next), .clk(clk), .q(bst_issue_c2), .se(se),
|
.si(), .so());
|
`SIMPLY_RISC_SCANIN, .so());
|
dff bst_issue_c3_dff(.din(bst_issue_c3_next), .clk(clk), .q(bst_issue_c3), .se(se),
|
dff_s bst_issue_c3_dff(.din(bst_issue_c3_next), .clk(clk), .q(bst_issue_c3), .se(se),
|
.si(), .so());
|
`SIMPLY_RISC_SCANIN, .so());
|
dff bst_issue_c4_dff(.din(bst_issue_c4_next), .clk(clk), .q(bst_issue_c4), .se(se),
|
dff_s bst_issue_c4_dff(.din(bst_issue_c4_next), .clk(clk), .q(bst_issue_c4), .se(se),
|
.si(), .so());
|
`SIMPLY_RISC_SCANIN, .so());
|
dff bst_issue_c5_dff(.din(bst_issue_c5_next), .clk(clk), .q(bst_issue_c5), .se(se),
|
dff_s bst_issue_c5_dff(.din(bst_issue_c5_next), .clk(clk), .q(bst_issue_c5), .se(se),
|
.si(), .so());
|
`SIMPLY_RISC_SCANIN, .so());
|
dff bst_issue_c6_dff(.din(bst_issue_c6_next), .clk(clk), .q(bst_issue_c6), .se(se),
|
dff_s bst_issue_c6_dff(.din(bst_issue_c6_next), .clk(clk), .q(bst_issue_c6), .se(se),
|
.si(), .so());
|
`SIMPLY_RISC_SCANIN, .so());
|
dff #(6) bst_stall_cntdff(.din(bst_stall_cnt_next[5:0]), .clk(clk), .q(bst_stall_cnt[5:0]),
|
dff_s #(6) bst_stall_cntdff(.din(bst_stall_cnt_next[5:0]), .clk(clk), .q(bst_stall_cnt[5:0]),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
dffr bst_stall_reqdff(.din(bst_stall_req_next), .clk(clk), .q(bst_stall_req),
|
dffr_s bst_stall_reqdff(.din(bst_stall_req_next), .clk(clk), .q(bst_stall_req),
|
.se(se), .si(), .so(), .rst(reset));
|
.se(se), `SIMPLY_RISC_SCANIN, .so(), .rst(reset));
|
|
|
//----------------------------------------
|
//----------------------------------------
|
// Decode Returning FPU/LSU packets
|
// Decode Returning FPU/LSU packets
|
//----------------------------------------
|
//----------------------------------------
|
|
|
// FPU result pulled off of cpx
|
// FPU result pulled off of cpx
|
assign is_fpu_result = (cpx_req_d1 == 4'b1000) ?
|
assign is_fpu_result = (cpx_req_d1 == `FP_RET) ?
|
cpx_vld_d1 & fp_pending : 1'b0;
|
cpx_vld_d1 & fp_pending : 1'b0;
|
assign ld_ret = lsu_ffu_ld_vld & ~(thr_match_fpw2 & flush_w2) & (blk_load_pending | load_pending);
|
assign ld_ret = lsu_ffu_ld_vld & ~(thr_match_fpw2 & flush_w2) & (blk_load_pending | load_pending);
|
|
|
// select frf write data
|
// select frf write data
|
// don't write data on Fcompares
|
// don't write data on Fcompares
|
Line 2212... |
Line 1379... |
//----------------------------------------
|
//----------------------------------------
|
// WEN for frf from load, FPU result or mov
|
// WEN for frf from load, FPU result or mov
|
assign external_wen_next = ld_ret & ~(ldfsr | ldxfsr) | (is_fpu_result & ~cpx_fcmp_d1 & ~take_ieee_trap);
|
assign external_wen_next = ld_ret & ~(ldfsr | ldxfsr) | (is_fpu_result & ~cpx_fcmp_d1 & ~take_ieee_trap);
|
assign rf_ecc_gen_next = external_wen_next | vis_wen_next;
|
assign rf_ecc_gen_next = external_wen_next | vis_wen_next;
|
|
|
dff rf_eccgen_dff(.din(rf_ecc_gen_next), .q(rf_ecc_gen), .clk(clk), .se(se), .si(), .so());
|
dff_s rf_eccgen_dff(.din(rf_ecc_gen_next), .q(rf_ecc_gen), .clk(clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff rf_wen_dff(.din(rf_wen_next), .q(rf_wen), .clk(clk), .se(se), .si(), .so());
|
dff_s rf_wen_dff(.din(rf_wen_next), .q(rf_wen), .clk(clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
// check for flush_pipe for moves
|
// check for flush_pipe for moves
|
assign rf_wen_next = rf_ecc_gen & ~(any_op_w2 & flush_w2) | move_wen_w2_valid;
|
assign rf_wen_next = rf_ecc_gen & ~(any_op_w2 & flush_w2) | move_wen_w2_valid;
|
|
|
|
|
// REN and WEN must be mutually exclusive. This works because WEN is always after W
|
// REN and WEN must be mutually exclusive. This works because WEN is always after W
|
Line 2273... |
Line 1440... |
// This is staged 2 cycles to allow for the cycle of ecc generation.
|
// This is staged 2 cycles to allow for the cycle of ecc generation.
|
//
|
//
|
assign ffu_op_done_next = ((is_fpu_result & ~take_ieee_trap) | fld_done |
|
assign ffu_op_done_next = ((is_fpu_result & ~take_ieee_trap) | fld_done |
|
blk_ld_done | bst_done | vis_result |
|
blk_ld_done | bst_done | vis_result |
|
fst_w & ~bst_w & ~kill_w);
|
fst_w & ~bst_w & ~kill_w);
|
dff ffu_op_done_dff(.din(ffu_op_done_next), .clk(clk), .q(ffu_op_done),
|
dff_s ffu_op_done_dff(.din(ffu_op_done_next), .clk(clk), .q(ffu_op_done),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
// sotheas,9/14/04: fixed eco 6910, send done on dtlb perr for block store
|
// sotheas,9/14/04: fixed eco 6910, send done on dtlb perr for block store
|
// using registered version of lsu_ffu_st_dtlb_perr_g
|
// using registered version of lsu_ffu_st_dtlb_perr_g
|
// WAS:
|
// WAS:
|
// assign ffu_op_done_vld = ffu_op_done & ~(any_op_w2 & flush_w2) | move_w2_vld;
|
// assign ffu_op_done_vld = ffu_op_done & ~(any_op_w2 & flush_w2) | move_w2_vld;
|
assign ffu_op_done_vld = (ffu_op_done | (bst_issue_c1 & !st_dtlb_perr_w2_l) )
|
assign ffu_op_done_vld = (ffu_op_done | (bst_issue_c1 & !st_dtlb_perr_w2_l) )
|
& ~(any_op_w2 & flush_w2) | move_w2_vld;
|
& ~(any_op_w2 & flush_w2) | move_w2_vld;
|
dff ffu_op_done2_dff(.din(ffu_op_done_vld), .clk(clk), .q(ffu_ifu_fpop_done_w2),
|
dff_s ffu_op_done2_dff(.din(ffu_op_done_vld), .clk(clk), .q(ffu_ifu_fpop_done_w2),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
//------------------------------------------
|
//------------------------------------------
|
// FSR Controls
|
// FSR Controls
|
//------------------------------------------
|
//------------------------------------------
|
|
|
Line 2345... |
Line 1512... |
|
|
// fcc set by fcmp, ldfsr or ldxfsr
|
// fcc set by fcmp, ldfsr or ldxfsr
|
assign cc_changed = fcc_sel_fpu |
|
assign cc_changed = fcc_sel_fpu |
|
fld_done & (ldfsr_vld | ldxfsr_vld);
|
fld_done & (ldfsr_vld | ldxfsr_vld);
|
|
|
dff cc_changed_dff(.din(cc_changed), .clk(clk), .q(cc_changed_w2),
|
dff_s cc_changed_dff(.din(cc_changed), .clk(clk), .q(cc_changed_w2),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff #(8) cc_next(.din(ctl_dp_fcc_w2[7:0]), .clk(clk), .q(ffu_ifu_cc_w2[7:0]),
|
dff_s #(8) cc_next(.din(ctl_dp_fcc_w2[7:0]), .clk(clk), .q(ffu_ifu_cc_w2[7:0]),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign ffu_ifu_cc_vld_w2[3:0] = ctl_dp_fp_thr[3:0] & {4{cc_changed_w2}};
|
assign ffu_ifu_cc_vld_w2[3:0] = ctl_dp_fp_thr[3:0] & {4{cc_changed_w2}};
|
|
|
//-----------------------------------
|
//-----------------------------------
|
// Traps
|
// Traps
|
//-----------------------------------
|
//-----------------------------------
|
|
|
// illegal instruction if blk ld/st is not 8 dp regs aligned
|
// illegal instruction if blk ld/st is not 8 dp regs aligned
|
dff illegal_vis_e2m (.din(illegal_vis_e), .clk(clk), .q(illegal_vis_m),
|
dff_s illegal_vis_e2m (.din(illegal_vis_e), .clk(clk), .q(illegal_vis_m),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
assign illegal_blk_m = (blk_ld_m | bst_m) & (rd[0] | rd[1] | rd[2] | rd[3]) & ~dest_single;
|
assign illegal_blk_m = (blk_ld_m | bst_m) & (rd[0] | rd[1] | rd[2] | rd[3]) & ~dest_single;
|
assign ffu_tlu_ill_inst_m = illegal_blk_m | illegal_vis_m;
|
assign ffu_tlu_ill_inst_m = illegal_blk_m | illegal_vis_m;
|
|
|
assign ctl_dp_ftt_w2 = take_ieee_trap ? 3'b001 :
|
assign ctl_dp_ftt_w2 = take_ieee_trap ? 3'b001 :
|
unimpl_qual_w2 ? 3'b011 :
|
unimpl_qual_w2 ? 3'b011 :
|
Line 2410... |
Line 1577... |
// FSR.UFM is not set. This case represents an exact denormalized
|
// FSR.UFM is not set. This case represents an exact denormalized
|
// result.
|
// result.
|
//
|
//
|
// Note: - FPU will signal underflow to the FFU for all "tiny" results.
|
// Note: - FPU will signal underflow to the FFU for all "tiny" results.
|
// - FPU always reports inexact along with overflow.
|
// - FPU always reports inexact along with overflow.
|
dff #(5) tem_dff(.din(dp_ctl_fsr_tem[4:0]), .clk(clk), .q(fsr_tem_d1),
|
dff_s #(5) tem_dff(.din(dp_ctl_fsr_tem[4:0]), .clk(clk), .q(fsr_tem_d1),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
assign fpexc_nxc =
|
assign fpexc_nxc =
|
cpx_fpexc_d1[0] &
|
cpx_fpexc_d1[`FSR_NXC] &
|
~(( fsr_tem_d1[3] & cpx_fpexc_d1[3]) | // enabled of
|
~(( fsr_tem_d1[3] & cpx_fpexc_d1[`FSR_OFC]) | // enabled of
|
( fsr_tem_d1[2] & cpx_fpexc_d1[2]) ); // enabled uf
|
( fsr_tem_d1[2] & cpx_fpexc_d1[`FSR_UFC]) ); // enabled uf
|
|
|
assign fpexc_ofc =
|
assign fpexc_ofc =
|
cpx_fpexc_d1[3] &
|
cpx_fpexc_d1[`FSR_OFC] &
|
~(~fsr_tem_d1[3] & fsr_tem_d1[0] & cpx_fpexc_d1[0]); // disabled of and enabled nx
|
~(~fsr_tem_d1[3] & fsr_tem_d1[0] & cpx_fpexc_d1[`FSR_NXC]); // disabled of and enabled nx
|
|
|
assign fpexc_ufc =
|
assign fpexc_ufc =
|
cpx_fpexc_d1[2] &
|
cpx_fpexc_d1[`FSR_UFC] &
|
~(~fsr_tem_d1[2] & ( fsr_tem_d1[0] & cpx_fpexc_d1[0])) & // disabled uf & enabled nx
|
~(~fsr_tem_d1[2] & ( fsr_tem_d1[0] & cpx_fpexc_d1[`FSR_NXC])) & // disabled uf & enabled nx
|
~(~fsr_tem_d1[2] & ~cpx_fpexc_d1[0]) ; // disabled uf with no inexact
|
~(~fsr_tem_d1[2] & ~cpx_fpexc_d1[`FSR_NXC]) ; // disabled uf with no inexact
|
// (i.e. exact denorm w/ UFM=0)
|
// (i.e. exact denorm w/ UFM=0)
|
|
|
|
|
assign ieee_trap_vec[4:0] =
|
assign ieee_trap_vec[4:0] =
|
({cpx_fpexc_d1[4],
|
({cpx_fpexc_d1[4],
|
Line 2439... |
Line 1606... |
|
|
|
|
// ieee trap has least priority. Put through a flop for timing reasons
|
// ieee trap has least priority. Put through a flop for timing reasons
|
assign ieee_trap = (|ieee_trap_vec[4:0]);
|
assign ieee_trap = (|ieee_trap_vec[4:0]);
|
assign take_ieee_trap = ieee_trap & is_fpu_result;
|
assign take_ieee_trap = ieee_trap & is_fpu_result;
|
dff trap_ieee_dff(.din(take_ieee_trap), .clk(clk), .q(ffu_tlu_trap_ieee754),
|
dff_s trap_ieee_dff(.din(take_ieee_trap), .clk(clk), .q(ffu_tlu_trap_ieee754),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign take_other_trap = unimpl_qual_w2;
|
assign take_other_trap = unimpl_qual_w2;
|
assign ffu_tlu_trap_other = take_other_trap;
|
assign ffu_tlu_trap_other = take_other_trap;
|
assign ffu_tlu_trap_ue = ue_trap_w3;
|
assign ffu_tlu_trap_ue = ue_trap_w3;
|
|
|
Line 2459... |
Line 1626... |
|
|
|
|
|
|
// accrued exceptions
|
// accrued exceptions
|
// fp_exc_w2 = dp_ctl_fsr_aexc | cpx_fpexc_d1 & {5{~take_ieee_trap}};
|
// fp_exc_w2 = dp_ctl_fsr_aexc | cpx_fpexc_d1 & {5{~take_ieee_trap}};
|
assign fp_exc_w2[9] = dp_ctl_fsr_aexc[4] |
|
assign fp_exc_w2[`FSR_NVA] = dp_ctl_fsr_aexc[`FSR_NVC] |
|
is_fpu_result & cpx_fpexc_d1[4] & ~fsr_tem_d1[4];
|
is_fpu_result & cpx_fpexc_d1[`FSR_NVC] & ~fsr_tem_d1[`FSR_NVC];
|
assign fp_exc_w2[6] = dp_ctl_fsr_aexc[1] |
|
assign fp_exc_w2[`FSR_DZA] = dp_ctl_fsr_aexc[`FSR_DZC] |
|
is_fpu_result & cpx_fpexc_d1[1] & ~fsr_tem_d1[1];
|
is_fpu_result & cpx_fpexc_d1[`FSR_DZC] & ~fsr_tem_d1[`FSR_DZC];
|
assign fp_exc_w2[7] = dp_ctl_fsr_aexc[2] |
|
assign fp_exc_w2[`FSR_UFA] = dp_ctl_fsr_aexc[`FSR_UFC] |
|
is_fpu_result & fpexc_ufc & ~fsr_tem_d1[2];
|
is_fpu_result & fpexc_ufc & ~fsr_tem_d1[`FSR_UFC];
|
assign fp_exc_w2[8] = dp_ctl_fsr_aexc[3] |
|
assign fp_exc_w2[`FSR_OFA] = dp_ctl_fsr_aexc[`FSR_OFC] |
|
is_fpu_result & fpexc_ofc & ~fsr_tem_d1[3];
|
is_fpu_result & fpexc_ofc & ~fsr_tem_d1[`FSR_OFC];
|
assign fp_exc_w2[5] = dp_ctl_fsr_aexc[0] |
|
assign fp_exc_w2[`FSR_NXA] = dp_ctl_fsr_aexc[`FSR_NXC] |
|
is_fpu_result & fpexc_nxc & ~fsr_tem_d1[0];
|
is_fpu_result & fpexc_nxc & ~fsr_tem_d1[`FSR_NXC];
|
|
|
assign ctl_dp_exc_w2[9:5] = fp_exc_w2[9:5];
|
assign ctl_dp_exc_w2[9:5] = fp_exc_w2[9:5];
|
// move, abs, etc will clear cexc, fpu_results will update, all else will leave unchanged
|
// move, abs, etc will clear cexc, fpu_results will update, all else will leave unchanged
|
wire update_cexc;
|
wire update_cexc;
|
assign update_cexc = is_fpu_result | move_w2_vld;
|
assign update_cexc = is_fpu_result | move_w2_vld;
|
Line 2488... |
Line 1655... |
wire [13:0] gen_synd_d1;
|
wire [13:0] gen_synd_d1;
|
wire gen_par_hi;
|
wire gen_par_hi;
|
wire gen_par_low;
|
wire gen_par_low;
|
wire [6:0] error_inj_data;
|
wire [6:0] error_inj_data;
|
output [13:0] ctl_frf_write_synd;
|
output [13:0] ctl_frf_write_synd;
|
dff #(14) gen_synd_dff (.din({dp_ctl_synd_out_high[6:0],dp_ctl_synd_out_low[6:0]}),
|
dff_s #(14) gen_synd_dff (.din({dp_ctl_synd_out_high[6:0],dp_ctl_synd_out_low[6:0]}),
|
.q(gen_synd_d1[13:0]), .clk(clk), .se(se), .si(), .so());
|
.q(gen_synd_d1[13:0]), .clk(clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
assign gen_par_hi = ^gen_synd_d1[13:7];
|
assign gen_par_hi = ^gen_synd_d1[13:7];
|
assign gen_par_low = ^gen_synd_d1[6:0];
|
assign gen_par_low = ^gen_synd_d1[6:0];
|
assign ctl_frf_write_synd[13:0] = ({gen_par_hi,gen_synd_d1[12:7],gen_par_low,gen_synd_d1[5:0]} ^
|
assign ctl_frf_write_synd[13:0] = ({gen_par_hi,gen_synd_d1[12:7],gen_par_low,gen_synd_d1[5:0]} ^
|
{error_inj_data[6:0],error_inj_data[6:0]});
|
{error_inj_data[6:0],error_inj_data[6:0]});
|
/////////////////////////////////
|
/////////////////////////////////
|
// error injection
|
// error injection
|
/////////////////////////////////
|
/////////////////////////////////
|
// injection doesn't check for flush on wen
|
// injection doesn't check for flush on wen
|
assign inject_err_next = ifu_ffu_inj_frferr & rf_wen_next;
|
assign inject_err_next = ifu_ffu_inj_frferr & rf_wen_next;
|
assign error_inj_data[6:0] = {7{inject_err}} & err_data[6:0];
|
assign error_inj_data[6:0] = {7{inject_err}} & err_data[6:0];
|
dff #(7) err_data_dff(.din(ifu_exu_ecc_mask[6:0]),
|
dff_s #(7) err_data_dff(.din(ifu_exu_ecc_mask[6:0]),
|
.q(err_data[6:0]),
|
.q(err_data[6:0]),
|
.clk(clk), .se(se), .si(), .so());
|
.clk(clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff err_cntl(.din(inject_err_next),
|
dff_s err_cntl(.din(inject_err_next),
|
.q(inject_err),
|
.q(inject_err),
|
.clk(clk), .se(se), .si(), .so());
|
.clk(clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
// speculate on error injection (don't check flush_pipe etc)
|
// speculate on error injection (don't check flush_pipe etc)
|
assign ffu_ifu_inj_ack = inject_err;
|
assign ffu_ifu_inj_ack = inject_err;
|
|
|
|
|
// check the upper half on a double or a single with an even reg num
|
// check the upper half on a double or a single with an even reg num
|
// check the lower half on a double or a single with an odd reg num
|
// check the lower half on a double or a single with an odd reg num
|
// ecc block will run on frf input for reads
|
// ecc block will run on frf input for reads
|
// otherwise it will run on the rd_data
|
// otherwise it will run on the rd_data
|
assign check_ecc_next = ren_rs2_m | fst_e | ren_rs1_w | bst_issue_c3_next;
|
assign check_ecc_next = ren_rs2_m | fst_e | ren_rs1_w | bst_issue_c3_next;
|
dff check_ecc_dff(.din(check_ecc_next), .clk(clk), .q(ctl_dp_ecc_sel_frf),
|
dff_s check_ecc_dff(.din(check_ecc_next), .clk(clk), .q(ctl_dp_ecc_sel_frf),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
// rs1 will not be checked if a ce was detected on rs2. If there was a ue on rs2
|
// rs1 will not be checked if a ce was detected on rs2. If there was a ue on rs2
|
// rs1 will be checked and a ce will be corrected, but the error on rs2 will be logged
|
// rs1 will be checked and a ce will be corrected, but the error on rs2 will be logged
|
assign chk_rs1_w2 = ren_rs1_w2;
|
assign chk_rs1_w2 = ren_rs1_w2;
|
assign chk_ecc_m[1] = fst_m & ~rd[0] & ~output_sel_fsr;
|
assign chk_ecc_m[1] = fst_m & ~rd[0] & ~output_sel_fsr;
|
assign chk_ecc_m[0] = fst_m & (~dest_single | rd[0]) & ~output_sel_fsr;
|
assign chk_ecc_m[0] = fst_m & (~dest_single | rd[0]) & ~output_sel_fsr;
|
Line 2528... |
Line 1695... |
assign chk_ecc_w[0] = ren_rs2_w & ~kill_eccchk_w & (~source_single | rs2[0]);
|
assign chk_ecc_w[0] = ren_rs2_w & ~kill_eccchk_w & (~source_single | rs2[0]);
|
assign chk_ecc_w2[1] = chk_rs1_w2 & ~rs1[0];
|
assign chk_ecc_w2[1] = chk_rs1_w2 & ~rs1[0];
|
assign chk_ecc_w2[0] = chk_rs1_w2 & (~source_single | rs1[0]);
|
assign chk_ecc_w2[0] = chk_rs1_w2 & (~source_single | rs1[0]);
|
|
|
assign chk_ecc[1:0] = chk_ecc_m[1:0] | chk_ecc_w[1:0] | chk_ecc_w2[1:0] | {2{bst_issue_c3}};
|
assign chk_ecc[1:0] = chk_ecc_m[1:0] | chk_ecc_w[1:0] | chk_ecc_w2[1:0] | {2{bst_issue_c3}};
|
dff #(2) chk_ecc_dff(.din(chk_ecc[1:0]), .clk(clk), .q(chk_ecc_prev[1:0]),
|
dff_s #(2) chk_ecc_dff(.din(chk_ecc[1:0]), .clk(clk), .q(chk_ecc_prev[1:0]),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign error_detected[1] = |dp_ctl_synd_out_high[5:0];
|
assign error_detected[1] = |dp_ctl_synd_out_high[5:0];
|
assign error_detected[0] = |dp_ctl_synd_out_low[5:0];
|
assign error_detected[0] = |dp_ctl_synd_out_low[5:0];
|
|
|
assign possible_ue[1] = ~dp_ctl_synd_out_high[6] & chk_ecc[1];
|
assign possible_ue[1] = ~dp_ctl_synd_out_high[6] & chk_ecc[1];
|
Line 2541... |
Line 1708... |
assign ce[1] = dp_ctl_synd_out_high[6] & chk_ecc[1];
|
assign ce[1] = dp_ctl_synd_out_high[6] & chk_ecc[1];
|
assign ce[0] = dp_ctl_synd_out_low[6] & chk_ecc[0];
|
assign ce[0] = dp_ctl_synd_out_low[6] & chk_ecc[0];
|
|
|
assign rollback_fst_m = ((dp_ctl_synd_out_high[6] & chk_ecc_m[1] & ~disable_ce_m) |
|
assign rollback_fst_m = ((dp_ctl_synd_out_high[6] & chk_ecc_m[1] & ~disable_ce_m) |
|
(dp_ctl_synd_out_low[6] & chk_ecc_m[0] & ~disable_ce_m));
|
(dp_ctl_synd_out_low[6] & chk_ecc_m[0] & ~disable_ce_m));
|
dff rollback_m2w(.din(rollback_fst_m), .clk(clk), .q(rollback_fst_w), .se(se), .si(), .so());
|
dff_s rollback_m2w(.din(rollback_fst_m), .clk(clk), .q(rollback_fst_w), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff #(2) possible_ue_dff(.din(possible_ue[1:0]), .clk(clk), .q(prev_poss_ue[1:0]),
|
dff_s #(2) possible_ue_dff(.din(possible_ue[1:0]), .clk(clk), .q(prev_poss_ue[1:0]),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff #(2) ce_dff(.din(ce[1:0]), .clk(clk), .q(previous_ce[1:0]),
|
dff_s #(2) ce_dff(.din(ce[1:0]), .clk(clk), .q(previous_ce[1:0]),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff #(2) err_det_dff(.din(error_detected[1:0]), .clk(clk), .q(prev_err_detected[1:0]),
|
dff_s #(2) err_det_dff(.din(error_detected[1:0]), .clk(clk), .q(prev_err_detected[1:0]),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
assign previous_ue = |(prev_err_detected[1:0] & prev_poss_ue[1:0]);
|
assign previous_ue = |(prev_err_detected[1:0] & prev_poss_ue[1:0]);
|
|
|
dff #(2) ecc_wen1_dff(.din(ecc_wen_gen_next[1:0]), .clk(clk), .q(ecc_wen_gen[1:0]),
|
dff_s #(2) ecc_wen1_dff(.din(ecc_wen_gen_next[1:0]), .clk(clk), .q(ecc_wen_gen[1:0]),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff #(2) ecc_wen2_dff(.din(ecc_wen_next[1:0]), .clk(clk), .q(ecc_wen[1:0]),
|
dff_s #(2) ecc_wen2_dff(.din(ecc_wen_next[1:0]), .clk(clk), .q(ecc_wen[1:0]),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
// if the ecc error was in the m stage we need to check for a kill
|
// if the ecc error was in the m stage we need to check for a kill
|
// if the ecc error was in the w stage we need to check flush
|
// if the ecc error was in the w stage we need to check flush
|
// ECC errors on rs1 will not be written back to the frf. The data that is used will be corrected.
|
// ECC errors on rs1 will not be written back to the frf. The data that is used will be corrected.
|
assign ecc_wen_gen_next[1:0] = previous_ce[1:0] &
|
assign ecc_wen_gen_next[1:0] = previous_ce[1:0] &
|
{2{bst_issue_c4 | fst_ce_w | rollback_rs2_w2 | rollback_rs1_w3}};
|
{2{bst_issue_c4 | fst_ce_w | rollback_rs2_w2 | rollback_rs1_w3}};
|
assign ecc_wen_next = ecc_wen_gen[1:0] & {2{~(fst_ce_w2 & flush_w2)}};
|
assign ecc_wen_next = ecc_wen_gen[1:0] & {2{~(fst_ce_w2 & flush_w2)}};
|
|
|
// pass along ce and ue so trap can be signalled to ffu and tlu
|
// pass along ce and ue so trap can be signalled to ffu and tlu
|
// if disable_ce_m then don't tell ifu reissue ce. Instead convert to a ue.
|
// if disable_ce_m then don't tell ifu reissue ce. Instead convert to a ue.
|
dff disable_ce_e2m(.din(ifu_exu_disable_ce_e), .clk(clk), .q(disable_ce_m),
|
dff_s disable_ce_e2m(.din(ifu_exu_disable_ce_e), .clk(clk), .q(disable_ce_m),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff disable_ce_m2w(.din(disable_ce_m), .clk(clk), .q(disable_ce_w),
|
dff_s disable_ce_m2w(.din(disable_ce_m), .clk(clk), .q(disable_ce_w),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
assign fst_ce_w = rollback_fst_w & ~kill_eccchk_w;
|
assign fst_ce_w = rollback_fst_w & ~kill_eccchk_w;
|
assign fst_ue_w = fst_w & (previous_ue | (disable_ce_w & |(previous_ce[1:0]))) & ~kill_eccchk_w;
|
assign fst_ue_w = fst_w & (previous_ue | (disable_ce_w & |(previous_ce[1:0]))) & ~kill_eccchk_w;
|
assign rollback_rs2_w2 = (ren_rs2_w2 & ~flush_w2 & |previous_ce[1:0]
|
assign rollback_rs2_w2 = (ren_rs2_w2 & ~flush_w2 & |previous_ce[1:0]
|
& ~rolled_back);
|
& ~rolled_back);
|
assign rs2_ce_w2 = ren_rs2_w2 & |previous_ce[1:0] & ~rolled_back & ~previous_ue;
|
assign rs2_ce_w2 = ren_rs2_w2 & |previous_ce[1:0] & ~rolled_back & ~previous_ue;
|
assign rs2_ue_w2 = ren_rs2_w2 & (previous_ue | (rolled_back & |previous_ce[1:0]));
|
assign rs2_ue_w2 = ren_rs2_w2 & (previous_ue | (rolled_back & |previous_ce[1:0]));
|
// must check for flush because eccchk doesn't do this
|
// must check for flush because eccchk doesn't do this
|
assign rs2_fst_ce_w2_vld = (rs2_ce_w2 | fst_ce_w2) & ~flush_w2;
|
assign rs2_fst_ce_w2_vld = (rs2_ce_w2 | fst_ce_w2) & ~flush_w2;
|
assign rs2_fst_ue_w2_vld = (rs2_ue_w2 | fst_ue_w2) & ~flush_w2;
|
assign rs2_fst_ue_w2_vld = (rs2_ue_w2 | fst_ue_w2) & ~flush_w2;
|
dff ce_w2w2(.din(fst_ce_w), .clk(clk), .q(fst_ce_w2),
|
dff_s ce_w2w2(.din(fst_ce_w), .clk(clk), .q(fst_ce_w2),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff ue_w2w2(.din(fst_ue_w), .clk(clk), .q(fst_ue_w2),
|
dff_s ue_w2w2(.din(fst_ue_w), .clk(clk), .q(fst_ue_w2),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff ce_w22w3(.din(rs2_fst_ce_w2_vld), .clk(clk), .q(rs2_fst_ce_w3),
|
dff_s ce_w22w3(.din(rs2_fst_ce_w2_vld), .clk(clk), .q(rs2_fst_ce_w3),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff ue_w22w3(.din(rs2_fst_ue_w2_vld), .clk(clk), .q(rs2_fst_ue_w3),
|
dff_s ue_w22w3(.din(rs2_fst_ue_w2_vld), .clk(clk), .q(rs2_fst_ue_w3),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign rs1_ce_w3 = ren_rs1_w3 & |previous_ce[1:0] & ~previous_ue & ~rolled_back;
|
assign rs1_ce_w3 = ren_rs1_w3 & |previous_ce[1:0] & ~previous_ue & ~rolled_back;
|
assign rollback_rs1_w3 = rs1_ce_w3 & ~ue_trap_w3;
|
assign rollback_rs1_w3 = rs1_ce_w3 & ~ue_trap_w3;
|
assign ce_w3 = (rs1_ce_w3 | rs2_fst_ce_w3);
|
assign ce_w3 = (rs1_ce_w3 | rs2_fst_ce_w3);
|
assign ue_w3 = (ren_rs1_w3 & (previous_ue | (rolled_back & |previous_ce[1:0]))) | rs2_fst_ue_w3;
|
assign ue_w3 = (ren_rs1_w3 & (previous_ue | (rolled_back & |previous_ce[1:0]))) | rs2_fst_ue_w3;
|
Line 2601... |
Line 1768... |
assign new_err_reg[5:0] = fst_w ? rd[5:0]:
|
assign new_err_reg[5:0] = fst_w ? rd[5:0]:
|
bst_issue_c4 ? bst_rs[5:0]:
|
bst_issue_c4 ? bst_rs[5:0]:
|
ren_rs2_w2 ? rs2[5:0]:
|
ren_rs2_w2 ? rs2[5:0]:
|
rs1[5:0];
|
rs1[5:0];
|
assign err_reg_next[5:0] = (log_new_err) ? new_err_reg[5:0] : err_reg_d1[5:0];
|
assign err_reg_next[5:0] = (log_new_err) ? new_err_reg[5:0] : err_reg_d1[5:0];
|
dff #(6) err_reg_dff(.din(err_reg_next[5:0]), .clk(clk), .q(err_reg_d1[5:0]),
|
dff_s #(6) err_reg_dff(.din(err_reg_next[5:0]), .clk(clk), .q(err_reg_d1[5:0]),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
assign ffu_ifu_err_reg_w2[5:0] = err_reg_d1[5:0];
|
assign ffu_ifu_err_reg_w2[5:0] = err_reg_d1[5:0];
|
|
|
// storage of error syndrome for logging
|
// storage of error syndrome for logging
|
// For singles the invalid half of the syndrome is zeroed out.
|
// For singles the invalid half of the syndrome is zeroed out.
|
// The syndrome reported to the ifu will be latched until a new error is detected
|
// The syndrome reported to the ifu will be latched until a new error is detected
|
assign new_err_synd[13:7] = gen_synd_d1[13:7] & {7{chk_ecc_prev[1]}};
|
assign new_err_synd[13:7] = gen_synd_d1[13:7] & {7{chk_ecc_prev[1]}};
|
assign new_err_synd[6:0] = gen_synd_d1[6:0] & {7{chk_ecc_prev[0]}};
|
assign new_err_synd[6:0] = gen_synd_d1[6:0] & {7{chk_ecc_prev[0]}};
|
assign err_synd_next[13:0] = (log_new_err)? new_err_synd: err_synd_d1;
|
assign err_synd_next[13:0] = (log_new_err)? new_err_synd: err_synd_d1;
|
dff #(14) err_synd_d1ff(.din(err_synd_next[13:0]), .clk(clk), .q(err_synd_d1[13:0]),
|
dff_s #(14) err_synd_d1ff(.din(err_synd_next[13:0]), .clk(clk), .q(err_synd_d1[13:0]),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
assign ffu_ifu_err_synd_w2[13:0] = err_synd_d1[13:0];
|
assign ffu_ifu_err_synd_w2[13:0] = err_synd_d1[13:0];
|
|
|
// kill moves and fpu ops
|
// kill moves and fpu ops
|
assign ecc_kill_rs2_w2 = rollback_rs2_w2 | (rs2_ue_w2 & nceen);
|
assign ecc_kill_rs2_w2 = rollback_rs2_w2 | (rs2_ue_w2 & nceen);
|
|
|
|
|
// pipe along enable signal for ue traps
|
// pipe along enable signal for ue traps
|
assign nceen_next = (any_op_e)? ifu_exu_nceen_e: (nceen & ~rollback_fst_w);
|
assign nceen_next = (any_op_e)? ifu_exu_nceen_e: (nceen & ~rollback_fst_w);
|
dff nceen_dff(.din(nceen_next), .clk(clk), .q(nceen),
|
dff_s nceen_dff(.din(nceen_next), .clk(clk), .q(nceen),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
assign ue_trap_w3 = (ue_w3 | bst_ue_c4) & nceen;
|
assign ue_trap_w3 = (ue_w3 | bst_ue_c4) & nceen;
|
|
|
// signals for killing stores on ecc
|
// signals for killing stores on ecc
|
// use this to kill any rs2/rd ce
|
// use this to kill any rs2/rd ce
|
assign ffu_ifu_fst_ce_w = rollback_fst_w;
|
assign ffu_ifu_fst_ce_w = rollback_fst_w;
|
Line 2635... |
Line 1802... |
assign possible_kill_st_ce_m = ((fst_m & ~output_sel_fsr & ~(disable_ce_m & ~nceen)) |
|
assign possible_kill_st_ce_m = ((fst_m & ~output_sel_fsr & ~(disable_ce_m & ~nceen)) |
|
(bst_issue_c3 & ~(fixed_bst_ce & ~nceen)));
|
(bst_issue_c3 & ~(fixed_bst_ce & ~nceen)));
|
assign possible_kill_st_ue_m = (fst_m & ~output_sel_fsr & nceen | bst_issue_c3 & nceen);
|
assign possible_kill_st_ue_m = (fst_m & ~output_sel_fsr & nceen | bst_issue_c3 & nceen);
|
assign kill_st_ce_w = (|previous_ce[1:0]) & possible_kill_st_ce_w;
|
assign kill_st_ce_w = (|previous_ce[1:0]) & possible_kill_st_ce_w;
|
assign ffu_lsu_kill_fst_w = (previous_ue)? possible_kill_st_ue_w: kill_st_ce_w;
|
assign ffu_lsu_kill_fst_w = (previous_ue)? possible_kill_st_ue_w: kill_st_ce_w;
|
dff kill_fst_ce_dff(.din(possible_kill_st_ce_m), .clk(clk), .q(possible_kill_st_ce_w),
|
dff_s kill_fst_ce_dff(.din(possible_kill_st_ce_m), .clk(clk), .q(possible_kill_st_ce_w),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff kill_fst_ue_dff(.din(possible_kill_st_ue_m), .clk(clk), .q(possible_kill_st_ue_w),
|
dff_s kill_fst_ue_dff(.din(possible_kill_st_ue_m), .clk(clk), .q(possible_kill_st_ue_w),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// rollback signals
|
// rollback signals
|
assign rollback_c1_next = rollback_rs2_w2 | rollback_rs1_w3;
|
assign rollback_c1_next = rollback_rs2_w2 | rollback_rs1_w3;
|
dffr #(3) rollback_dff(.din({rollback_c1_next,rollback_c1_vld,rollback_c2}),
|
dffr_s #(3) rollback_dff(.din({rollback_c1_next,rollback_c1_vld,rollback_c2}),
|
.q({rollback_c1, rollback_c2, rollback_c3}),
|
.q({rollback_c1, rollback_c2, rollback_c3}),
|
.clk(clk), .se(se), .si(), .so(), .rst(reset));
|
.clk(clk), .se(se), `SIMPLY_RISC_SCANIN, .so(), .rst(reset));
|
// if both rs1 and rs2 rollback then the state machine needs to start on rs1
|
// if both rs1 and rs2 rollback then the state machine needs to start on rs1
|
assign rollback_c1_vld = rollback_c1 & ~ue_trap_w3 & ~rollback_rs1_w3;
|
assign rollback_c1_vld = rollback_c1 & ~ue_trap_w3 & ~rollback_rs1_w3;
|
|
|
assign rolled_back_next = rollback_c1_vld | rolled_back & ~any_op_e;
|
assign rolled_back_next = rollback_c1_vld | rolled_back & ~any_op_e;
|
dffr rollback_state(.din(rolled_back_next), .q(rolled_back),
|
dffr_s rollback_state(.din(rolled_back_next), .q(rolled_back),
|
.rst(reset), .clk(clk),
|
.rst(reset), .clk(clk),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
//////////////////////////////
|
//////////////////////////////
|
// Performance counter signals
|
// Performance counter signals
|
//////////////////////////////
|
//////////////////////////////
|
assign ffu_tlu_fpu_tid[1:0] = tid[1:0] & {2{is_fpu_result}}; // don't toggle wire if not needed
|
assign ffu_tlu_fpu_tid[1:0] = tid[1:0] & {2{is_fpu_result}}; // don't toggle wire if not needed
|