| Line 17... |
Line 17... |
// License along with this work; if not, write to the Free Software
|
// License along with this work; if not, write to the Free Software
|
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
|
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
|
//
|
//
|
// ========== Copyright Header End ============================================
|
// ========== Copyright Header End ============================================
|
////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////
|
|
`ifdef SIMPLY_RISC_TWEAKS
|
|
`define SIMPLY_RISC_SCANIN .si('h0)
|
|
`else
|
|
`define SIMPLY_RISC_SCANIN .si()
|
|
`endif
|
/*
|
/*
|
// Module Name: sparc_ffu_ctl_visctl
|
// Module Name: sparc_ffu_ctl_visctl
|
// Description: This is the ffu vis control block.
|
// Description: This is the ffu vis control block.
|
*/
|
*/
|
module sparc_ffu_ctl_visctl (/*AUTOARG*/
|
module sparc_ffu_ctl_visctl (/*AUTOARG*/
|
| Line 128... |
Line 133... |
wire visop_w2;
|
wire visop_w2;
|
wire visop_w3;
|
wire visop_w3;
|
wire visop_w3_vld;
|
wire visop_w3_vld;
|
wire add;
|
wire add;
|
wire align;
|
wire align;
|
wire logic_MAYBEARESERVEDWORD;
|
wire logic_wire;
|
wire siam;
|
wire siam;
|
wire alignaddr;
|
wire alignaddr;
|
|
|
wire opf_log_zero;
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wire opf_log_zero;
|
wire opf_log_one;
|
wire opf_log_one;
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| Line 235... |
Line 240... |
// W: rs2 data ready, check rs2 ecc
|
// W: rs2 data ready, check rs2 ecc
|
// W2: rs1 data ready, check rs1 ecc
|
// W2: rs1 data ready, check rs1 ecc
|
// W3: execute vis operation (result written to rs2/rd flop)
|
// W3: execute vis operation (result written to rs2/rd flop)
|
// W4: gen ecc and write to frf
|
// W4: gen ecc and write to frf
|
|
|
dff visop_e2m(.din(issue_visop_e), .clk(clk), .q(visop_m), .si(), .so(), .se(se));
|
dff_s visop_e2m(.din(issue_visop_e), .clk(clk), .q(visop_m), `SIMPLY_RISC_SCANIN, .so(), .se(se));
|
dff visop_m2w(.din(visop_m), .clk(clk), .q(visop_w), .si(), .so(), .se(se));
|
dff_s visop_m2w(.din(visop_m), .clk(clk), .q(visop_w), `SIMPLY_RISC_SCANIN, .so(), .se(se));
|
dff visop_w2w2(.din(visop_w_vld), .clk(clk), .q(visop_w2), .si(), .so(), .se(se));
|
dff_s visop_w2w2(.din(visop_w_vld), .clk(clk), .q(visop_w2), `SIMPLY_RISC_SCANIN, .so(), .se(se));
|
dff visop_w22w3(.din(visop_w2_vld), .clk(clk), .q(visop_w3), .si(), .so(), .se(se));
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dff_s visop_w22w3(.din(visop_w2_vld), .clk(clk), .q(visop_w3), `SIMPLY_RISC_SCANIN, .so(), .se(se));
|
|
|
assign issue_visop_e = visop_e | visop & rollback_c3;
|
assign issue_visop_e = visop_e | visop & rollback_c3;
|
// only check kills in w since they are accumulated into kill_w
|
// only check kills in w since they are accumulated into kill_w
|
assign visop_w_vld = visop_w & ~kill_w;
|
assign visop_w_vld = visop_w & ~kill_w;
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assign visop_w2_vld = visop_w2 & ~flush_w2 & ~rollback_rs2_w2;
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assign visop_w2_vld = visop_w2 & ~flush_w2 & ~rollback_rs2_w2;
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| Line 254... |
Line 259... |
////////////////////////////////////
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////////////////////////////////////
|
// Decode opf
|
// Decode opf
|
////////////////////////////////////
|
////////////////////////////////////
|
assign add = ~opf[8] & ~opf[7] & opf[6] & ~opf[5] & opf[4] & ~opf[3];
|
assign add = ~opf[8] & ~opf[7] & opf[6] & ~opf[5] & opf[4] & ~opf[3];
|
assign align = ~opf[8] & ~opf[7] & opf[6] & ~opf[5] & ~opf[4] & opf[3] & ~opf[2] & ~opf[1] & ~opf[0];
|
assign align = ~opf[8] & ~opf[7] & opf[6] & ~opf[5] & ~opf[4] & opf[3] & ~opf[2] & ~opf[1] & ~opf[0];
|
assign logic_MAYBEARESERVEDWORD = ~opf[8] & ~opf[7] & opf[6] & opf[5];
|
assign logic_wire = ~opf[8] & ~opf[7] & opf[6] & opf[5];
|
assign siam = ~opf[8] & opf[7] & ~opf[6] & ~opf[5] & ~opf[4] & ~opf[3] & ~opf[2] & ~opf[1] & opf[0];
|
assign siam = ~opf[8] & opf[7] & ~opf[6] & ~opf[5] & ~opf[4] & ~opf[3] & ~opf[2] & ~opf[1] & opf[0];
|
assign alignaddr = ~opf[8] & ~opf[7] & ~opf[6] & ~opf[5] & opf[4] & opf[3] & ~opf[2] & ~opf[0]; //alignaddress
|
assign alignaddr = ~opf[8] & ~opf[7] & ~opf[6] & ~opf[5] & opf[4] & opf[3] & ~opf[2] & ~opf[0]; //alignaddress
|
|
|
assign illegal_vis_e = (visop_e & ~(add | align | logic_MAYBEARESERVEDWORD | siam | alignaddr) |
|
assign illegal_vis_e = (visop_e & ~(add | align | logic_wire | siam | alignaddr) |
|
illegal_rs1_e | illegal_rs2_e | illegal_siam_e);
|
illegal_rs1_e | illegal_rs2_e | illegal_siam_e);
|
assign rs1_check_nonzero_e = visop_e & (siam | (logic_MAYBEARESERVEDWORD & (opf_log_zero | opf_log_one | opf_log_src2 | opf_log_not2)));
|
assign rs1_check_nonzero_e = visop_e & (siam | (logic_wire & (opf_log_zero | opf_log_one | opf_log_src2 | opf_log_not2)));
|
assign rs2_check_nonzero_e = visop_e & logic_MAYBEARESERVEDWORD & (opf_log_zero | opf_log_one | opf_log_src1 | opf_log_not1);
|
assign rs2_check_nonzero_e = visop_e & logic_wire & (opf_log_zero | opf_log_one | opf_log_src1 | opf_log_not1);
|
assign illegal_rs1_e = (frs1_e[4:0] != 5'b00000) & rs1_check_nonzero_e;
|
assign illegal_rs1_e = (frs1_e[4:0] != 5'b00000) & rs1_check_nonzero_e;
|
assign illegal_rs2_e = (frs2_e[4:0] != 5'b00000) & rs2_check_nonzero_e;
|
assign illegal_rs2_e = (frs2_e[4:0] != 5'b00000) & rs2_check_nonzero_e;
|
assign illegal_siam_e = ((frd_e[4:0] != 5'b00000) | frs2_e[4] | frs2_e[3]) & siam & visop_e;
|
assign illegal_siam_e = ((frd_e[4:0] != 5'b00000) | frs2_e[4] | frs2_e[3]) & siam & visop_e;
|
|
|
assign vis_nofrf_e = visop_e & (siam | alignaddr | opf_log_zero | opf_log_one);
|
assign vis_nofrf_e = visop_e & (siam | alignaddr | opf_log_zero | opf_log_one);
|
|
|
// controls for add
|
// controls for add
|
// Make subtract come out of its own flop for loading purposes (very critical timing)
|
// Make subtract come out of its own flop for loading purposes (very critical timing)
|
dff sub_dff(.din(opf[2]), .clk(clk), .q(ctl_vis_subtract), .se(se), .si(), .so());
|
dff_s sub_dff(.din(opf[2]), .clk(clk), .q(ctl_vis_subtract), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
assign ctl_vis_cin = opf[2];
|
assign ctl_vis_cin = opf[2];
|
assign ctl_vis_add32 = opf[1];
|
assign ctl_vis_add32 = opf[1];
|
|
|
// controls for logic_MAYBEARESERVEDWORD
|
// controls for logic
|
assign opf_log_zero = ~opf[4] & ~opf[3] & ~opf[2] & ~opf[1];
|
assign opf_log_zero = ~opf[4] & ~opf[3] & ~opf[2] & ~opf[1];
|
assign opf_log_nor = ~opf[4] & ~opf[3] & ~opf[2] & opf[1];
|
assign opf_log_nor = ~opf[4] & ~opf[3] & ~opf[2] & opf[1];
|
assign opf_log_andnot2 = ~opf[4] & ~opf[3] & opf[2] & ~opf[1];
|
assign opf_log_andnot2 = ~opf[4] & ~opf[3] & opf[2] & ~opf[1];
|
assign opf_log_not2 = ~opf[4] & ~opf[3] & opf[2] & opf[1];
|
assign opf_log_not2 = ~opf[4] & ~opf[3] & opf[2] & opf[1];
|
assign opf_log_andnot1 = ~opf[4] & opf[3] & ~opf[2] & ~opf[1];
|
assign opf_log_andnot1 = ~opf[4] & opf[3] & ~opf[2] & ~opf[1];
|
| Line 292... |
Line 297... |
assign opf_log_src2 = opf[4] & opf[3] & ~opf[2] & ~opf[1];
|
assign opf_log_src2 = opf[4] & opf[3] & ~opf[2] & ~opf[1];
|
assign opf_log_ornot1 = opf[4] & opf[3] & ~opf[2] & opf[1];
|
assign opf_log_ornot1 = opf[4] & opf[3] & ~opf[2] & opf[1];
|
assign opf_log_or = opf[4] & opf[3] & opf[2] & ~opf[1];
|
assign opf_log_or = opf[4] & opf[3] & opf[2] & ~opf[1];
|
assign opf_log_one = opf[4] & opf[3] & opf[2] & opf[1];
|
assign opf_log_one = opf[4] & opf[3] & opf[2] & opf[1];
|
|
|
// selects for logic_MAYBEARESERVEDWORD mux
|
// selects for logic mux
|
assign ctl_vis_log_sel_nand = opf_log_or | opf_log_nand | opf_log_ornot1 | opf_log_ornot2;
|
assign ctl_vis_log_sel_nand = opf_log_or | opf_log_nand | opf_log_ornot1 | opf_log_ornot2;
|
assign ctl_vis_log_sel_xor = opf_log_xor | opf_log_xnor;
|
assign ctl_vis_log_sel_xor = opf_log_xor | opf_log_xnor;
|
assign ctl_vis_log_sel_nor = opf_log_and | opf_log_nor | opf_log_andnot1 | opf_log_andnot2;
|
assign ctl_vis_log_sel_nor = opf_log_and | opf_log_nor | opf_log_andnot1 | opf_log_andnot2;
|
assign ctl_vis_log_sel_pass = (opf_log_zero | opf_log_one | opf_log_src1 | opf_log_src2 |
|
assign ctl_vis_log_sel_pass = (opf_log_zero | opf_log_one | opf_log_src1 | opf_log_src2 |
|
opf_log_not1 | opf_log_not2);
|
opf_log_not1 | opf_log_not2);
|
|
|
assign invert_rs1_next = (opf_log_not1 | opf_log_or | opf_log_and |
|
assign invert_rs1_next = (opf_log_not1 | opf_log_or | opf_log_and |
|
opf_log_ornot2 | opf_log_andnot2);
|
opf_log_ornot2 | opf_log_andnot2);
|
assign invert_rs2_next = (opf_log_not2 | opf_log_or | opf_log_and |
|
assign invert_rs2_next = (opf_log_not2 | opf_log_or | opf_log_and |
|
opf_log_ornot1 | opf_log_andnot1 | opf_log_xnor);
|
opf_log_ornot1 | opf_log_andnot1 | opf_log_xnor);
|
dff invert_rs1_dff(.din(invert_rs1_next), .clk(clk), .q(ctl_vis_log_invert_rs1),
|
dff_s invert_rs1_dff(.din(invert_rs1_next), .clk(clk), .q(ctl_vis_log_invert_rs1),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff invert_rs2_dff(.din(invert_rs2_next), .clk(clk), .q(ctl_vis_log_invert_rs2),
|
dff_s invert_rs2_dff(.din(invert_rs2_next), .clk(clk), .q(ctl_vis_log_invert_rs2),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
// precalculate to help timing
|
// precalculate to help timing
|
assign log_pass_rs1_next = opf_log_src1 | opf_log_not1;
|
assign log_pass_rs1_next = opf_log_src1 | opf_log_not1;
|
assign log_pass_rs2_next = opf_log_src2 | opf_log_not2;
|
assign log_pass_rs2_next = opf_log_src2 | opf_log_not2;
|
dff #(2) log_pass_dff(.din({log_pass_rs1_next,log_pass_rs2_next}), .clk(clk),
|
dff_s #(2) log_pass_dff(.din({log_pass_rs1_next,log_pass_rs2_next}), .clk(clk),
|
.q({log_pass_rs1,log_pass_rs2}), .se(se), .si(), .so());
|
.q({log_pass_rs1,log_pass_rs2}), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign ctl_vis_log_pass_rs1 = log_pass_rs1;
|
assign ctl_vis_log_pass_rs1 = log_pass_rs1;
|
assign ctl_vis_log_pass_rs2 = log_pass_rs2 & ~log_pass_rs1;
|
assign ctl_vis_log_pass_rs2 = log_pass_rs2 & ~log_pass_rs1;
|
assign ctl_vis_log_constant = opf_log_one;
|
assign ctl_vis_log_constant = opf_log_one;
|
assign ctl_vis_log_pass_const = ~(ctl_vis_log_pass_rs1 | ctl_vis_log_pass_rs2);
|
assign ctl_vis_log_pass_const = ~(ctl_vis_log_pass_rs1 | ctl_vis_log_pass_rs2);
|
| Line 352... |
Line 357... |
.in3({t3_gsr_rnd[2:0], t3_gsr_align[2:0]}),
|
.in3({t3_gsr_rnd[2:0], t3_gsr_align[2:0]}),
|
.sel0(ctl_dp_thr_e[0]),
|
.sel0(ctl_dp_thr_e[0]),
|
.sel1(ctl_dp_thr_e[1]),
|
.sel1(ctl_dp_thr_e[1]),
|
.sel2(ctl_dp_thr_e[2]),
|
.sel2(ctl_dp_thr_e[2]),
|
.sel3(ctl_dp_thr_e[3]));
|
.sel3(ctl_dp_thr_e[3]));
|
dff #(43) gsr_e2m(.din({dp_ctl_gsr_mask_e[31:0],gsr_rnd_e[2:0],
|
dff_s #(43) gsr_e2m(.din({dp_ctl_gsr_mask_e[31:0],gsr_rnd_e[2:0],
|
dp_ctl_gsr_scale_e[4:0],gsr_align_e[2:0]}), .clk(clk),
|
dp_ctl_gsr_scale_e[4:0],gsr_align_e[2:0]}), .clk(clk),
|
.q({ffu_exu_rsr_data_hi_m[31:0],ffu_exu_rsr_data_mid_m[2:0], ffu_exu_rsr_data_lo_m[7:0]}),
|
.q({ffu_exu_rsr_data_hi_m[31:0],ffu_exu_rsr_data_mid_m[2:0], ffu_exu_rsr_data_lo_m[7:0]}),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff #(3) gsr_align_dff(.din(gsr_align[2:0]), .clk(clk), .q(gsr_align_d1[2:0]), .se(se), .si(), .so());
|
dff_s #(3) gsr_align_dff(.din(gsr_align[2:0]), .clk(clk), .q(gsr_align_d1[2:0]), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// put in to help timing for sending to lsu
|
// put in to help timing for sending to lsu
|
dff #(2) fpu_rnd_dff(.din(fpu_rnd_next[1:0]), .clk(clk), .q(fpu_rnd[1:0]), .si(), .so(), .se(se));
|
dff_s #(2) fpu_rnd_dff(.din(fpu_rnd_next[1:0]), .clk(clk), .q(fpu_rnd[1:0]), `SIMPLY_RISC_SCANIN, .so(), .se(se));
|
assign fpu_rnd_next[1:0] = (gsr_rnd[2])? gsr_rnd[1:0]: dp_ctl_fsr_rnd[1:0];
|
assign fpu_rnd_next[1:0] = (gsr_rnd[2])? gsr_rnd[1:0]: dp_ctl_fsr_rnd[1:0];
|
|
|
// if alignaddress_little then write the 2's complement
|
// if alignaddress_little then write the 2's complement
|
assign align_addr_data_w2[2:0] = (opf[1])? (~wgsr_align_offset_w2[2:0] + 3'b001):
|
assign align_addr_data_w2[2:0] = (opf[1])? (~wgsr_align_offset_w2[2:0] + 3'b001):
|
wgsr_align_offset_w2[2:0];
|
wgsr_align_offset_w2[2:0];
|
|
|
assign gsr_addr_d = (ifu_tlu_sraddr_d[6:0] == 7'b0010011);
|
assign gsr_addr_d = (ifu_tlu_sraddr_d[6:0] == 7'b0010011);
|
assign wgsr_e = exu_ffu_wsr_inst_e & gsr_addr_e;
|
assign wgsr_e = exu_ffu_wsr_inst_e & gsr_addr_e;
|
dff gsr_addr_d2e(.din(gsr_addr_d), .clk(clk), .q(gsr_addr_e), .se(se), .si(), .so());
|
dff_s gsr_addr_d2e(.din(gsr_addr_d), .clk(clk), .q(gsr_addr_e), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// need independent kill checks because this isn't killed by new fpop
|
// need independent kill checks because this isn't killed by new fpop
|
assign wgsr_vld_m = wgsr_m & ~(thr_match_mw2 & flush_w2);
|
assign wgsr_vld_m = wgsr_m & ~(thr_match_mw2 & flush_w2);
|
assign wgsr_vld_w = wgsr_w & ifu_tlu_inst_vld_w & ~(thr_match_ww2 & flush_w2);
|
assign wgsr_vld_w = wgsr_w & ifu_tlu_inst_vld_w & ~(thr_match_ww2 & flush_w2);
|
assign wgsr_vld_w2 = wgsr_w2 & ~flush_w2;
|
assign wgsr_vld_w2 = wgsr_w2 & ~flush_w2;
|
dff wgsr_e2m(.din(wgsr_e), .clk(clk), .q(wgsr_m), .si(), .so(), .se(se));
|
dff_s wgsr_e2m(.din(wgsr_e), .clk(clk), .q(wgsr_m), `SIMPLY_RISC_SCANIN, .so(), .se(se));
|
dff wgsr_m2w(.din(wgsr_vld_m), .clk(clk), .q(wgsr_w), .si(), .so(), .se(se));
|
dff_s wgsr_m2w(.din(wgsr_vld_m), .clk(clk), .q(wgsr_w), `SIMPLY_RISC_SCANIN, .so(), .se(se));
|
dff wgsr_w2w2(.din(wgsr_vld_w), .clk(clk), .q(wgsr_w2), .si(), .so(), .se(se));
|
dff_s wgsr_w2w2(.din(wgsr_vld_w), .clk(clk), .q(wgsr_w2), `SIMPLY_RISC_SCANIN, .so(), .se(se));
|
|
|
assign thr_w2[3] = (tid_w2[1:0] == 2'b11);
|
assign thr_w2[3] = (tid_w2[1:0] == 2'b11);
|
assign thr_w2[2] = (tid_w2[1:0] == 2'b10);
|
assign thr_w2[2] = (tid_w2[1:0] == 2'b10);
|
assign thr_w2[1] = (tid_w2[1:0] == 2'b01);
|
assign thr_w2[1] = (tid_w2[1:0] == 2'b01);
|
assign thr_w2[0] = (tid_w2[1:0] == 2'b00);
|
assign thr_w2[0] = (tid_w2[1:0] == 2'b00);
|
| Line 473... |
Line 478... |
.sel0(t3_align_wen_l),
|
.sel0(t3_align_wen_l),
|
.sel1(t3_gsr_wsr_w2),
|
.sel1(t3_gsr_wsr_w2),
|
.sel2(t3_alignaddr_w2));
|
.sel2(t3_alignaddr_w2));
|
|
|
|
|
dffr #(6) t0_gsr_dff(.din({t0_gsr_rnd_next[2:0], t0_gsr_align_next[2:0]}), .clk(clk),
|
dffr_s #(6) t0_gsr_dff(.din({t0_gsr_rnd_next[2:0], t0_gsr_align_next[2:0]}), .clk(clk),
|
.q({t0_gsr_rnd[2:0], t0_gsr_align[2:0]}), .se(se),
|
.q({t0_gsr_rnd[2:0], t0_gsr_align[2:0]}), .se(se),
|
.si(), .so(), .rst(reset));
|
`SIMPLY_RISC_SCANIN, .so(), .rst(reset));
|
dffr #(6) t1_gsr_dff(.din({t1_gsr_rnd_next[2:0], t1_gsr_align_next[2:0]}), .clk(clk),
|
dffr_s #(6) t1_gsr_dff(.din({t1_gsr_rnd_next[2:0], t1_gsr_align_next[2:0]}), .clk(clk),
|
.q({t1_gsr_rnd[2:0], t1_gsr_align[2:0]}), .se(se),
|
.q({t1_gsr_rnd[2:0], t1_gsr_align[2:0]}), .se(se),
|
.si(), .so(), .rst(reset));
|
`SIMPLY_RISC_SCANIN, .so(), .rst(reset));
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dffr #(6) t2_gsr_dff(.din({t2_gsr_rnd_next[2:0], t2_gsr_align_next[2:0]}), .clk(clk),
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dffr_s #(6) t2_gsr_dff(.din({t2_gsr_rnd_next[2:0], t2_gsr_align_next[2:0]}), .clk(clk),
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.q({t2_gsr_rnd[2:0], t2_gsr_align[2:0]}), .se(se),
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.q({t2_gsr_rnd[2:0], t2_gsr_align[2:0]}), .se(se),
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.si(), .so(), .rst(reset));
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`SIMPLY_RISC_SCANIN, .so(), .rst(reset));
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dffr #(6) t3_gsr_dff(.din({t3_gsr_rnd_next[2:0], t3_gsr_align_next[2:0]}), .clk(clk),
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dffr_s #(6) t3_gsr_dff(.din({t3_gsr_rnd_next[2:0], t3_gsr_align_next[2:0]}), .clk(clk),
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.q({t3_gsr_rnd[2:0], t3_gsr_align[2:0]}), .se(se),
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.q({t3_gsr_rnd[2:0], t3_gsr_align[2:0]}), .se(se),
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.si(), .so(), .rst(reset));
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`SIMPLY_RISC_SCANIN, .so(), .rst(reset));
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dffre #(3) siam_rnd_dff(.din(ifu_ffu_rnd_e[2:0]), .clk(clk),
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dffre_s #(3) siam_rnd_dff(.din(ifu_ffu_rnd_e[2:0]), .clk(clk),
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.q(siam_rnd), .se(se), .si(), .so(),
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.q(siam_rnd), .se(se), `SIMPLY_RISC_SCANIN, .so(),
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.rst(reset), .en(visop_e));
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.rst(reset), .en(visop_e));
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dff #(3) align_offset_dff1(.din(exu_ffu_gsr_align_m[2:0]), .clk(clk),
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dff_s #(3) align_offset_dff1(.din(exu_ffu_gsr_align_m[2:0]), .clk(clk),
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.q(wgsr_align_offset_w[2:0]), .se(se), .si(), .so());
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.q(wgsr_align_offset_w[2:0]), .se(se), `SIMPLY_RISC_SCANIN, .so());
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dff #(3) align_offset_dff2(.din(wgsr_align_offset_w[2:0]), .clk(clk),
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dff_s #(3) align_offset_dff2(.din(wgsr_align_offset_w[2:0]), .clk(clk),
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.q(wgsr_align_offset_w2[2:0]), .se(se), .si(), .so());
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.q(wgsr_align_offset_w2[2:0]), .se(se), `SIMPLY_RISC_SCANIN, .so());
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dff #(3) rnd_dff1(.din(exu_ffu_gsr_rnd_m[2:0]), .clk(clk),
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dff_s #(3) rnd_dff1(.din(exu_ffu_gsr_rnd_m[2:0]), .clk(clk),
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.q(wgsr_rnd_w[2:0]), .se(se), .si(), .so());
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.q(wgsr_rnd_w[2:0]), .se(se), `SIMPLY_RISC_SCANIN, .so());
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dff #(3) rnd_dff2(.din(wgsr_rnd_w[2:0]), .clk(clk),
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dff_s #(3) rnd_dff2(.din(wgsr_rnd_w[2:0]), .clk(clk),
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.q(wgsr_rnd_w2[2:0]), .se(se), .si(), .so());
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.q(wgsr_rnd_w2[2:0]), .se(se), `SIMPLY_RISC_SCANIN, .so());
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assign wsr_data_m[36:0] = {exu_ffu_gsr_mask_m[31:0], exu_ffu_gsr_scale_m[4:0]};
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assign wsr_data_m[36:0] = {exu_ffu_gsr_mask_m[31:0], exu_ffu_gsr_scale_m[4:0]};
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dff #(37) wsr_data_m2w(.din(wsr_data_m[36:0]), .clk(clk), .q(wsr_data_w[36:0]),
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dff_s #(37) wsr_data_m2w(.din(wsr_data_m[36:0]), .clk(clk), .q(wsr_data_w[36:0]),
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.se(se), .si(), .so());
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.se(se), `SIMPLY_RISC_SCANIN, .so());
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dff #(37) wsr_data_w2w2(.din(wsr_data_w[36:0]), .clk(clk), .q(ctl_dp_wsr_data_w2[36:0]),
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dff_s #(37) wsr_data_w2w2(.din(wsr_data_w[36:0]), .clk(clk), .q(ctl_dp_wsr_data_w2[36:0]),
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.se(se), .si(), .so());
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.se(se), `SIMPLY_RISC_SCANIN, .so());
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endmodule // sparc_ffu_ctl_visctl
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endmodule // sparc_ffu_ctl_visctl
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