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[/] [s1_core/] [trunk/] [hdl/] [rtl/] [sparc_core/] [sparc_ffu_dp.v] - Diff between revs 105 and 113

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Rev 105 Rev 113
Line 17... Line 17... 
// License along with this work; if not, write to the Free Software
 
// License along with this work; if not, write to the Free Software
 
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
 
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
 
// 
// 
// ========== Copyright Header End ============================================
 
// ========== Copyright Header End ============================================
 
///////////////////////////////////////////////////////////////////////
 
///////////////////////////////////////////////////////////////////////
 
 
 
`ifdef SIMPLY_RISC_TWEAKS
 
 
 
`define SIMPLY_RISC_SCANIN .si(0)
 
 
 
`else
 
 
 
`define SIMPLY_RISC_SCANIN .si()
 
 
 
`endif
 
/*
 
/*
 
//  Module Name: sparc_ffu_dp
 
//  Module Name: sparc_ffu_dp
 
//      Description: This is the ffu datapath.  It stores the 2 128 bit operands
 
//      Description: This is the ffu datapath.  It stores the 2 128 bit operands
 
//      and the result (puts result in the 1st source to save space).
 
//      and the result (puts result in the 1st source to save space).
 
*/
 
*/
 
 
 
 
 
/*
 
`include "iop.h"
 
/* ========== Copyright Header Begin ==========================================
 
 
 
*
 
 
 
* OpenSPARC T1 Processor File: iop.h
 
 
 
* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
 
 
 
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
 
 
 
*
 
 
 
* The above named program is free software; you can redistribute it and/or
 
 
 
* modify it under the terms of the GNU General Public
 
 
 
* License version 2 as published by the Free Software Foundation.
 
 
 
*
 
 
 
* The above named program is distributed in the hope that it will be
 
 
 
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
 
 
 
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 
 
 
* General Public License for more details.
 
 
 
*
 
 
 
* You should have received a copy of the GNU General Public
 
 
 
* License along with this work; if not, write to the Free Software
 
 
 
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
 
 
 
*
 
 
 
* ========== Copyright Header End ============================================
 
 
 
*/
 
 
 
//-*- verilog -*-
 
 
 
////////////////////////////////////////////////////////////////////////
 
 
 
/*
 
 
 
//
 
 
 
//  Description:        Global header file that contain definitions that
 
 
 
//                      are common/shared at the IOP chip level
 
 
 
*/
 
 
 
////////////////////////////////////////////////////////////////////////
 
 
 
 
 
 
 
 
 
 
 
// Address Map Defines
 
 
 
// ===================
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// CMP space
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// IOP space
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
                               //`define ENET_ING_CSR     8'h84
 
 
 
                               //`define ENET_EGR_CMD_CSR 8'h85
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// L2 space
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// More IOP space
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//Cache Crossbar Width and Field Defines
 
 
 
//======================================
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//bits 133:128 are shared by different fields
 
 
 
//for different packet types.
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//End cache crossbar defines
 
 
 
 
 
 
 
 
 
 
 
// Number of COS supported by EECU 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// 
 
 
// BSC bus sizes
 
 
 
// =============
 
 
 
//
 
 
 
 
 
 
 
// General
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// CTags
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// reinstated temporarily
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// CoS
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// L2$ Bank
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// L2$ Req
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// L2$ Ack
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Enet Egress Command Unit
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Enet Egress Packet Unit
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// This is cleaved in between Egress Datapath Ack's
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Enet Egress Datapath
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// In-Order / Ordered Queue: EEPU
 
 
 
// Tag is: TLEN, SOF, EOF, QID = 15
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Nack + Tag Info + CTag
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// ENET Ingress Queue Management Req
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// ENET Ingress Queue Management Ack
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Enet Ingress Packet Unit
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// ENET Ingress Packet Unit Ack
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// In-Order / Ordered Queue: PCI
 
 
 
// Tag is: CTAG
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// PCI-X Request
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// PCI_X Acknowledge
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// BSC array sizes
 
 
 
//================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// ECC syndrome bits per memory element
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// BSC Port Definitions
 
 
 
// ====================
 
 
 
//
 
 
 
// Bits 7 to 4 of curr_port_id
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Number of ports of each type
 
 
 
 
 
 
 
 
 
 
 
// Bits needed to represent above
 
 
 
 
 
 
 
 
 
 
 
// How wide the linked list pointers are
 
 
 
// 60b for no payload (2CoS)
 
 
 
// 80b for payload (2CoS)
 
 
 
 
 
 
 
//`define BSC_OBJ_PTR   80
 
 
 
//`define BSC_HD1_HI    69
 
 
 
//`define BSC_HD1_LO    60
 
 
 
//`define BSC_TL1_HI    59
 
 
 
//`define BSC_TL1_LO    50
 
 
 
//`define BSC_CT1_HI    49
 
 
 
//`define BSC_CT1_LO    40
 
 
 
//`define BSC_HD0_HI    29
 
 
 
//`define BSC_HD0_LO    20
 
 
 
//`define BSC_TL0_HI    19
 
 
 
//`define BSC_TL0_LO    10
 
 
 
//`define BSC_CT0_HI     9
 
 
 
//`define BSC_CT0_LO     0
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// I2C STATES in DRAMctl
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// IOB defines
 
 
 
// ===========
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//`define IOB_INT_STAT_WIDTH   32
 
 
 
//`define IOB_INT_STAT_HI      31
 
 
 
//`define IOB_INT_STAT_LO       0
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// fixme - double check address mapping
 
 
 
// CREG in `IOB_INT_CSR space
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// CREG in `IOB_MAN_CSR space
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Address map for TAP access of SPARC ASI
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// CIOP UCB Bus Width
 
 
 
// ==================
 
 
 
//
 
 
 
//`define IOB_EECU_WIDTH       16  // ethernet egress command
 
 
 
//`define EECU_IOB_WIDTH       16
 
 
 
 
 
 
 
//`define IOB_NRAM_WIDTH       16  // NRAM (RLDRAM previously)
 
 
 
//`define NRAM_IOB_WIDTH        4
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//`define IOB_ENET_ING_WIDTH   32  // ethernet ingress
 
 
 
//`define ENET_ING_IOB_WIDTH    8
 
 
 
 
 
 
 
//`define IOB_ENET_EGR_WIDTH    4  // ethernet egress
 
 
 
//`define ENET_EGR_IOB_WIDTH    4
 
 
 
 
 
 
 
//`define IOB_ENET_MAC_WIDTH    4  // ethernet MAC
 
 
 
//`define ENET_MAC_IOB_WIDTH    4
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//`define IOB_BSC_WIDTH         4  // BSC
 
 
 
//`define BSC_IOB_WIDTH         4
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//`define IOB_CLSP_WIDTH        4  // clk spine unit
 
 
 
//`define CLSP_IOB_WIDTH        4
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// CIOP UCB Buf ID Type
 
 
 
// ====================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// Interrupt Device ID
 
 
 
// ===================
 
 
 
//
 
 
 
// Caution: DUMMY_DEV_ID has to be 9 bit wide
 
 
 
//          for fields to line up properly in the IOB.
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// Soft Error related definitions 
 
 
// ==============================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// CMP clock
 
 
 
// =========
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// NRAM/IO Interface
 
 
 
// =================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// NRAM/ENET Interface
 
 
 
// ===================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// IO/FCRAM Interface
 
 
 
// ==================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// PCI Interface
 
 
 
// ==================
 
 
 
// Load/store size encodings
 
 
 
// -------------------------
 
 
 
// Size encoding
 
 
 
// 000 - byte
 
 
 
// 001 - half-word
 
 
 
// 010 - word
 
 
 
// 011 - double-word
 
 
 
// 100 - quad
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// JBI<->SCTAG Interface
 
 
 
// =======================
 
 
 
// Outbound Header Format
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Inbound Header Format
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// JBI->IOB Mondo Header Format
 
 
 
// ============================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// JBI->IOB Mondo Bus Width/Cycle
 
 
 
// ==============================
 
 
 
// Cycle  1 Header[15:8]
 
 
 
// Cycle  2 Header[ 7:0]
 
 
 
// Cycle  3 J_AD[127:120]
 
 
 
// Cycle  4 J_AD[119:112]
 
 
 
// .....
 
 
 
// Cycle 18 J_AD[  7:  0]
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
module sparc_ffu_dp (/*AUTOARG*/
 
module sparc_ffu_dp (/*AUTOARG*/
 
   // Outputs
 
   // Outputs
 
   so, dp_frf_data, ffu_lsu_data, dp_vis_rs1_data, dp_vis_rs2_data,
 
   so, dp_frf_data, ffu_lsu_data, dp_vis_rs1_data, dp_vis_rs2_data,
 
   dp_ctl_rs2_sign, dp_ctl_fsr_fcc, dp_ctl_fsr_rnd, dp_ctl_fsr_tem,
 
   dp_ctl_rs2_sign, dp_ctl_fsr_fcc, dp_ctl_fsr_rnd, dp_ctl_fsr_tem,
Line 1014... Line 181... 
   wire [36:0]   t3_gsr_nxt;
 
   wire [36:0]   t3_gsr_nxt;
 
 
 
 
 
   assign        reset = ~ctl_dp_rst_l;
 
   assign        reset = ~ctl_dp_rst_l;
 
   assign        clk= rclk;
 
   assign        clk= rclk;
 
 
 
 
 
   dff #(64) cpx_reg(.din(cpx_fpu_data[63:0]),
 
   dff_s #(64) cpx_reg(.din(cpx_fpu_data[63:0]),
 
                                       .q   (fpu_ffu_data[63:0]),
 
                                       .q   (fpu_ffu_data[63:0]),
 
                                       .clk (clk), .se(se), .si(), .so());
 
                                       .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
 
 
 
 
 
   // flop for lsu data.  the data is flopped in ffu, but the vld is flopped in the lsu.
 
   // flop for lsu data.  the data is flopped in ffu, but the vld is flopped in the lsu.
 
   // This is for timing reasons on the valid bit and Sanjay didn't want to redo the
 
   // This is for timing reasons on the valid bit and Sanjay didn't want to redo the
 
   // lsu dp for the data portion
 
   // lsu dp for the data portion
 
   dff #(64) lsu_data_dff(.din(lsu_ffu_ld_data[63:0]), .clk(clk), .q(lsu_ffu_ld_data_d1[63:0]),
 
   dff_s #(64) lsu_data_dff(.din(lsu_ffu_ld_data[63:0]), .clk(clk), .q(lsu_ffu_ld_data_d1[63:0]),
 
                          .se(se), .si(), .so());
 
                          .se(se), `SIMPLY_RISC_SCANIN, .so());
 
   assign dp_ctl_ld_fcc[7:0] = {lsu_ffu_ld_data_d1[37:32], lsu_ffu_ld_data_d1[11:10]};
 
   assign dp_ctl_ld_fcc[7:0] = {lsu_ffu_ld_data_d1[37:32], lsu_ffu_ld_data_d1[11:10]};
 
 
 
 
 
   ///////////////////////////////////////////////
 
   ///////////////////////////////////////////////
 
   //   Input from FRF (shift as needed for singles)
 
   //   Input from FRF (shift as needed for singles)
 
   //   The data needs to be shifted around because these are 64 bit reads but
 
   //   The data needs to be shifted around because these are 64 bit reads but
Line 1100... Line 267... 
                           .sel0 (ctl_dp_rs2_frf_read),
 
                           .sel0 (ctl_dp_rs2_frf_read),
 
                           .sel1 (ctl_dp_rs2_sel_vis),
 
                           .sel1 (ctl_dp_rs2_sel_vis),
 
                           .sel2 (ctl_dp_rs2_sel_fpu_lsu),
 
                           .sel2 (ctl_dp_rs2_sel_fpu_lsu),
 
                           .sel3 (ctl_dp_rs2_keep_data));
 
                           .sel3 (ctl_dp_rs2_keep_data));
 
 
 
 
 
   dff #(64) rs2_rd_dff(.din (rs2_rd_data_next[63:0]),
 
   dff_s #(64) rs2_rd_dff(.din (rs2_rd_data_next[63:0]),
 
                                          .q   (rs2_rd_data[63:0]),
 
                                          .q   (rs2_rd_data[63:0]),
 
                                          .clk (clk), .se(se), .si(), .so());
 
                                          .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
 
   assign dp_vis_rs2_data[63:0] = rs2_rd_data[63:0];
 
   assign dp_vis_rs2_data[63:0] = rs2_rd_data[63:0];
 
   dff #(64) write_data_dff(.din(rs2_rd_data[63:0]),
 
   dff_s #(64) write_data_dff(.din(rs2_rd_data[63:0]),
 
                            .q(write_data[63:0]),
 
                            .q(write_data[63:0]),
 
                            .clk(clk), .se(se), .si(), .so());
 
                            .clk(clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
 
 
 
 
 
   ////////////////////////////////////////////////////////
 
   ////////////////////////////////////////////////////////
 
   //                   RS1
 
   //                   RS1
 
   ////////////////////////////////////////////////////////
 
   ////////////////////////////////////////////////////////
 
   // RS1 next either takes value from frf or keeps value
 
   // RS1 next either takes value from frf or keeps value
 
   dp_mux2es #(64) rs1_mux(.dout (rs1_data_next[63:0]),
 
   dp_mux2es #(64) rs1_mux(.dout (rs1_data_next[63:0]),
 
                           .in0  (rs1_data[63:0]),
 
                           .in0  (rs1_data[63:0]),
 
                           .in1  (new_frf_data[63:0]),
 
                           .in1  (new_frf_data[63:0]),
 
                           .sel  (ctl_dp_new_rs1));
 
                           .sel  (ctl_dp_new_rs1));
 
 
 
 
 
   dff #(64) rs1_dff(.din (rs1_data_next[63:0]),
 
   dff_s #(64) rs1_dff(.din (rs1_data_next[63:0]),
 
                                 .q   (rs1_data[63:0]),
 
                                 .q   (rs1_data[63:0]),
 
                                 .clk (clk), .se(se), .si(), .so());
 
                                 .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
 
   assign dp_vis_rs1_data[63:0] = rs1_data[63:0];
 
   assign dp_vis_rs1_data[63:0] = rs1_data[63:0];
 
 
 
 
 
 
 
 
 
   /////////////////////////////////////////////////////////
 
   /////////////////////////////////////////////////////////
 
   //                   FSR
 
   //                   FSR
Line 1192... Line 359... 
                                                    t3_fsr[19:15],  // TEM
 
                                                    t3_fsr[19:15],  // TEM
 
                                                    ctl_dp_ftt_w2[2:0],  // ftt
 
                                                    ctl_dp_ftt_w2[2:0],  // ftt
 
                                                    ctl_dp_fcc_w2[1:0],
 
                                                    ctl_dp_fcc_w2[1:0],
 
                                                    ctl_dp_exc_w2[9:0]};
 
                                                    ctl_dp_exc_w2[9:0]};
 
 
 
 
 
 
 
`ifdef FPGA_SYN_1THREAD
 
 
 
 
 
 
 
   mux3ds #28 fsr0_mux(.dout (t0_fsr_nxt[27:0]),
 
 
 
                       .in0  (t0_fsr[27:0]),
 
 
 
                       .in1  (t0_ldfsr_data[27:0]),
 
 
 
                       .in2  (t0_fpufsr_data[27:0]),
 
 
 
                       .sel0 (ctl_dp_fsr_sel_old[0]),
 
 
 
                       .sel1 (ctl_dp_fsr_sel_ld[0]),
 
 
 
                       .sel2 (ctl_dp_fsr_sel_fpu[0]));
 
 
 
   // FSR registers
 
 
 
   // need only 28 flops for FSR since rest are always 0
 
 
 
   dffr_s #28 fsr0_reg(.din (t0_fsr_nxt[27:0]),
 
 
 
                                 .q   (t0_fsr[27:0]),
 
 
 
                     .rst(reset),
 
 
 
                                 .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
 
 
 
   assign current_fsr[27:0] = t0_fsr[27:0];
 
 
 
 
 
 
 
`else
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
   mux3ds #28 fsr0_mux(.dout (t0_fsr_nxt[27:0]),
 
   mux3ds #28 fsr0_mux(.dout (t0_fsr_nxt[27:0]),
 
                       .in0  (t0_fsr[27:0]),
 
                       .in0  (t0_fsr[27:0]),
 
                       .in1  (t0_ldfsr_data[27:0]),
 
                       .in1  (t0_ldfsr_data[27:0]),
 
                       .in2  (t0_fpufsr_data[27:0]),
 
                       .in2  (t0_fpufsr_data[27:0]),
Line 1242... Line 409... 
                       .sel1 (ctl_dp_fsr_sel_ld[3]),
 
                       .sel1 (ctl_dp_fsr_sel_ld[3]),
 
                       .sel2 (ctl_dp_fsr_sel_fpu[3]));
 
                       .sel2 (ctl_dp_fsr_sel_fpu[3]));
 
 
 
 
 
   // FSR registers
 
   // FSR registers
 
   // need only 28 flops for FSR since rest are always 0
 
   // need only 28 flops for FSR since rest are always 0
 
   dffr #28 fsr0_reg(.din (t0_fsr_nxt[27:0]),
 
   dffr_s #28 fsr0_reg(.din (t0_fsr_nxt[27:0]),
 
                                 .q   (t0_fsr[27:0]),
 
                                 .q   (t0_fsr[27:0]),
 
                     .rst(reset),
 
                     .rst(reset),
 
                                 .clk (clk), .se(se), .si(), .so());
 
                                 .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
 
   dffr #28 fsr1_reg(.din (t1_fsr_nxt[27:0]),
 
   dffr_s #28 fsr1_reg(.din (t1_fsr_nxt[27:0]),
 
                                 .q   (t1_fsr[27:0]),
 
                                 .q   (t1_fsr[27:0]),
 
                     .rst(reset),
 
                     .rst(reset),
 
                                 .clk (clk), .se(se), .si(), .so());
 
                                 .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
 
   dffr #28 fsr2_reg(.din (t2_fsr_nxt[27:0]),
 
   dffr_s #28 fsr2_reg(.din (t2_fsr_nxt[27:0]),
 
                                 .q   (t2_fsr[27:0]),
 
                                 .q   (t2_fsr[27:0]),
 
                     .rst(reset),
 
                     .rst(reset),
 
                                 .clk (clk), .se(se), .si(), .so());
 
                                 .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
 
   dffr #28 fsr3_reg(.din (t3_fsr_nxt[27:0]),
 
   dffr_s #28 fsr3_reg(.din (t3_fsr_nxt[27:0]),
 
                                 .q   (t3_fsr[27:0]),
 
                                 .q   (t3_fsr[27:0]),
 
                     .rst(reset),
 
                     .rst(reset),
 
                                 .clk (clk), .se(se), .si(), .so());
 
                                 .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
 
 
 
 
 
   // Current FSR
 
   // Current FSR
 
   mux4ds #28 curr_fsr_mux(.dout (current_fsr[27:0]),
 
   mux4ds #28 curr_fsr_mux(.dout (current_fsr[27:0]),
 
                           .in0  (t0_fsr[27:0]),
 
                           .in0  (t0_fsr[27:0]),
 
                           .in1  (t1_fsr[27:0]),
 
                           .in1  (t1_fsr[27:0]),
Line 1269... Line 436... 
                           .in3  (t3_fsr[27:0]),
 
                           .in3  (t3_fsr[27:0]),
 
                           .sel0 (ctl_dp_fp_thr[0]),
 
                           .sel0 (ctl_dp_fp_thr[0]),
 
                           .sel1 (ctl_dp_fp_thr[1]),
 
                           .sel1 (ctl_dp_fp_thr[1]),
 
                           .sel2 (ctl_dp_fp_thr[2]),
 
                           .sel2 (ctl_dp_fp_thr[2]),
 
                           .sel3 (ctl_dp_fp_thr[3]));
 
                           .sel3 (ctl_dp_fp_thr[3]));
 
 // !`ifdef FPGA_SYN_1THREAD
 
`endif // !`ifdef FPGA_SYN_1THREAD
 
 
 
 
 
   assign dp_ctl_fsr_fcc = {current_fsr[27:22], current_fsr[11:10]};
 
   assign dp_ctl_fsr_fcc = {current_fsr[27:22], current_fsr[11:10]};
 
   assign dp_ctl_fsr_rnd = current_fsr[21:20];
 
   assign dp_ctl_fsr_rnd = current_fsr[21:20];
 
   assign dp_ctl_fsr_tem = current_fsr[19:15];
 
   assign dp_ctl_fsr_tem = current_fsr[19:15];
 
   assign dp_ctl_fsr_aexc = current_fsr[9:5];
 
   assign dp_ctl_fsr_aexc = current_fsr[9:5];
Line 1301... Line 468... 
                                .dout(corr_data_next[63:32]),
 
                                .dout(corr_data_next[63:32]),
 
                                .pflag(dp_ctl_synd_out_high[6]),
 
                                .pflag(dp_ctl_synd_out_high[6]),
 
                                .cflag(dp_ctl_synd_out_high[5:0]));
 
                                .cflag(dp_ctl_synd_out_high[5:0]));
 
 
 
 
 
 
 
 
 
   dff #(64) ecc_corr_data(.din(corr_data_next[63:0]), .q(corr_data[63:0]),
 
   dff_s #(64) ecc_corr_data(.din(corr_data_next[63:0]), .q(corr_data[63:0]),
 
                           .clk(clk), .se(se), .si(), .so());
 
                           .clk(clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
 
 
 
 
 
 
 
 
 
   ////////////////////////////////////////////////
 
   ////////////////////////////////////////////////
 
   // GSR Storage
 
   // GSR Storage
 
   ////////////////////////////////////////////////
 
   ////////////////////////////////////////////////
 
   // GSR registers
 
   // GSR registers
 
   // need only 37 flops for GSR since rest are always 0
 
   // need only 37 flops for GSR since rest are always 0
 
   // and the align and rnd fields are in the ctl block
 
   // and the align and rnd fields are in the ctl block
 
 
 
`ifdef FPGA_SYN_1THREAD
 
 
 
   dffr_s #37 gsr0_reg(.din (t0_gsr_nxt[36:0]),
 
 
 
                                 .q   (t0_gsr[36:0]),
 
 
 
                     .rst(reset),
 
 
 
                                 .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
 
 
 
   assign     t0_gsr_nxt[36:0] = t0_gsr[36:0];
 
 
 
   assign     gsr_e[36:0] = t0_gsr[36:0];
 
 
 
 
 
 
 
`else
 
 
 
 
 
 
 
   dffr_s #37 gsr0_reg(.din (t0_gsr_nxt[36:0]),
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
   dffr #37 gsr0_reg(.din (t0_gsr_nxt[36:0]),
 
 
 
                                 .q   (t0_gsr[36:0]),
 
                                 .q   (t0_gsr[36:0]),
 
                     .rst(reset),
 
                     .rst(reset),
 
                                 .clk (clk), .se(se), .si(), .so());
 
                                 .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
 
   dffr #37 gsr1_reg(.din (t1_gsr_nxt[36:0]),
 
   dffr_s #37 gsr1_reg(.din (t1_gsr_nxt[36:0]),
 
                                 .q   (t1_gsr[36:0]),
 
                                 .q   (t1_gsr[36:0]),
 
                     .rst(reset),
 
                     .rst(reset),
 
                                 .clk (clk), .se(se), .si(), .so());
 
                                 .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
 
   dffr #37 gsr2_reg(.din (t2_gsr_nxt[36:0]),
 
   dffr_s #37 gsr2_reg(.din (t2_gsr_nxt[36:0]),
 
                                 .q   (t2_gsr[36:0]),
 
                                 .q   (t2_gsr[36:0]),
 
                     .rst(reset),
 
                     .rst(reset),
 
                                 .clk (clk), .se(se), .si(), .so());
 
                                 .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
 
   dffr #37 gsr3_reg(.din (t3_gsr_nxt[36:0]),
 
   dffr_s #37 gsr3_reg(.din (t3_gsr_nxt[36:0]),
 
                                 .q   (t3_gsr[36:0]),
 
                                 .q   (t3_gsr[36:0]),
 
                     .rst(reset),
 
                     .rst(reset),
 
                                 .clk (clk), .se(se), .si(), .so());
 
                                 .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
 
 
 
 
 
   dp_mux2es #(37) gsr0_mux(.dout(t0_gsr_nxt[36:0]),
 
   dp_mux2es #(37) gsr0_mux(.dout(t0_gsr_nxt[36:0]),
 
                            .in0(t0_gsr[36:0]),
 
                            .in0(t0_gsr[36:0]),
 
                            .in1(ctl_dp_wsr_data_w2[36:0]),
 
                            .in1(ctl_dp_wsr_data_w2[36:0]),
 
                            .sel(ctl_dp_gsr_wsr_w2[0]));
 
                            .sel(ctl_dp_gsr_wsr_w2[0]));
Line 1366... Line 533... 
                           .in3  (t3_gsr[36:0]),
 
                           .in3  (t3_gsr[36:0]),
 
                           .sel0 (ctl_dp_thr_e[0]),
 
                           .sel0 (ctl_dp_thr_e[0]),
 
                           .sel1 (ctl_dp_thr_e[1]),
 
                           .sel1 (ctl_dp_thr_e[1]),
 
                           .sel2 (ctl_dp_thr_e[2]),
 
                           .sel2 (ctl_dp_thr_e[2]),
 
                           .sel3 (ctl_dp_thr_e[3]));
 
                           .sel3 (ctl_dp_thr_e[3]));
 
 // !`ifdef FPGA_SYN_1THREAD
 
`endif // !`ifdef FPGA_SYN_1THREAD
 
 
 
 
 
   assign     dp_ctl_gsr_scale_e[4:0] = gsr_e[4:0];
 
   assign     dp_ctl_gsr_scale_e[4:0] = gsr_e[4:0];
 
   assign     dp_ctl_gsr_mask_e[31:0] = gsr_e[36:5];
 
   assign     dp_ctl_gsr_mask_e[31:0] = gsr_e[36:5];
 
 
 
 
 
 
 
 

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