OpenCores

Line 26...

*/

*/

////////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////////

// Global header file includes

// Global header file includes

////////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////////

/*

`include "sys.h"

/* ========== Copyright Header Begin ==========================================

`include "iop.h"

`include "ifu.h"

* OpenSPARC T1 Processor File: sys.h

`include "lsu.h"

* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.

* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.

* The above named program is free software; you can redistribute it and/or

* modify it under the terms of the GNU General Public

* License version 2 as published by the Free Software Foundation.

* The above named program is distributed in the hope that it will be

* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of

* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

* General Public License for more details.

* You should have received a copy of the GNU General Public

* License along with this work; if not, write to the Free Software

* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.

* ========== Copyright Header End ============================================

*/

// -*- verilog -*-

////////////////////////////////////////////////////////////////////////

/*

//

// Description:         Global header file that contain definitions that

//                      are common/shared at the systme level

*/

////////////////////////////////////////////////////////////////////////

//

// Setting the time scale

// If the timescale changes, JP_TIMESCALE may also have to change.

`timescale      1ps/1ps

//

// JBUS clock

// =========

//

// Afara Link Defines

// ==================

// Reliable Link

// Afara Link Objects

// Afara Link Object Format - Reliable Link

// Afara Link Object Format - Congestion

// Afara Link Object Format - Acknowledge

// Afara Link Object Format - Request

// Afara Link Object Format - Message

// Acknowledge Types

// Request Types

// Afara Link Frame

//

// UCB Packet Type

// ===============

//

//

// UCB Data Packet Format

// ======================

//

// Size encoding for the UCB_SIZE_HI/LO field

// 000 - byte

// 001 - half-word

// 010 - word

// 011 - double-word

// 111 - quad-word

//

// UCB Interrupt Packet Format

// ===========================

//

//`define UCB_THR_HI             9      // (6) cpu/thread ID shared with

//`define UCB_THR_LO             4             data packet format

//`define UCB_PKT_HI             3      // (4) packet type shared with

//`define UCB_PKT_LO             0      //     data packet format

//

// FCRAM Bus Widths

// ================

//

//

// ENET clock periods

// ==================

//

//

// JBus Bridge defines

// =================

//

//

// PCI Device Address Configuration

// ================================

//

/*

/* ========== Copyright Header Begin ==========================================

* OpenSPARC T1 Processor File: iop.h

* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.

* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.

* The above named program is free software; you can redistribute it and/or

* modify it under the terms of the GNU General Public

* License version 2 as published by the Free Software Foundation.

* The above named program is distributed in the hope that it will be

* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of

* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

* General Public License for more details.

* You should have received a copy of the GNU General Public

* License along with this work; if not, write to the Free Software

* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.

* ========== Copyright Header End ============================================

*/

//-*- verilog -*-

////////////////////////////////////////////////////////////////////////

/*

//

//  Description:        Global header file that contain definitions that

//                      are common/shared at the IOP chip level

*/

////////////////////////////////////////////////////////////////////////

// Address Map Defines

// ===================

// CMP space

// IOP space

                               //`define ENET_ING_CSR     8'h84

                               //`define ENET_EGR_CMD_CSR 8'h85

// L2 space

// More IOP space

//Cache Crossbar Width and Field Defines

//======================================

//bits 133:128 are shared by different fields

//for different packet types.

//End cache crossbar defines

// Number of COS supported by EECU

//

// BSC bus sizes

// =============

//

// General

// CTags

// reinstated temporarily

// CoS

// L2$ Bank

// L2$ Req

// L2$ Ack

// Enet Egress Command Unit

// Enet Egress Packet Unit

// This is cleaved in between Egress Datapath Ack's

// Enet Egress Datapath

// In-Order / Ordered Queue: EEPU

// Tag is: TLEN, SOF, EOF, QID = 15

// Nack + Tag Info + CTag

// ENET Ingress Queue Management Req

// ENET Ingress Queue Management Ack

// Enet Ingress Packet Unit

// ENET Ingress Packet Unit Ack

// In-Order / Ordered Queue: PCI

// Tag is: CTAG

// PCI-X Request

// PCI_X Acknowledge

//

// BSC array sizes

//================

//

// ECC syndrome bits per memory element

//

// BSC Port Definitions

// ====================

//

// Bits 7 to 4 of curr_port_id

// Number of ports of each type

// Bits needed to represent above

// How wide the linked list pointers are

// 60b for no payload (2CoS)

// 80b for payload (2CoS)

//`define BSC_OBJ_PTR   80

//`define BSC_HD1_HI    69

//`define BSC_HD1_LO    60

//`define BSC_TL1_HI    59

//`define BSC_TL1_LO    50

//`define BSC_CT1_HI    49

//`define BSC_CT1_LO    40

//`define BSC_HD0_HI    29

//`define BSC_HD0_LO    20

//`define BSC_TL0_HI    19

//`define BSC_TL0_LO    10

//`define BSC_CT0_HI     9

//`define BSC_CT0_LO     0

// I2C STATES in DRAMctl

//

// IOB defines

// ===========

//

//`define IOB_INT_STAT_WIDTH   32

//`define IOB_INT_STAT_HI      31

//`define IOB_INT_STAT_LO       0

// fixme - double check address mapping

// CREG in `IOB_INT_CSR space

// CREG in `IOB_MAN_CSR space

// Address map for TAP access of SPARC ASI

//

// CIOP UCB Bus Width

// ==================

//

//`define IOB_EECU_WIDTH       16  // ethernet egress command

//`define EECU_IOB_WIDTH       16

//`define IOB_NRAM_WIDTH       16  // NRAM (RLDRAM previously)

//`define NRAM_IOB_WIDTH        4

//`define IOB_ENET_ING_WIDTH   32  // ethernet ingress

//`define ENET_ING_IOB_WIDTH    8

//`define IOB_ENET_EGR_WIDTH    4  // ethernet egress

//`define ENET_EGR_IOB_WIDTH    4

//`define IOB_ENET_MAC_WIDTH    4  // ethernet MAC

//`define ENET_MAC_IOB_WIDTH    4

//`define IOB_BSC_WIDTH         4  // BSC

//`define BSC_IOB_WIDTH         4

//`define IOB_CLSP_WIDTH        4  // clk spine unit

//`define CLSP_IOB_WIDTH        4

//

// CIOP UCB Buf ID Type

// ====================

//

//

// Interrupt Device ID

// ===================

//

// Caution: DUMMY_DEV_ID has to be 9 bit wide

//          for fields to line up properly in the IOB.

//

// Soft Error related definitions

// ==============================

//

//

// CMP clock

// =========

//

//

// NRAM/IO Interface

// =================

//

//

// NRAM/ENET Interface

// ===================

//

//

// IO/FCRAM Interface

// ==================

//

//

// PCI Interface

// ==================

// Load/store size encodings

// -------------------------

// Size encoding

// 000 - byte

// 001 - half-word

// 010 - word

// 011 - double-word

// 100 - quad

//

// JBI<->SCTAG Interface

// =======================

// Outbound Header Format

// Inbound Header Format

//

// JBI->IOB Mondo Header Format

// ============================

//

// JBI->IOB Mondo Bus Width/Cycle

// ==============================

// Cycle  1 Header[15:8]

// Cycle  2 Header[ 7:0]

// Cycle  3 J_AD[127:120]

// Cycle  4 J_AD[119:112]

// .....

// Cycle 18 J_AD[  7:  0]

/*

/* ========== Copyright Header Begin ==========================================

* OpenSPARC T1 Processor File: ifu.h

* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.

* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.

* The above named program is free software; you can redistribute it and/or

* modify it under the terms of the GNU General Public

* License version 2 as published by the Free Software Foundation.

* The above named program is distributed in the hope that it will be

* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of

* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

* General Public License for more details.

* You should have received a copy of the GNU General Public

* License along with this work; if not, write to the Free Software

* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.

* ========== Copyright Header End ============================================

*/

////////////////////////////////////////////////////////////////////////

/*

//

//  Module Name: ifu.h

//  Description:

//  All ifu defines

*/

//--------------------------------------------

// Icache Values in IFU::ICD/ICV/ICT/FDP/IFQDP

//--------------------------------------------

// Set Values

// IC_IDX_HI = log(icache_size/4ways) - 1

// !!IMPORTANT!! a change to IC_LINE_SZ will mean a change to the code as

//   well.  Unfortunately this has not been properly parametrized.

//   Changing the IC_LINE_SZ param alone is *not* enough.

// !!IMPORTANT!! a change to IC_TAG_HI will mean a change to the code as

//   well.  Changing the IC_TAG_HI param alone is *not* enough to

//   change the PA range.

// highest bit of PA

// Derived Values

// 4095

// number of entries - 1 = 511

// 12

// 28

// 7

// tags for all 4 ways + parity

// 116

// 115

//----------------------------------------------------------------------

// For thread scheduler in IFU::DTU::SWL

//----------------------------------------------------------------------

// thread states:  (thr_state[4:0])

// thread configuration register bit fields

//----------------------------------------------------------------------

// For MIL fsm in IFU::IFQ

//----------------------------------------------------------------------

//---------------------------------------------------

// Interrupt Block

//---------------------------------------------------

//-------------------------------------

// IFQ

//-------------------------------------

// valid bit plus ifill

//`ifdef SPARC_L2_64B

//`else

//`define BANK_ID_HI 8

//`define BANK_ID_LO 7

//`endif

//`define CPX_INV_PA_HI  116

//`define CPX_INV_PA_LO  112

//----------------------------------------

// IFU Traps

//----------------------------------------

// precise

// disrupting

/*

/* ========== Copyright Header Begin ==========================================

* OpenSPARC T1 Processor File: lsu.h

* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.

* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.

* The above named program is free software; you can redistribute it and/or

* modify it under the terms of the GNU General Public

* License version 2 as published by the Free Software Foundation.

* The above named program is distributed in the hope that it will be

* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of

* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

* General Public License for more details.

* You should have received a copy of the GNU General Public

* License along with this work; if not, write to the Free Software

* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.

* ========== Copyright Header End ============================================

*/

//`define STB_PCX_WY_HI   107

//`define STB_PCX_WY_LO   106

// TLB Tag and Data Format

// I-TLB version - lsu_tlb only.

// Invalidate Format

//addr<5:4>=00

//addr<5:4>=01

//addr<5:4>=10

//addr<5:4>=11

// cpuid - 4b

// CPUany, addr<5:4>=00,10

// CPUany, addr<5:4>=01,11

// CPUany, addr<5:4>=01,11

// DTAG parity error Invalidate

// CPX BINIT STORE

////////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////////

// Local header file includes / local defines

// Local header file includes / local defines

////////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////////

Line 1716...

Line 121...

   lsu_ifu_direct_map_l1, lsu_ifu_dcache_tag_perror,

   lsu_ifu_direct_map_l1, lsu_ifu_dcache_tag_perror,

   lsu_ifu_dcache_data_perror, lsu_ifu_dc_parity_error_w2,

   lsu_ifu_dcache_data_perror, lsu_ifu_dc_parity_error_w2,

   lsu_ifu_cpxpkt_i1, lsu_ifu_asi_vld, lsu_ifu_asi_thrid,

   lsu_ifu_cpxpkt_i1, lsu_ifu_asi_vld, lsu_ifu_asi_thrid,

   lsu_ifu_asi_state, lsu_ifu_asi_load, lsu_ifu_asi_addr,

   lsu_ifu_asi_state, lsu_ifu_asi_load, lsu_ifu_asi_addr,

   lsu_ifu_addr_real_l, grst_l, gdbginit_l, ffu_ifu_tid_w2,

   lsu_ifu_addr_real_l, grst_l, gdbginit_l, ffu_ifu_tid_w2,

   ffu_ifu_stallreq,wbm_spc_stall,wbm_spc_resume, ffu_ifu_inj_ack, ffu_ifu_fst_ce_w,

   ffu_ifu_stallreq, ffu_ifu_inj_ack, ffu_ifu_fst_ce_w,

   ffu_ifu_fpop_done_w2, ffu_ifu_err_synd_w2, ffu_ifu_err_reg_w2,

   ffu_ifu_fpop_done_w2, ffu_ifu_err_synd_w2, ffu_ifu_err_reg_w2,

   ffu_ifu_ecc_ue_w2, ffu_ifu_ecc_ce_w2, ffu_ifu_cc_w2,

   ffu_ifu_ecc_ue_w2, ffu_ifu_ecc_ce_w2, ffu_ifu_cc_w2,

   ffu_ifu_cc_vld_w2, exu_ifu_va_oor_m, exu_ifu_spill_e,

   ffu_ifu_cc_vld_w2, exu_ifu_va_oor_m, exu_ifu_spill_e,

   exu_ifu_regz_e, exu_ifu_regn_e, exu_ifu_oddwin_s,

   exu_ifu_regz_e, exu_ifu_regn_e, exu_ifu_oddwin_s,

   exu_ifu_longop_done_g, exu_ifu_inj_ack, exu_ifu_err_synd_m,

   exu_ifu_longop_done_g, exu_ifu_inj_ack, exu_ifu_err_synd_m,

Line 1806...

Line 211...

   input [5:0]          ffu_ifu_err_reg_w2;     // To errdp of sparc_ifu_errdp.v

   input [5:0]          ffu_ifu_err_reg_w2;     // To errdp of sparc_ifu_errdp.v

   input [13:0]         ffu_ifu_err_synd_w2;    // To errdp of sparc_ifu_errdp.v

   input [13:0]         ffu_ifu_err_synd_w2;    // To errdp of sparc_ifu_errdp.v

   input                ffu_ifu_fpop_done_w2;   // To swl of sparc_ifu_swl.v

   input                ffu_ifu_fpop_done_w2;   // To swl of sparc_ifu_swl.v

   input                ffu_ifu_fst_ce_w;       // To swl of sparc_ifu_swl.v, ...

   input                ffu_ifu_fst_ce_w;       // To swl of sparc_ifu_swl.v, ...

   input                ffu_ifu_inj_ack;        // To errctl of sparc_ifu_errctl.v

   input                ffu_ifu_inj_ack;        // To errctl of sparc_ifu_errctl.v

   input                ffu_ifu_stallreq;input wbm_spc_stall;input wbm_spc_resume;       // To fcl of sparc_ifu_fcl.v

   input                ffu_ifu_stallreq;       // To fcl of sparc_ifu_fcl.v

   input [1:0]          ffu_ifu_tid_w2;         // To swl of sparc_ifu_swl.v, ...

   input [1:0]          ffu_ifu_tid_w2;         // To swl of sparc_ifu_swl.v, ...

   input                gdbginit_l;             // To swl of sparc_ifu_swl.v, ...

   input                gdbginit_l;             // To swl of sparc_ifu_swl.v, ...

   input                grst_l;                 // To swl of sparc_ifu_swl.v, ...

   input                grst_l;                 // To swl of sparc_ifu_swl.v, ...

   input [3:0]          lsu_ifu_addr_real_l;    // To fcl of sparc_ifu_fcl.v

   input [3:0]          lsu_ifu_addr_real_l;    // To fcl of sparc_ifu_fcl.v

   input [17:0]         lsu_ifu_asi_addr;       // To ifqdp of sparc_ifu_ifqdp.v

   input [17:0]         lsu_ifu_asi_addr;       // To ifqdp of sparc_ifu_ifqdp.v

   input                lsu_ifu_asi_load;       // To ifqctl of sparc_ifu_ifqctl.v

   input                lsu_ifu_asi_load;       // To ifqctl of sparc_ifu_ifqctl.v

   input [7:0]          lsu_ifu_asi_state;      // To ifqctl of sparc_ifu_ifqctl.v

   input [7:0]          lsu_ifu_asi_state;      // To ifqctl of sparc_ifu_ifqctl.v

   input [1:0]          lsu_ifu_asi_thrid;      // To ifqctl of sparc_ifu_ifqctl.v

   input [1:0]          lsu_ifu_asi_thrid;      // To ifqctl of sparc_ifu_ifqctl.v

   input                lsu_ifu_asi_vld;        // To ifqctl of sparc_ifu_ifqctl.v

   input                lsu_ifu_asi_vld;        // To ifqctl of sparc_ifu_ifqctl.v

   input [145-1:0]lsu_ifu_cpxpkt_i1;     // To ifqdp of sparc_ifu_ifqdp.v

   input [`CPX_WIDTH-1:0]lsu_ifu_cpxpkt_i1;     // To ifqdp of sparc_ifu_ifqdp.v

   input                lsu_ifu_dc_parity_error_w2;// To swl of sparc_ifu_swl.v, ...

   input                lsu_ifu_dc_parity_error_w2;// To swl of sparc_ifu_swl.v, ...

   input                lsu_ifu_dcache_data_perror;// To errctl of sparc_ifu_errctl.v

   input                lsu_ifu_dcache_data_perror;// To errctl of sparc_ifu_errctl.v

   input                lsu_ifu_dcache_tag_perror;// To errctl of sparc_ifu_errctl.v

   input                lsu_ifu_dcache_tag_perror;// To errctl of sparc_ifu_errctl.v

   input                lsu_ifu_direct_map_l1;  // To ifqctl of sparc_ifu_ifqctl.v

   input                lsu_ifu_direct_map_l1;  // To ifqctl of sparc_ifu_ifqctl.v

   input                lsu_ifu_dtlb_data_su;   // To errctl of sparc_ifu_errctl.v

   input                lsu_ifu_dtlb_data_su;   // To errctl of sparc_ifu_errctl.v

Line 1831...

Line 236...

   input [3:0]          lsu_ifu_icache_en;      // To fcl of sparc_ifu_fcl.v

   input [3:0]          lsu_ifu_icache_en;      // To fcl of sparc_ifu_fcl.v

   input [3:0]          lsu_ifu_inj_ack;        // To errctl of sparc_ifu_errctl.v

   input [3:0]          lsu_ifu_inj_ack;        // To errctl of sparc_ifu_errctl.v

   input                lsu_ifu_io_error;       // To errctl of sparc_ifu_errctl.v

   input                lsu_ifu_io_error;       // To errctl of sparc_ifu_errctl.v

   input                lsu_ifu_l2_corr_error;  // To errctl of sparc_ifu_errctl.v

   input                lsu_ifu_l2_corr_error;  // To errctl of sparc_ifu_errctl.v

   input                lsu_ifu_l2_unc_error;   // To errctl of sparc_ifu_errctl.v

   input                lsu_ifu_l2_unc_error;   // To errctl of sparc_ifu_errctl.v

   input [11:5] lsu_ifu_ld_icache_index;// To invctl of sparc_ifu_invctl.v

   input [`IC_IDX_HI:5] lsu_ifu_ld_icache_index;// To invctl of sparc_ifu_invctl.v

   input [1:0]          lsu_ifu_ld_pcxpkt_tid;  // To invctl of sparc_ifu_invctl.v

   input [1:0]          lsu_ifu_ld_pcxpkt_tid;  // To invctl of sparc_ifu_invctl.v

   input                lsu_ifu_ld_pcxpkt_vld;  // To invctl of sparc_ifu_invctl.v

   input                lsu_ifu_ld_pcxpkt_vld;  // To invctl of sparc_ifu_invctl.v

   input [3:0]          lsu_ifu_ldst_cmplt;     // To swl of sparc_ifu_swl.v

   input [3:0]          lsu_ifu_ldst_cmplt;     // To swl of sparc_ifu_swl.v

   input                lsu_ifu_ldst_miss_g;    // To swl of sparc_ifu_swl.v

   input                lsu_ifu_ldst_miss_g;    // To swl of sparc_ifu_swl.v

   input                lsu_ifu_ldsta_internal_e;// To dec of sparc_ifu_dec.v, ...

   input                lsu_ifu_ldsta_internal_e;// To dec of sparc_ifu_dec.v, ...

Line 2296...

Line 701...

   wire                 ifd_ifc_asi_vachklo_i2; // From ifqdp of sparc_ifu_ifqdp.v

   wire                 ifd_ifc_asi_vachklo_i2; // From ifqdp of sparc_ifu_ifqdp.v

   wire [3:2]           ifd_ifc_asiaddr_i2;     // From ifqdp of sparc_ifu_ifqdp.v

   wire [3:2]           ifd_ifc_asiaddr_i2;     // From ifqdp of sparc_ifu_ifqdp.v

   wire                 ifd_ifc_cpxce_i2;       // From ifqdp of sparc_ifu_ifqdp.v

   wire                 ifd_ifc_cpxce_i2;       // From ifqdp of sparc_ifu_ifqdp.v

   wire                 ifd_ifc_cpxms_i2;       // From ifqdp of sparc_ifu_ifqdp.v

   wire                 ifd_ifc_cpxms_i2;       // From ifqdp of sparc_ifu_ifqdp.v

   wire                 ifd_ifc_cpxnc_i2;       // From ifqdp of sparc_ifu_ifqdp.v

   wire                 ifd_ifc_cpxnc_i2;       // From ifqdp of sparc_ifu_ifqdp.v

   wire [(143 - 140 + 1):0]ifd_ifc_cpxreq_i1;      // From ifqdp of sparc_ifu_ifqdp.v

   wire [`CPX_RQ_SIZE:0]ifd_ifc_cpxreq_i1;      // From ifqdp of sparc_ifu_ifqdp.v

   wire [3:0]           ifd_ifc_cpxreq_nxt;     // From ifqdp of sparc_ifu_ifqdp.v

   wire [3:0]           ifd_ifc_cpxreq_nxt;     // From ifqdp of sparc_ifu_ifqdp.v

   wire [1:0]           ifd_ifc_cpxthr_nxt;     // From ifqdp of sparc_ifu_ifqdp.v

   wire [1:0]           ifd_ifc_cpxthr_nxt;     // From ifqdp of sparc_ifu_ifqdp.v

   wire                 ifd_ifc_cpxue_i2;       // From ifqdp of sparc_ifu_ifqdp.v

   wire                 ifd_ifc_cpxue_i2;       // From ifqdp of sparc_ifu_ifqdp.v

   wire                 ifd_ifc_cpxvld_i2;      // From ifqdp of sparc_ifu_ifqdp.v

   wire                 ifd_ifc_cpxvld_i2;      // From ifqdp of sparc_ifu_ifqdp.v

   wire [2:0]           ifd_ifc_destid0;        // From ifqdp of sparc_ifu_ifqdp.v

   wire [2:0]           ifd_ifc_destid0;        // From ifqdp of sparc_ifu_ifqdp.v

Line 2315...

Line 720...

   wire                 ifd_ifc_iobpkt_i2;      // From ifqdp of sparc_ifu_ifqdp.v

   wire                 ifd_ifc_iobpkt_i2;      // From ifqdp of sparc_ifu_ifqdp.v

   wire [3:0]           ifd_ifc_miladdr4_i2;    // From ifqdp of sparc_ifu_ifqdp.v

   wire [3:0]           ifd_ifc_miladdr4_i2;    // From ifqdp of sparc_ifu_ifqdp.v

   wire [3:0]           ifd_ifc_milhit_s;       // From ifqdp of sparc_ifu_ifqdp.v

   wire [3:0]           ifd_ifc_milhit_s;       // From ifqdp of sparc_ifu_ifqdp.v

   wire [2:0]           ifd_ifc_newdestid_s;    // From ifqdp of sparc_ifu_ifqdp.v

   wire [2:0]           ifd_ifc_newdestid_s;    // From ifqdp of sparc_ifu_ifqdp.v

   wire [4:2]           ifd_ifc_pcxline_d;      // From ifqdp of sparc_ifu_ifqdp.v

   wire [4:2]           ifd_ifc_pcxline_d;      // From ifqdp of sparc_ifu_ifqdp.v

   wire [145-1:0]ifd_inv_ifqop_i2;       // From ifqdp of sparc_ifu_ifqdp.v

   wire [`CPX_WIDTH-1:0]ifd_inv_ifqop_i2;       // From ifqdp of sparc_ifu_ifqdp.v

   wire [1:0]           ifd_inv_wrway_i2;       // From ifqdp of sparc_ifu_ifqdp.v

   wire [1:0]           ifd_inv_wrway_i2;       // From ifqdp of sparc_ifu_ifqdp.v

   wire [3:0]           ifq_dtu_pred_rdy;       // From ifqctl of sparc_ifu_ifqctl.v

   wire [3:0]           ifq_dtu_pred_rdy;       // From ifqctl of sparc_ifu_ifqctl.v

   wire [3:0]           ifq_dtu_thrrdy;         // From ifqctl of sparc_ifu_ifqctl.v

   wire [3:0]           ifq_dtu_thrrdy;         // From ifqctl of sparc_ifu_ifqctl.v

   wire                 ifq_erb_asi_erraddr_i2; // From ifqctl of sparc_ifu_ifqctl.v

   wire                 ifq_erb_asi_erraddr_i2; // From ifqctl of sparc_ifu_ifqctl.v

   wire                 ifq_erb_asi_erren_i2;   // From ifqctl of sparc_ifu_ifqctl.v

   wire                 ifq_erb_asi_erren_i2;   // From ifqctl of sparc_ifu_ifqctl.v

Line 2336...

Line 741...

   wire                 ifq_erb_l2_ue;          // From ifqctl of sparc_ifu_ifqctl.v

   wire                 ifq_erb_l2_ue;          // From ifqctl of sparc_ifu_ifqctl.v

   wire [1:0]           ifq_erb_l2err_tid;      // From ifqctl of sparc_ifu_ifqctl.v

   wire [1:0]           ifq_erb_l2err_tid;      // From ifqctl of sparc_ifu_ifqctl.v

   wire                 ifq_erb_rdinst_f;       // From ifqctl of sparc_ifu_ifqctl.v

   wire                 ifq_erb_rdinst_f;       // From ifqctl of sparc_ifu_ifqctl.v

   wire                 ifq_erb_rdtag_f;        // From ifqctl of sparc_ifu_ifqctl.v

   wire                 ifq_erb_rdtag_f;        // From ifqctl of sparc_ifu_ifqctl.v

   wire                 ifq_erb_ue_rep;         // From ifqctl of sparc_ifu_ifqctl.v

   wire                 ifq_erb_ue_rep;         // From ifqctl of sparc_ifu_ifqctl.v

   wire [11:4]  ifq_erb_wrindex_f;      // From ifqdp of sparc_ifu_ifqdp.v

   wire [`IC_IDX_HI:4]  ifq_erb_wrindex_f;      // From ifqdp of sparc_ifu_ifqdp.v

   wire [1:0]           ifq_fcl_asi_tid_bf;     // From ifqctl of sparc_ifu_ifqctl.v

   wire [1:0]           ifq_fcl_asi_tid_bf;     // From ifqctl of sparc_ifu_ifqctl.v

   wire                 ifq_fcl_asird_bf;       // From ifqctl of sparc_ifu_ifqctl.v

   wire                 ifq_fcl_asird_bf;       // From ifqctl of sparc_ifu_ifqctl.v

   wire [3:0]           ifq_fcl_fill_thr;       // From ifqctl of sparc_ifu_ifqctl.v

   wire [3:0]           ifq_fcl_fill_thr;       // From ifqctl of sparc_ifu_ifqctl.v

   wire                 ifq_fcl_flush_sonly_e;  // From ifqctl of sparc_ifu_ifqctl.v

   wire                 ifq_fcl_flush_sonly_e;  // From ifqctl of sparc_ifu_ifqctl.v

   wire                 ifq_fcl_icd_wrreq_bf;   // From ifqctl of sparc_ifu_ifqctl.v

   wire                 ifq_fcl_icd_wrreq_bf;   // From ifqctl of sparc_ifu_ifqctl.v

Line 2351...

Line 756...

   wire                 ifq_fcl_wrreq_bf;       // From ifqctl of sparc_ifu_ifqctl.v

   wire                 ifq_fcl_wrreq_bf;       // From ifqctl of sparc_ifu_ifqctl.v

   wire [32:0]          ifq_fdp_fill_inst;      // From ifqdp of sparc_ifu_ifqdp.v

   wire [32:0]          ifq_fdp_fill_inst;      // From ifqdp of sparc_ifu_ifqdp.v

   wire                 ifq_icd_data_sel_bist_i2;// From ifqctl of sparc_ifu_ifqctl.v

   wire                 ifq_icd_data_sel_bist_i2;// From ifqctl of sparc_ifu_ifqctl.v

   wire                 ifq_icd_data_sel_fill_i2;// From ifqctl of sparc_ifu_ifqctl.v

   wire                 ifq_icd_data_sel_fill_i2;// From ifqctl of sparc_ifu_ifqctl.v

   wire                 ifq_icd_data_sel_old_i2;// From ifqctl of sparc_ifu_ifqctl.v

   wire                 ifq_icd_data_sel_old_i2;// From ifqctl of sparc_ifu_ifqctl.v

   wire [11:2]  ifq_icd_index_bf;       // From ifqdp of sparc_ifu_ifqdp.v

   wire [`IC_IDX_HI:2]  ifq_icd_index_bf;       // From ifqdp of sparc_ifu_ifqdp.v

   wire [3:0]           ifq_icd_worden_bf;      // From ifqctl of sparc_ifu_ifqctl.v

   wire [3:0]           ifq_icd_worden_bf;      // From ifqctl of sparc_ifu_ifqctl.v

   wire [135:0]         ifq_icd_wrdata_i2;      // From ifqdp of sparc_ifu_ifqdp.v

   wire [135:0]         ifq_icd_wrdata_i2;      // From ifqdp of sparc_ifu_ifqdp.v

   wire [1:0]           ifq_icd_wrway_bf;       // From ifqdp of sparc_ifu_ifqdp.v

   wire [1:0]           ifq_icd_wrway_bf;       // From ifqdp of sparc_ifu_ifqdp.v

   wire [3:0]           ifq_ict_dec_wrway_bf;   // From invctl of sparc_ifu_invctl.v

   wire [3:0]           ifq_ict_dec_wrway_bf;   // From invctl of sparc_ifu_invctl.v

   wire                 ifq_icv_wrdata_bf;      // From ifqctl of sparc_ifu_ifqctl.v

   wire                 ifq_icv_wrdata_bf;      // From ifqctl of sparc_ifu_ifqctl.v

   wire [15:0]          ifq_icv_wren_bf;        // From invctl of sparc_ifu_invctl.v

   wire [15:0]          ifq_icv_wren_bf;        // From invctl of sparc_ifu_invctl.v

   wire [11:5]  ifq_icv_wrindex_bf;     // From invctl of sparc_ifu_invctl.v

   wire [`IC_IDX_HI:5]  ifq_icv_wrindex_bf;     // From invctl of sparc_ifu_invctl.v

   wire                 ifq_swl_stallreq;       // From ifqctl of sparc_ifu_ifqctl.v

   wire                 ifq_swl_stallreq;       // From ifqctl of sparc_ifu_ifqctl.v

   wire                 imd_dcl_abit_d;         // From imd of sparc_ifu_imd.v

   wire                 imd_dcl_abit_d;         // From imd of sparc_ifu_imd.v

   wire [3:0]           imd_dcl_brcond_d;       // From imd of sparc_ifu_imd.v

   wire [3:0]           imd_dcl_brcond_d;       // From imd of sparc_ifu_imd.v

   wire [7:0]           imd_dcl_mvcond_d;       // From imd of sparc_ifu_imd.v

   wire [7:0]           imd_dcl_mvcond_d;       // From imd of sparc_ifu_imd.v

   wire                 inv_ifc_inv_pending;    // From invctl of sparc_ifu_invctl.v

   wire                 inv_ifc_inv_pending;    // From invctl of sparc_ifu_invctl.v

Line 2420...

Line 825...

   // rptr bus for bist read of icache

   // rptr bus for bist read of icache

   wire [67:0]      wsel_mbist_icache_data;

   wire [67:0]      wsel_mbist_icache_data;

   // bus width mismatch

   // bus width mismatch

   wire [(39 - 11):0] ifq_ict_wrtag_f;        // From ifqdp of sparc_ifu_ifqdp.v

   wire [`IC_TAG_SZ:0] ifq_ict_wrtag_f;        // From ifqdp of sparc_ifu_ifqdp.v

   // scan wires

   // scan wires

   wire                scan0_1;

   wire                scan0_1;

   wire                scan0_2;

   wire                scan0_2;

   wire                scan0_3;

   wire                scan0_3;

Line 2570...

Line 975...

                     .swl_dec_divbusy_e (swl_dec_divbusy_e),

                     .swl_dec_divbusy_e (swl_dec_divbusy_e),

                     .swl_dec_fp_enable_d(swl_dec_fp_enable_d));

                     .swl_dec_fp_enable_d(swl_dec_fp_enable_d));

   // Pipeline Control and Switch Logic

   // Pipeline Control and Switch Logic

   sparc_ifu_swl swl(.wbm_spc_stall(wbm_spc_stall),.wbm_spc_resume(wbm_spc_resume),

   sparc_ifu_swl swl(

                     .so                (scan0_2),

                     .so                (scan0_2),

                     .si                (scan0_1),

                     .si                (scan0_1),

                                 .thr_config_in_m       (exu_tlu_wsr_data_m[2:0]),

                                 .thr_config_in_m       (exu_tlu_wsr_data_m[2:0]),

                     .extra_longlat_compl(4'b0),

                     .extra_longlat_compl(4'b0),

Line 2860...

Line 1265...

                     // keep around in case we need it later

                     // keep around in case we need it later

                     .ifu_reset_l       (),

                     .ifu_reset_l       (),

                                 .fdp_fcl_va2_bf    (fdp_icd_vaddr_bf[2]),

                                 .fdp_fcl_va2_bf    (fdp_icd_vaddr_bf[2]),

                     .itlb_fcl_priv_s1  (itlb_rd_tte_data[4]),

                     .itlb_fcl_priv_s1  (itlb_rd_tte_data[`STLB_DATA_P]),

                     .tlu_fcl_dmp_pid_bf (tlu_itlb_tte_tag_w2[58:56]),

                     .tlu_fcl_dmp_pid_bf (tlu_itlb_tte_tag_w2[58:56]),

                     .tlu_fcl_dmp_real_bf (tlu_itlb_tte_tag_w2[55]),

                     .tlu_fcl_dmp_real_bf (tlu_itlb_tte_tag_w2[55]),

                     .itlb_fcl_cp_s1    (itlb_rd_tte_data[7]),

                     .itlb_fcl_cp_s1    (itlb_rd_tte_data[`STLB_DATA_CP]),

                     // need these here since itlb is not auto inst'ed

                     // need these here since itlb is not auto inst'ed

                                 .fcl_itlb_invall_f_l(fcl_itlb_invall_f_l),

                                 .fcl_itlb_invall_f_l(fcl_itlb_invall_f_l),

                     .fcl_itlb_cam_vld_bf(fcl_itlb_cam_vld_bf),

                     .fcl_itlb_cam_vld_bf(fcl_itlb_cam_vld_bf),

                     .fcl_itlb_cam_bypass_bf(fcl_itlb_cam_bypass_bf),

                     .fcl_itlb_cam_bypass_bf(fcl_itlb_cam_bypass_bf),

                     .fcl_itlb_addr_mask_l(fcl_itlb_addr_mask_l),

                     .fcl_itlb_addr_mask_l(fcl_itlb_addr_mask_l),

Line 3143...

Line 1548...

   bw_r_tlb itlb(

   bw_r_tlb itlb(

                              .tlb_pgnum_crit   (),

                              .tlb_pgnum_crit   (),

                              // Outputs

                              // Outputs

                              .tlb_rd_tte_tag    (itlb_rd_tte_tag[58:0]),  // 2

                              .tlb_rd_tte_tag    (itlb_rd_tte_tag[58:0]),  // 2

                              .tlb_rd_tte_data (itlb_rd_tte_data[42:0]), // 2

                              .tlb_rd_tte_data (itlb_rd_tte_data[42:0]), // 2

                              .tlb_pgnum             (itlb_ifq_paddr_s[39:10]), // 2

                              .tlb_pgnum             (itlb_ifq_paddr_s[`IC_TAG_HI:10]), // 2

                              .tlb_cam_hit         (itlb_fcl_tlbmiss_f_l),    // 1

                              .tlb_cam_hit         (itlb_fcl_tlbmiss_f_l),    // 1

                              .cache_way_hit   (itlb_wsel_waysel_s1[3:0]), // 2

                              .cache_way_hit   (itlb_wsel_waysel_s1[3:0]), // 2

                              .cache_hit       (itlb_fcl_imiss_s_l),      // 2

                              .cache_hit       (itlb_fcl_imiss_s_l),      // 2

                              .so               (short_scan0_1),

                              .so               (short_scan0_1),

Line 3206...

Line 1611...

                              .tlb_demap            (fcl_itlb_dmp_vld_bf),        // 0

                              .tlb_demap            (fcl_itlb_dmp_vld_bf),        // 0

                              .tlb_demap_all    (fcl_itlb_dmp_all_bf),        // 0

                              .tlb_demap_all    (fcl_itlb_dmp_all_bf),        // 0

                  .tlb_demap_auto (tlu_itlb_dmp_actxt_g),

                  .tlb_demap_auto (tlu_itlb_dmp_actxt_g),

                              .cache_ptag_w3    ({ict_itlb_tag3_f[27:0],   // 1

                              .cache_ptag_w3    ({ict_itlb_tag3_f[27:0],   // 1

                                                                  fdp_erb_pc_f[11:(11-1)]}),

                                                                  fdp_erb_pc_f[`IC_IDX_HI:(`IC_IDX_HI-1)]}),

                              .cache_ptag_w2    ({ict_itlb_tag2_f[27:0],    // 1

                              .cache_ptag_w2    ({ict_itlb_tag2_f[27:0],    // 1

                                                                  fdp_erb_pc_f[11:(11-1)]}),

                                                                  fdp_erb_pc_f[`IC_IDX_HI:(`IC_IDX_HI-1)]}),

                              .cache_ptag_w1    ({ict_itlb_tag1_f[27:0],    // 1

                              .cache_ptag_w1    ({ict_itlb_tag1_f[27:0],    // 1

                                    fdp_erb_pc_f[11:(11-1)]}),

                                    fdp_erb_pc_f[`IC_IDX_HI:(`IC_IDX_HI-1)]}),

                              .cache_ptag_w0    ({ict_itlb_tag0_f[27:0],     // 1

                              .cache_ptag_w0    ({ict_itlb_tag0_f[27:0],     // 1

                                    fdp_erb_pc_f[11:(11-1)]}),

                                    fdp_erb_pc_f[`IC_IDX_HI:(`IC_IDX_HI-1)]}),

                              .cache_set_vld    (icv_itlb_valid_f[3:0]),     // 1

                              .cache_set_vld    (icv_itlb_valid_f[3:0]),     // 1

                              .tlb_bypass           (fcl_itlb_cam_bypass_bf),    // 0

                              .tlb_bypass           (fcl_itlb_cam_bypass_bf),    // 0

                              .tlb_bypass_va    (fdp_icd_vaddr_bf[12:10]),   // 0

                              .tlb_bypass_va    (fdp_icd_vaddr_bf[12:10]),   // 0

Line 3286...

Line 1691...

                          .ary_fuse_repair_en(icd_fuse_repair_en[1:0])); // Templated

                          .ary_fuse_repair_en(icd_fuse_repair_en[1:0])); // Templated

//   sparc_ifu_icd icd

//   sparc_ifu_icd icd

   bw_r_icd icd(

   bw_r_icd icd(

                .so                     (scan0_8),

                .so                     (scan0_8),

                .si                     (scan0_7),

                .si                     (scan0_7),

                                   .fdp_icd_index_bf  (fdp_icd_vaddr_bf[11:2]),

                                   .fdp_icd_index_bf  (fdp_icd_vaddr_bf[`IC_IDX_HI:2]),

                 .ifq_icd_index_bf  ({ifq_icd_index_bf[11:2]}),

                 .ifq_icd_index_bf  ({ifq_icd_index_bf[`IC_IDX_HI:2]}),

                 .bist_ic_data      (mbist_icache_wdata[7:0]),

                 .bist_ic_data      (mbist_icache_wdata[7:0]),

                 .rst_tri_en        (mem_write_disable),

                 .rst_tri_en        (mem_write_disable),

                 .reset_l           (arst_l),

                 .reset_l           (arst_l),

                                   /*AUTOINST*/

                                   /*AUTOINST*/

                // Outputs

                // Outputs

Line 3347...

Line 1752...

                 // Inputs

                 // Inputs

                 .rclk                  (rclk),

                 .rclk                  (rclk),

                 .se                    (se),

                 .se                    (se),

                 .reset_l               (arst_l),                // Templated

                 .reset_l               (arst_l),                // Templated

                 .sehold                (sehold),

                 .sehold                (sehold),

                 .index0_x              (fdp_icd_vaddr_bf[11:5]), // Templated

                 .index0_x              (fdp_icd_vaddr_bf[`IC_IDX_HI:5]), // Templated

                 .index1_x              (ifq_icd_index_bf[11:5]), // Templated

                 .index1_x              (ifq_icd_index_bf[`IC_IDX_HI:5]), // Templated

                 .index_sel_x           (fcl_icd_index_sel_ifq_bf), // Templated

                 .index_sel_x           (fcl_icd_index_sel_ifq_bf), // Templated

                 .dec_wrway_x           (ifq_ict_dec_wrway_bf[3:0]), // Templated

                 .dec_wrway_x           (ifq_ict_dec_wrway_bf[3:0]), // Templated

                 .rdreq_x               (fcl_icd_rdreq_bf),      // Templated

                 .rdreq_x               (fcl_icd_rdreq_bf),      // Templated

                 .wrreq_x               (fcl_ict_wrreq_bf),      // Templated

                 .wrreq_x               (fcl_ict_wrreq_bf),      // Templated

                 .wrtag_w0_y            ({4'b0, ifq_ict_wrtag_f[(39 - 11):0]}), // Templated

                 .wrtag_w0_y            ({4'b0, ifq_ict_wrtag_f[`IC_TAG_SZ:0]}), // Templated

                 .wrtag_w1_y            ({4'b0, ifq_ict_wrtag_f[(39 - 11):0]}), // Templated

                 .wrtag_w1_y            ({4'b0, ifq_ict_wrtag_f[`IC_TAG_SZ:0]}), // Templated

                 .wrtag_w2_y            ({4'b0, ifq_ict_wrtag_f[(39 - 11):0]}), // Templated

                 .wrtag_w2_y            ({4'b0, ifq_ict_wrtag_f[`IC_TAG_SZ:0]}), // Templated

                 .wrtag_w3_y            ({4'b0, ifq_ict_wrtag_f[(39 - 11):0]}), // Templated

                 .wrtag_w3_y            ({4'b0, ifq_ict_wrtag_f[`IC_TAG_SZ:0]}), // Templated

                 .adj                   (lsu_ictag_mrgn[3:0]));   // Templated

                 .adj                   (lsu_ictag_mrgn[3:0]));   // Templated

//     sparc_ifu_icv icv

//     sparc_ifu_icv icv

/*   bw_r_rf16x32 AUTO_TEMPLATE(

/*   bw_r_rf16x32 AUTO_TEMPLATE(

                    // Outputs

                    // Outputs

                    .dout          (icv_itlb_valid_f[3:0]),

                    .dout          (icv_itlb_valid_f[3:0]),

Line 3390...

Line 1795...

                     .se                (se),                    // Templated

                     .se                (se),                    // Templated

                     .si                (short_scan0_2),         // Templated

                     .si                (short_scan0_2),         // Templated

                     .reset_l           (arst_l),                // Templated

                     .reset_l           (arst_l),                // Templated

                     .sehold            (sehold),                // Templated

                     .sehold            (sehold),                // Templated

                     .rst_tri_en        (mem_write_disable),     // Templated

                     .rst_tri_en        (mem_write_disable),     // Templated

                     .rd_adr1           (ifq_icv_wrindex_bf[11:5]), // Templated

                     .rd_adr1           (ifq_icv_wrindex_bf[`IC_IDX_HI:5]), // Templated

                     .rd_adr2           (fdp_icv_index_bf[11:5]), // Templated

                     .rd_adr2           (fdp_icv_index_bf[11:5]), // Templated

                     .rd_adr1_sel       (fcl_ifq_grant_bf),      // Templated

                     .rd_adr1_sel       (fcl_ifq_grant_bf),      // Templated

                     .rd_en             (fcl_icv_rdreq_bf),      // Templated

                     .rd_en             (fcl_icv_rdreq_bf),      // Templated

                     .wr_adr            (ifq_icv_wrindex_bf[11:7]), // Templated

                     .wr_adr            (ifq_icv_wrindex_bf[`IC_IDX_HI:7]), // Templated

                     .wr_en             (fcl_icv_wrreq_bf),      // Templated

                     .wr_en             (fcl_icv_wrreq_bf),      // Templated

                     .bit_wen           (ifq_icv_wren_bf[15:0]), // Templated

                     .bit_wen           (ifq_icv_wren_bf[15:0]), // Templated

                     .din               (ifq_icv_wrdata_bf));     // Templated

                     .din               (ifq_icv_wrdata_bf));     // Templated

   sparc_ifu_ifqdp ifqdp(

   sparc_ifu_ifqdp ifqdp(

                         .so            (short_so1),

                         .so            (short_so1),

                         .si            (short_scan1_1),

                         .si            (short_scan1_1),

                        .ifq_ict_wrtag_f(ifq_ict_wrtag_f[(39 - 11):0]),

                        .ifq_ict_wrtag_f(ifq_ict_wrtag_f[`IC_TAG_SZ:0]),

                         .fdp_ifq_paddr_f(fdp_erb_pc_f[9:2]),

                         .fdp_ifq_paddr_f(fdp_erb_pc_f[9:2]),

                         /*AUTOINST*/

                         /*AUTOINST*/

                         // Outputs

                         // Outputs

                         .ifu_lsu_pcxpkt_e(ifu_lsu_pcxpkt_e[51:0]),

                         .ifu_lsu_pcxpkt_e(ifu_lsu_pcxpkt_e[51:0]),

                         .ifq_fdp_fill_inst(ifq_fdp_fill_inst[32:0]),

                         .ifq_fdp_fill_inst(ifq_fdp_fill_inst[32:0]),

                         .ifq_erb_asidata_i2(ifq_erb_asidata_i2[47:0]),

                         .ifq_erb_asidata_i2(ifq_erb_asidata_i2[47:0]),

                         .ifd_inv_ifqop_i2(ifd_inv_ifqop_i2[145-1:0]),

                         .ifd_inv_ifqop_i2(ifd_inv_ifqop_i2[`CPX_WIDTH-1:0]),

                         .ifq_icd_index_bf(ifq_icd_index_bf[11:2]),

                         .ifq_icd_index_bf(ifq_icd_index_bf[`IC_IDX_HI:2]),

                         .ifq_icd_wrdata_i2(ifq_icd_wrdata_i2[135:0]),

                         .ifq_icd_wrdata_i2(ifq_icd_wrdata_i2[135:0]),

                         .ifq_erb_wrindex_f(ifq_erb_wrindex_f[11:4]),

                         .ifq_erb_wrindex_f(ifq_erb_wrindex_f[`IC_IDX_HI:4]),

                         .ifq_icd_wrway_bf(ifq_icd_wrway_bf[1:0]),

                         .ifq_icd_wrway_bf(ifq_icd_wrway_bf[1:0]),

                         .ifd_ifc_milhit_s(ifd_ifc_milhit_s[3:0]),

                         .ifd_ifc_milhit_s(ifd_ifc_milhit_s[3:0]),

                         .ifd_ifc_instoffset0(ifd_ifc_instoffset0[1:0]),

                         .ifd_ifc_instoffset0(ifd_ifc_instoffset0[1:0]),

                         .ifd_ifc_instoffset1(ifd_ifc_instoffset1[1:0]),

                         .ifd_ifc_instoffset1(ifd_ifc_instoffset1[1:0]),

                         .ifd_ifc_instoffset2(ifd_ifc_instoffset2[1:0]),

                         .ifd_ifc_instoffset2(ifd_ifc_instoffset2[1:0]),

                         .ifd_ifc_instoffset3(ifd_ifc_instoffset3[1:0]),

                         .ifd_ifc_instoffset3(ifd_ifc_instoffset3[1:0]),

                         .ifd_ifc_cpxthr_nxt(ifd_ifc_cpxthr_nxt[1:0]),

                         .ifd_ifc_cpxthr_nxt(ifd_ifc_cpxthr_nxt[1:0]),

                         .ifd_ifc_cpxreq_nxt(ifd_ifc_cpxreq_nxt[3:0]),

                         .ifd_ifc_cpxreq_nxt(ifd_ifc_cpxreq_nxt[3:0]),

                         .ifd_ifc_cpxreq_i1(ifd_ifc_cpxreq_i1[(143 - 140 + 1):0]),

                         .ifd_ifc_cpxreq_i1(ifd_ifc_cpxreq_i1[`CPX_RQ_SIZE:0]),

                         .ifd_ifc_destid0(ifd_ifc_destid0[2:0]),

                         .ifd_ifc_destid0(ifd_ifc_destid0[2:0]),

                         .ifd_ifc_destid1(ifd_ifc_destid1[2:0]),

                         .ifd_ifc_destid1(ifd_ifc_destid1[2:0]),

                         .ifd_ifc_destid2(ifd_ifc_destid2[2:0]),

                         .ifd_ifc_destid2(ifd_ifc_destid2[2:0]),

                         .ifd_ifc_destid3(ifd_ifc_destid3[2:0]),

                         .ifd_ifc_destid3(ifd_ifc_destid3[2:0]),

                         .ifd_ifc_newdestid_s(ifd_ifc_newdestid_s[2:0]),

                         .ifd_ifc_newdestid_s(ifd_ifc_newdestid_s[2:0]),

Line 3442...

Line 1847...

                         .ifd_ifc_miladdr4_i2(ifd_ifc_miladdr4_i2[3:0]),

                         .ifd_ifc_miladdr4_i2(ifd_ifc_miladdr4_i2[3:0]),

                         .ifd_inv_wrway_i2(ifd_inv_wrway_i2[1:0]),

                         .ifd_inv_wrway_i2(ifd_inv_wrway_i2[1:0]),

                         // Inputs

                         // Inputs

                         .rclk          (rclk),

                         .rclk          (rclk),

                         .se            (se),

                         .se            (se),

                         .lsu_ifu_cpxpkt_i1(lsu_ifu_cpxpkt_i1[145-1:0]),

                         .lsu_ifu_cpxpkt_i1(lsu_ifu_cpxpkt_i1[`CPX_WIDTH-1:0]),

                         .lsu_ifu_asi_addr(lsu_ifu_asi_addr[17:0]),

                         .lsu_ifu_asi_addr(lsu_ifu_asi_addr[17:0]),

                         .lsu_ifu_stxa_data(lsu_ifu_stxa_data[47:0]),

                         .lsu_ifu_stxa_data(lsu_ifu_stxa_data[47:0]),

                         .itlb_ifq_paddr_s(itlb_ifq_paddr_s[39:10]),

                         .itlb_ifq_paddr_s(itlb_ifq_paddr_s[39:10]),

                         .ifc_ifd_reqvalid_e(ifc_ifd_reqvalid_e),

                         .ifc_ifd_reqvalid_e(ifc_ifd_reqvalid_e),

                         .ifc_ifd_filladdr4_i2(ifc_ifd_filladdr4_i2),

                         .ifc_ifd_filladdr4_i2(ifc_ifd_filladdr4_i2),

Line 3475...

Line 1880...

                         .mbist_icache_index(mbist_icache_index[7:0]));

                         .mbist_icache_index(mbist_icache_index[7:0]));

   sparc_ifu_ifqctl ifqctl(

   sparc_ifu_ifqctl ifqctl(

                           .so          (scan0_9),

                           .so          (scan0_9),

                           .si          (scan0_8),

                           .si          (scan0_8),

                           .ifd_ifc_cpxvalid_i1(lsu_ifu_cpxpkt_i1[144]),

                           .ifd_ifc_cpxvalid_i1(lsu_ifu_cpxpkt_i1[`CPX_VLD]),

                           .lsu_ifu_cpxpkt_wayvld_i1 (lsu_ifu_cpxpkt_i1[133]),

                           .lsu_ifu_cpxpkt_wayvld_i1 (lsu_ifu_cpxpkt_i1[`CPX_WYVLD]),

                           .ifq_sscan_data(ifq_sscan_data[3:0]),

                           .ifq_sscan_data(ifq_sscan_data[3:0]),

                           .rst_tri_en  (mux_drive_disable),

                           .rst_tri_en  (mux_drive_disable),

                           /*AUTOINST*/

                           /*AUTOINST*/

                           // Outputs

                           // Outputs

Line 3552...

Line 1957...

                           .ifd_ifc_milhit_s(ifd_ifc_milhit_s[3:0]),

                           .ifd_ifc_milhit_s(ifd_ifc_milhit_s[3:0]),

                           .ifd_ifc_instoffset0(ifd_ifc_instoffset0[1:0]),

                           .ifd_ifc_instoffset0(ifd_ifc_instoffset0[1:0]),

                           .ifd_ifc_instoffset1(ifd_ifc_instoffset1[1:0]),

                           .ifd_ifc_instoffset1(ifd_ifc_instoffset1[1:0]),

                           .ifd_ifc_instoffset2(ifd_ifc_instoffset2[1:0]),

                           .ifd_ifc_instoffset2(ifd_ifc_instoffset2[1:0]),

                           .ifd_ifc_instoffset3(ifd_ifc_instoffset3[1:0]),

                           .ifd_ifc_instoffset3(ifd_ifc_instoffset3[1:0]),

                           .ifd_ifc_cpxreq_i1(ifd_ifc_cpxreq_i1[(143 - 140 + 1):0]),

                           .ifd_ifc_cpxreq_i1(ifd_ifc_cpxreq_i1[`CPX_RQ_SIZE:0]),

                           .ifd_ifc_cpxreq_nxt(ifd_ifc_cpxreq_nxt[3:0]),

                           .ifd_ifc_cpxreq_nxt(ifd_ifc_cpxreq_nxt[3:0]),

                           .ifd_ifc_cpxthr_nxt(ifd_ifc_cpxthr_nxt[1:0]),

                           .ifd_ifc_cpxthr_nxt(ifd_ifc_cpxthr_nxt[1:0]),

                           .ifd_ifc_cpxvld_i2(ifd_ifc_cpxvld_i2),

                           .ifd_ifc_cpxvld_i2(ifd_ifc_cpxvld_i2),

                           .ifd_ifc_iobpkt_i2(ifd_ifc_iobpkt_i2),

                           .ifd_ifc_iobpkt_i2(ifd_ifc_iobpkt_i2),

                           .ifd_ifc_4bpkt_i2(ifd_ifc_4bpkt_i2),

                           .ifd_ifc_4bpkt_i2(ifd_ifc_4bpkt_i2),

Line 3605...

Line 2010...

                           .so          (scan0_10),

                           .so          (scan0_10),

                           .si          (scan0_9),

                           .si          (scan0_9),

                           /*AUTOINST*/

                           /*AUTOINST*/

                           // Outputs

                           // Outputs

                           .inv_ifc_inv_pending(inv_ifc_inv_pending),

                           .inv_ifc_inv_pending(inv_ifc_inv_pending),

                           .ifq_icv_wrindex_bf(ifq_icv_wrindex_bf[11:5]),

                           .ifq_icv_wrindex_bf(ifq_icv_wrindex_bf[`IC_IDX_HI:5]),

                           .ifq_icv_wren_bf(ifq_icv_wren_bf[15:0]),

                           .ifq_icv_wren_bf(ifq_icv_wren_bf[15:0]),

                           .ifq_ict_dec_wrway_bf(ifq_ict_dec_wrway_bf[3:0]),

                           .ifq_ict_dec_wrway_bf(ifq_ict_dec_wrway_bf[3:0]),

                           .ifq_fcl_invreq_bf(ifq_fcl_invreq_bf),

                           .ifq_fcl_invreq_bf(ifq_fcl_invreq_bf),

                           .ifq_erb_asiway_f(ifq_erb_asiway_f[1:0]),

                           .ifq_erb_asiway_f(ifq_erb_asiway_f[1:0]),

                           // Inputs

                           // Inputs

                           .rclk        (rclk),

                           .rclk        (rclk),

                           .se          (se),

                           .se          (se),

                           .const_cpuid (const_cpuid[2:0]),

                           .const_cpuid (const_cpuid[2:0]),

                           .mbist_icache_write(mbist_icache_write),

                           .mbist_icache_write(mbist_icache_write),

                           .lsu_ifu_ld_icache_index(lsu_ifu_ld_icache_index[11:5]),

                           .lsu_ifu_ld_icache_index(lsu_ifu_ld_icache_index[`IC_IDX_HI:5]),

                           .lsu_ifu_ld_pcxpkt_vld(lsu_ifu_ld_pcxpkt_vld),

                           .lsu_ifu_ld_pcxpkt_vld(lsu_ifu_ld_pcxpkt_vld),

                           .lsu_ifu_ld_pcxpkt_tid(lsu_ifu_ld_pcxpkt_tid[1:0]),

                           .lsu_ifu_ld_pcxpkt_tid(lsu_ifu_ld_pcxpkt_tid[1:0]),

                           .ifc_inv_ifqadv_i2(ifc_inv_ifqadv_i2),

                           .ifc_inv_ifqadv_i2(ifc_inv_ifqadv_i2),

                           .ifc_inv_asireq_i2(ifc_inv_asireq_i2),

                           .ifc_inv_asireq_i2(ifc_inv_asireq_i2),

                           .ifq_icd_index_bf(ifq_icd_index_bf[11:5]),

                           .ifq_icd_index_bf(ifq_icd_index_bf[`IC_IDX_HI:5]),

                           .ifd_inv_ifqop_i2(ifd_inv_ifqop_i2[145-1:0]),

                           .ifd_inv_ifqop_i2(ifd_inv_ifqop_i2[`CPX_WIDTH-1:0]),

                           .ifd_inv_wrway_i2(ifd_inv_wrway_i2[1:0]));

                           .ifd_inv_wrway_i2(ifd_inv_wrway_i2[1:0]));

   sparc_ifu_errdp  errdp(

   sparc_ifu_errdp  errdp(

                          .so           (scan0_11),

                          .so           (scan0_11),

                          .si           (scan0_10),

                          .si           (scan0_10),

                         .ifq_erb_wrtag_f(ifq_ict_wrtag_f[(39 - 11)-1:0]),

                         .ifq_erb_wrtag_f(ifq_ict_wrtag_f[`IC_TAG_SZ-1:0]),

                          .ict_itlb_tags_f({ict_itlb_tag3_f[28:0],

                          .ict_itlb_tags_f({ict_itlb_tag3_f[28:0],

                                            ict_itlb_tag2_f[28:0],

                                            ict_itlb_tag2_f[28:0],

                                            ict_itlb_tag1_f[28:0],

                                            ict_itlb_tag1_f[28:0],

                                            ict_itlb_tag0_f[28:0]}),

                                            ict_itlb_tag0_f[28:0]}),

                          .wsel_erb_asidata_s({wsel_mbist_icache_data[65:64],

                          .wsel_erb_asidata_s({wsel_mbist_icache_data[65:64],

Line 3670...

Line 2075...

                          .erc_erd_pgsz_b1(erc_erd_pgsz_b1),

                          .erc_erd_pgsz_b1(erc_erd_pgsz_b1),

                          .erc_erd_erren_asidata(erc_erd_erren_asidata[1:0]),

                          .erc_erd_erren_asidata(erc_erd_erren_asidata[1:0]),

                          .erc_erd_errstat_asidata(erc_erd_errstat_asidata[22:0]),

                          .erc_erd_errstat_asidata(erc_erd_errstat_asidata[22:0]),

                          .erc_erd_errinj_asidata(erc_erd_errinj_asidata[31:0]),

                          .erc_erd_errinj_asidata(erc_erd_errinj_asidata[31:0]),

                          .ifq_erb_asidata_i2(ifq_erb_asidata_i2[47:0]),

                          .ifq_erb_asidata_i2(ifq_erb_asidata_i2[47:0]),

                          .ifq_erb_wrindex_f(ifq_erb_wrindex_f[11:4]),

                          .ifq_erb_wrindex_f(ifq_erb_wrindex_f[`IC_IDX_HI:4]),

                          .erc_erd_asiway_s1_l(erc_erd_asiway_s1_l[3:0]),

                          .erc_erd_asiway_s1_l(erc_erd_asiway_s1_l[3:0]),

                          .fcl_erb_itlbrd_data_s(fcl_erb_itlbrd_data_s),

                          .fcl_erb_itlbrd_data_s(fcl_erb_itlbrd_data_s),

                          .erc_erd_ld_imask(erc_erd_ld_imask),

                          .erc_erd_ld_imask(erc_erd_ld_imask),

                          .erc_erd_asisrc_sel_icd_s_l(erc_erd_asisrc_sel_icd_s_l),

                          .erc_erd_asisrc_sel_icd_s_l(erc_erd_asisrc_sel_icd_s_l),

                          .erc_erd_asisrc_sel_misc_s_l(erc_erd_asisrc_sel_misc_s_l),

                          .erc_erd_asisrc_sel_misc_s_l(erc_erd_asisrc_sel_misc_s_l),

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[/] [s1_core/] [trunk/] [hdl/] [rtl/] [sparc_core/] [sparc_ifu.v] - Diff between revs 105 and 113