| Line 16... |
Line 16... |
// You should have received a copy of the GNU General Public
|
// You should have received a copy of the GNU General Public
|
// License along with this work; if not, write to the Free Software
|
// License along with this work; if not, write to the Free Software
|
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
|
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
|
//
|
//
|
// ========== Copyright Header End ============================================
|
// ========== Copyright Header End ============================================
|
|
`ifdef SIMPLY_RISC_TWEAKS
|
|
`define SIMPLY_RISC_SCANIN .si(0)
|
|
`define SIMPLY_RISC_SCANDATA .sd(0)
|
|
`else
|
|
`define SIMPLY_RISC_SCANIN .si()
|
|
`define SIMPLY_RISC_SCANDATA .sd()
|
|
`endif
|
////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////
|
/*
|
/*
|
// Module Name: sparc_ifu_dcl
|
// Module Name: sparc_ifu_dcl
|
// Description:
|
// Description:
|
// The decode control logic block does branch condition evaluation,
|
// The decode control logic block does branch condition evaluation,
|
| Line 30... |
Line 37... |
// choose the branch offset and immediate operand.
|
// choose the branch offset and immediate operand.
|
//
|
//
|
*/
|
*/
|
////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////
|
|
|
|
`define CC_N 3
|
|
`define CC_Z 2
|
|
`define CC_V 1
|
|
`define CC_C 0
|
|
|
|
`define FP_U 3
|
|
`define FP_G 2
|
|
`define FP_L 1
|
|
`define FP_E 0
|
|
|
|
`define FSR_FCC0_HI 11
|
|
`define FSR_FCC0_LO 10
|
|
`define FSR_FCC1_HI 33
|
|
`define FSR_FCC1_LO 32
|
|
`define FSR_FCC2_HI 35
|
|
`define FSR_FCC2_LO 34
|
|
`define FSR_FCC3_HI 37
|
|
`define FSR_FCC3_LO 36
|
|
|
|
|
module sparc_ifu_dcl(/*AUTOARG*/
|
module sparc_ifu_dcl(/*AUTOARG*/
|
// Outputs
|
// Outputs
|
ifu_exu_kill_e, ifu_exu_dontmv_regz0_e, ifu_exu_dontmv_regz1_e,
|
ifu_exu_kill_e, ifu_exu_dontmv_regz0_e, ifu_exu_dontmv_regz1_e,
|
| Line 235... |
Line 242... |
//----------------------------------------------------------------------
|
//----------------------------------------------------------------------
|
assign clk = rclk;
|
assign clk = rclk;
|
|
|
|
|
// S Stage Operands
|
// S Stage Operands
|
dff #(2) opreg(.din (fdp_dcl_op_s),
|
dff_s #(2) opreg(.din (fdp_dcl_op_s),
|
.clk (clk),
|
.clk (clk),
|
.q (op_d),
|
.q (op_d),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff #(6) op3_reg(.din (fdp_dcl_op3_s),
|
dff_s #(6) op3_reg(.din (fdp_dcl_op3_s),
|
.clk (clk),
|
.clk (clk),
|
.q (op3_d),
|
.q (op3_d),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff abite_reg(.din (imd_dcl_abit_d),
|
dff_s abite_reg(.din (imd_dcl_abit_d),
|
.clk (clk),
|
.clk (clk),
|
.q (abit_e),
|
.q (abit_e),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// need to protect from scan contention
|
// need to protect from scan contention
|
dff #(4) thre_reg(.din (swl_dcl_thr_d),
|
dff_s #(4) thre_reg(.din (swl_dcl_thr_d),
|
.q (thr_e),
|
.q (thr_e),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
//------------------------------
|
//------------------------------
|
// Choose correct immediate data
|
// Choose correct immediate data
|
//------------------------------
|
//------------------------------
|
// movcc if op3 = 101100
|
// movcc if op3 = 101100
|
| Line 306... |
Line 313... |
//------------------------------------
|
//------------------------------------
|
// mark branch/conditional instrctions
|
// mark branch/conditional instrctions
|
//------------------------------------
|
//------------------------------------
|
// call
|
// call
|
assign call_inst_d = ~op_d[1] & op_d[0];
|
assign call_inst_d = ~op_d[1] & op_d[0];
|
dff #(1) call_inste_reg(.din (call_inst_d),
|
dff_s #(1) call_inste_reg(.din (call_inst_d),
|
.clk (clk),
|
.clk (clk),
|
.q (call_inst_e),
|
.q (call_inst_e),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// call or branch but not nop/sethi
|
// call or branch but not nop/sethi
|
assign dbr_inst_d = ~op_d[1] & (op_d[0] | op3_d[4] | op3_d[3]);
|
assign dbr_inst_d = ~op_d[1] & (op_d[0] | op3_d[4] | op3_d[3]);
|
|
|
// Choose between branch offset and immediate operand
|
// Choose between branch offset and immediate operand
|
assign dcl_imd_immbr_sel_br_d = dbr_inst_d;
|
assign dcl_imd_immbr_sel_br_d = dbr_inst_d;
|
|
|
// tell exu to use pc instead of rs1
|
// tell exu to use pc instead of rs1
|
assign ifu_exu_dbrinst_d = ~op_d[1];
|
assign ifu_exu_dbrinst_d = ~op_d[1];
|
|
|
dff #(1) dbr_inste_reg(.din (dbr_inst_d),
|
dff_s #(1) dbr_inste_reg(.din (dbr_inst_d),
|
.clk (clk),
|
.clk (clk),
|
.q (dbr_inst_e),
|
.q (dbr_inst_e),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// jmpl + return
|
// jmpl + return
|
assign ibr_inst_d = op_d[1] & ~op_d[0] &
|
assign ibr_inst_d = op_d[1] & ~op_d[0] &
|
op3_d[5] & op3_d[4] & op3_d[3] &
|
op3_d[5] & op3_d[4] & op3_d[3] &
|
~op3_d[2] & ~op3_d[1];
|
~op3_d[2] & ~op3_d[1];
|
dff #(1) ibr_inste_reg(.din (ibr_inst_d),
|
dff_s #(1) ibr_inste_reg(.din (ibr_inst_d),
|
.clk (clk),
|
.clk (clk),
|
.q (ibr_inst_e),
|
.q (ibr_inst_e),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
// mov
|
// mov
|
assign mov_inst_d = (op_d[1] & ~op_d[0] &
|
assign mov_inst_d = (op_d[1] & ~op_d[0] &
|
op3_d[5] & ~op3_d[4] & op3_d[3] & op3_d[2] &
|
op3_d[5] & ~op3_d[4] & op3_d[3] & op3_d[2] &
|
(~op3_d[1] & ~op3_d[0] | op3_d[1] & op3_d[0]));
|
(~op3_d[1] & ~op3_d[0] | op3_d[1] & op3_d[0]));
|
|
|
dff #(1) mov_inste_reg(.din (mov_inst_d),
|
dff_s #(1) mov_inste_reg(.din (mov_inst_d),
|
.clk (clk),
|
.clk (clk),
|
.q (mov_inst_e),
|
.q (mov_inst_e),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
// tcc
|
// tcc
|
assign tcc_inst_d = op_d[1] & ~op_d[0] &
|
assign tcc_inst_d = op_d[1] & ~op_d[0] &
|
op3_d[5] & op3_d[4] & op3_d[3] &
|
op3_d[5] & op3_d[4] & op3_d[3] &
|
~op3_d[2] & op3_d[1] & ~op3_d[0];
|
~op3_d[2] & op3_d[1] & ~op3_d[0];
|
dff #(1) tcc_inste_reg(.din (tcc_inst_d),
|
dff_s #(1) tcc_inste_reg(.din (tcc_inst_d),
|
.clk (clk),
|
.clk (clk),
|
.q (tcc_inst_e),
|
.q (tcc_inst_e),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign mvbr_sel_br_d = ~op_d[1] & ~op_d[0] | // br
|
assign mvbr_sel_br_d = ~op_d[1] & ~op_d[0] | // br
|
op3_d[3] & ~op3_d[2] & op3_d[1] & ~op3_d[0]; // tcc
|
op3_d[3] & ~op3_d[2] & op3_d[1] & ~op3_d[0]; // tcc
|
|
|
assign cc_mvbr_d = ~(~op_d[1] & ~op_d[0] & op3_d[4] & op3_d[3] | // bpr
|
assign cc_mvbr_d = ~(~op_d[1] & ~op_d[0] & op3_d[4] & op3_d[3] | // bpr
|
| Line 390... |
Line 397... |
// assign fcc_dec_d[3] = curr_fcc_d[1] & curr_fcc_d[0];
|
// assign fcc_dec_d[3] = curr_fcc_d[1] & curr_fcc_d[0];
|
|
|
// dff #(4) fcce_reg(.din (fcc_dec_d),
|
// dff #(4) fcce_reg(.din (fcc_dec_d),
|
// .q (fcc_dec_e),
|
// .q (fcc_dec_e),
|
// .clk (clk),
|
// .clk (clk),
|
// .se (se), .si(), .so());
|
// .se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
|
|
//------------------
|
//------------------
|
// CC Logic for BCC
|
// CC Logic for BCC
|
//------------------
|
//------------------
|
| Line 409... |
Line 416... |
// 011 fcc3
|
// 011 fcc3
|
// assign use_xcc_d = (dec_dcl_cctype_d[2] | op3_d[3]) & dec_dcl_cctype_d[1];
|
// assign use_xcc_d = (dec_dcl_cctype_d[2] | op3_d[3]) & dec_dcl_cctype_d[1];
|
assign use_xcc_d = dec_dcl_cctype_d[1];
|
assign use_xcc_d = dec_dcl_cctype_d[1];
|
assign fpcond_mvbr_d = ~dec_dcl_cctype_d[2] & ~tcc_inst_d;
|
assign fpcond_mvbr_d = ~dec_dcl_cctype_d[2] & ~tcc_inst_d;
|
|
|
dff fpbr_reg(.din (fpcond_mvbr_d),
|
dff_s fpbr_reg(.din (fpcond_mvbr_d),
|
.clk (clk),
|
.clk (clk),
|
.q (fpcond_mvbr_e),
|
.q (fpcond_mvbr_e),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// mux between xcc and icc
|
// mux between xcc and icc
|
// assign cc_d = use_xcc_d ? exu_ifu_cc_d[7:4] : // xcc
|
// assign cc_d = use_xcc_d ? exu_ifu_cc_d[7:4] : // xcc
|
// exu_ifu_cc_d[3:0]; // icc
|
// exu_ifu_cc_d[3:0]; // icc
|
// dff #(4) ccreg_e(.din (cc_d),
|
// dff #(4) ccreg_e(.din (cc_d),
|
// .clk (clk),
|
// .clk (clk),
|
// .q (cc_e),
|
// .q (cc_e),
|
// .se (se), .si(), .so());
|
// .se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
bw_u1_soffm2_4x UZsize_ccreg0_e(.d0 (exu_ifu_cc_d[0]),
|
bw_u1_soffm2_4x UZsize_ccreg0_e(.d0 (exu_ifu_cc_d[0]),
|
.d1 (exu_ifu_cc_d[4]),
|
.d1 (exu_ifu_cc_d[4]),
|
.s (use_xcc_d),
|
.s (use_xcc_d),
|
.q (cc_e[0]),
|
.q (cc_e[0]),
|
.ck (clk), .se(se), .sd(), .so());
|
.ck (clk), .se(se), `SIMPLY_RISC_SCANDATA, .so());
|
bw_u1_soffm2_4x UZsize_ccreg1_e(.d0 (exu_ifu_cc_d[1]),
|
bw_u1_soffm2_4x UZsize_ccreg1_e(.d0 (exu_ifu_cc_d[1]),
|
.d1 (exu_ifu_cc_d[5]),
|
.d1 (exu_ifu_cc_d[5]),
|
.s (use_xcc_d),
|
.s (use_xcc_d),
|
.q (cc_e[1]),
|
.q (cc_e[1]),
|
.ck (clk), .se(se), .sd(), .so());
|
.ck (clk), .se(se), `SIMPLY_RISC_SCANDATA, .so());
|
bw_u1_soffm2_4x UZsize_ccreg2_e(.d0 (exu_ifu_cc_d[2]),
|
bw_u1_soffm2_4x UZsize_ccreg2_e(.d0 (exu_ifu_cc_d[2]),
|
.d1 (exu_ifu_cc_d[6]),
|
.d1 (exu_ifu_cc_d[6]),
|
.s (use_xcc_d),
|
.s (use_xcc_d),
|
.q (cc_e[2]),
|
.q (cc_e[2]),
|
.ck (clk), .se(se), .sd(), .so());
|
.ck (clk), .se(se), `SIMPLY_RISC_SCANDATA, .so());
|
bw_u1_soffm2_4x UZsize_ccreg3_e(.d0 (exu_ifu_cc_d[3]),
|
bw_u1_soffm2_4x UZsize_ccreg3_e(.d0 (exu_ifu_cc_d[3]),
|
.d1 (exu_ifu_cc_d[7]),
|
.d1 (exu_ifu_cc_d[7]),
|
.s (use_xcc_d),
|
.s (use_xcc_d),
|
.q (cc_e[3]),
|
.q (cc_e[3]),
|
.ck (clk), .se(se), .sd(), .so());
|
.ck (clk), .se(se), `SIMPLY_RISC_SCANDATA, .so());
|
|
|
|
|
//------------------------------
|
//------------------------------
|
// Evaluate Branch
|
// Evaluate Branch
|
//------------------------------
|
//------------------------------
|
| Line 460... |
Line 467... |
.in2 (imd_dcl_mvcond_d[3:0]), // movr
|
.in2 (imd_dcl_mvcond_d[3:0]), // movr
|
.sel0 (mvbr_sel_br_d),
|
.sel0 (mvbr_sel_br_d),
|
.sel1 (sel_movcc),
|
.sel1 (sel_movcc),
|
.sel2 (sel_movr));
|
.sel2 (sel_movr));
|
|
|
dff #(4) brcond_e_reg(.din (br_cond_d),
|
dff_s #(4) brcond_e_reg(.din (br_cond_d),
|
.clk (clk),
|
.clk (clk),
|
.q (br_cond_e),
|
.q (br_cond_e),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// Branch Type Decode
|
// Branch Type Decode
|
assign ls_brcond_d[0] = ~br_cond_d[1] & ~br_cond_d[0];
|
assign ls_brcond_d[0] = ~br_cond_d[1] & ~br_cond_d[0];
|
assign ls_brcond_d[1] = ~br_cond_d[1] & br_cond_d[0];
|
assign ls_brcond_d[1] = ~br_cond_d[1] & br_cond_d[0];
|
assign ls_brcond_d[2] = br_cond_d[1] & ~br_cond_d[0];
|
assign ls_brcond_d[2] = br_cond_d[1] & ~br_cond_d[0];
|
assign ls_brcond_d[3] = br_cond_d[1] & br_cond_d[0];
|
assign ls_brcond_d[3] = br_cond_d[1] & br_cond_d[0];
|
|
|
dff #(4) lsbrc_e_reg(.din (ls_brcond_d),
|
dff_s #(4) lsbrc_e_reg(.din (ls_brcond_d),
|
.clk (clk),
|
.clk (clk),
|
.q (ls_brcond_e),
|
.q (ls_brcond_e),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// Evaluate potential integer CC branches
|
// Evaluate potential integer CC branches
|
assign ltz_e = (cc_e[3] ^ cc_e[1]);
|
assign ltz_e = (cc_e[`CC_N] ^ cc_e[`CC_V]);
|
|
|
assign cc_breval_e[0] = 1'b0; // BPN
|
assign cc_breval_e[0] = 1'b0; // BPN
|
assign cc_breval_e[1] = cc_e[2]; // BPE
|
assign cc_breval_e[1] = cc_e[`CC_Z]; // BPE
|
assign cc_breval_e[2] = cc_e[2] | ltz_e; // BPLE
|
assign cc_breval_e[2] = cc_e[`CC_Z] | ltz_e; // BPLE
|
assign cc_breval_e[3] = ltz_e; // BPL
|
assign cc_breval_e[3] = ltz_e; // BPL
|
assign cc_breval_e[4] = cc_e[2] | cc_e[0]; // BPLEU
|
assign cc_breval_e[4] = cc_e[`CC_Z] | cc_e[`CC_C]; // BPLEU
|
assign cc_breval_e[5] = cc_e[0]; // BPCS
|
assign cc_breval_e[5] = cc_e[`CC_C]; // BPCS
|
assign cc_breval_e[6] = cc_e[3]; // BPNEG
|
assign cc_breval_e[6] = cc_e[`CC_N]; // BPNEG
|
assign cc_breval_e[7] = cc_e[1]; // BPVS
|
assign cc_breval_e[7] = cc_e[`CC_V]; // BPVS
|
|
|
// mux to choose right condition
|
// mux to choose right condition
|
assign cc_eval0 = cc_breval_e[0] & ls_brcond_e[0] |
|
assign cc_eval0 = cc_breval_e[0] & ls_brcond_e[0] |
|
cc_breval_e[1] & ls_brcond_e[1] |
|
cc_breval_e[1] & ls_brcond_e[1] |
|
cc_breval_e[2] & ls_brcond_e[2] |
|
cc_breval_e[2] & ls_brcond_e[2] |
|
| Line 522... |
Line 529... |
fp_breval_d[7] & ls_brcond_d[3];
|
fp_breval_d[7] & ls_brcond_d[3];
|
|
|
assign fp_eval_d = br_cond_d[2] ? fp_eval1_d :
|
assign fp_eval_d = br_cond_d[2] ? fp_eval1_d :
|
fp_eval0_d;
|
fp_eval0_d;
|
|
|
dff #(1) fpev_ff(.din (fp_eval_d),
|
dff_s #(1) fpev_ff(.din (fp_eval_d),
|
.q (fp_eval_e),
|
.q (fp_eval_e),
|
.clk (clk),
|
.clk (clk),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// merge eval0, eval1 and fp condition codes
|
// merge eval0, eval1 and fp condition codes
|
assign ccfp_sel[0] = ~fpcond_mvbr_e & ~br_cond_e[2];
|
assign ccfp_sel[0] = ~fpcond_mvbr_e & ~br_cond_e[2];
|
assign ccfp_sel[1] = ~fpcond_mvbr_e & br_cond_e[2];
|
assign ccfp_sel[1] = ~fpcond_mvbr_e & br_cond_e[2];
|
// assign ccfp_sel[2] = fpcond_mvbr_e & ~br_cond_e[2];
|
// assign ccfp_sel[2] = fpcond_mvbr_e & ~br_cond_e[2];
|
| Line 561... |
Line 568... |
// br_cond_e[2]) & ~cc_mvbr_e;
|
// br_cond_e[2]) & ~cc_mvbr_e;
|
assign r_eval0 = exu_ifu_regn_e ? ((br_cond_e[1] ^ br_cond_e[2]) &
|
assign r_eval0 = exu_ifu_regn_e ? ((br_cond_e[1] ^ br_cond_e[2]) &
|
~cc_mvbr_e) :
|
~cc_mvbr_e) :
|
(br_cond_e[2] & ~cc_mvbr_e);
|
(br_cond_e[2] & ~cc_mvbr_e);
|
|
|
dff #(1) regcc_ff(.din (cc_mvbr_d),
|
dff_s #(1) regcc_ff(.din (cc_mvbr_d),
|
.clk (clk),
|
.clk (clk),
|
.q (cc_mvbr_e),
|
.q (cc_mvbr_e),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// Evaluate Final Branch condition
|
// Evaluate Final Branch condition
|
// 3:1 mux
|
// 3:1 mux
|
// assign cond_brtaken_e = cc_mvbr_e ? ccbr_taken_e :
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// assign cond_brtaken_e = cc_mvbr_e ? ccbr_taken_e :
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// exu_ifu_regz_e ? r_eval1 :
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// exu_ifu_regz_e ? r_eval1 :
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| Line 607... |
Line 614... |
// assign ifu_exu_dontmove_e = mov_inst_e & ~cond_brtaken_e;
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// assign ifu_exu_dontmove_e = mov_inst_e & ~cond_brtaken_e;
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assign ifu_exu_dontmv_regz0_e = ~temp0 & mov_inst_e;
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assign ifu_exu_dontmv_regz0_e = ~temp0 & mov_inst_e;
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assign ifu_exu_dontmv_regz1_e = ~temp1 & mov_inst_e;
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assign ifu_exu_dontmv_regz1_e = ~temp1 & mov_inst_e;
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// branch condition to FPU
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// branch condition to FPU
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dff #(1) fpcond_ff(.din (cond_brtaken_e),
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dff_s #(1) fpcond_ff(.din (cond_brtaken_e),
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.q (ifu_ffu_mvcnd_m),
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.q (ifu_ffu_mvcnd_m),
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.clk (clk),
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.clk (clk),
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.se (se), .si(), .so());
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.se (se), `SIMPLY_RISC_SCANIN, .so());
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// branch / move completion and anull signals
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// branch / move completion and anull signals
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// assign dtu_fcl_brtaken_e = ~dtu_inst_anull_e &
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// assign dtu_fcl_brtaken_e = ~dtu_inst_anull_e &
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// (ibr_inst_e | call_inst_e |
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// (ibr_inst_e | call_inst_e |
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// dbr_inst_e & cond_brtaken_e);
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// dbr_inst_e & cond_brtaken_e);
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| Line 631... |
Line 638... |
fcl_dtu_inst_vld_e;
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fcl_dtu_inst_vld_e;
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|
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assign tcc_done_e = ~dtu_inst_anull_e & tcc_inst_e & ~ccbr_taken_e &
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assign tcc_done_e = ~dtu_inst_anull_e & tcc_inst_e & ~ccbr_taken_e &
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fcl_dtu_inst_vld_e;
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fcl_dtu_inst_vld_e;
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|
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dff #(1) tccm_ff(.din (tcc_done_e),
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dff_s #(1) tccm_ff(.din (tcc_done_e),
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.q (dcl_swl_tcc_done_m),
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.q (dcl_swl_tcc_done_m),
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.clk (clk),
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.clk (clk),
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.se (se), .si(), .so());
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.se (se), `SIMPLY_RISC_SCANIN, .so());
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// logic to anull delay slot, if this branch itsel is not anulled
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// logic to anull delay slot, if this branch itsel is not anulled
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assign anull_cbr = abit_e & dbr_inst_e & ~br_always_e & ~call_inst_e;
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assign anull_cbr = abit_e & dbr_inst_e & ~br_always_e & ~call_inst_e;
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assign anull_ubr = abit_e & dbr_inst_e & br_always_e & ~call_inst_e;
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assign anull_ubr = abit_e & dbr_inst_e & br_always_e & ~call_inst_e;
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| Line 646... |
Line 653... |
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// check which thread to anull
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// check which thread to anull
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assign thr_vld_e = thr_e & {4{fcl_dtu_inst_vld_e}};
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assign thr_vld_e = thr_e & {4{fcl_dtu_inst_vld_e}};
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|
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assign all_flush_w = tlu_ifu_flush_pipe_w | ifu_tlu_flush_w;
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assign all_flush_w = tlu_ifu_flush_pipe_w | ifu_tlu_flush_w;
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dff #(1) flshw2_ff(.din (all_flush_w),
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dff_s #(1) flshw2_ff(.din (all_flush_w),
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.q (all_flush_w2),
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.q (all_flush_w2),
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.clk (clk), .se(se), .si(), .so());
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.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
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|
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assign flush_abit = swl_dcl_thr_w2 & {4{all_flush_w2}};
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assign flush_abit = swl_dcl_thr_w2 & {4{all_flush_w2}};
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assign anull_next_e = ((~anull_e & {4{anull_all}} & thr_vld_e) |
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assign anull_next_e = ((~anull_e & {4{anull_all}} & thr_vld_e) |
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(anull_e & ~(thr_e & {4{fcl_dtu_inst_vld_e |
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(anull_e & ~(thr_e & {4{fcl_dtu_inst_vld_e |
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fcl_dtu_intr_vld_e}}))) &
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fcl_dtu_intr_vld_e}}))) &
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~flush_abit;
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~flush_abit;
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|
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// anull_e needs to be per thread
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// anull_e needs to be per thread
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dffr #(4) anull_ff(.din (anull_next_e),
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dffr_s #(4) anull_ff(.din (anull_next_e),
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.clk (clk),
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.clk (clk),
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.rst (dtu_reset),
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.rst (dtu_reset),
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.q (anull_e),
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.q (anull_e),
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.se (se), .si(), .so());
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.se (se), `SIMPLY_RISC_SCANIN, .so());
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|
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//
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//
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// assign thr_dec_e[0] = swl_dcl_thr_e[0] | rst_tri_enable;
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// assign thr_dec_e[0] = swl_dcl_thr_e[0] | rst_tri_enable;
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// assign thr_dec_e[3:1] = swl_dcl_thr_e[3:1] & {3{~rst_tri_enable}};
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// assign thr_dec_e[3:1] = swl_dcl_thr_e[3:1] & {3{~rst_tri_enable}};
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|
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assign thr_anull_d = swl_dcl_thr_d & anull_next_e;
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assign thr_anull_d = swl_dcl_thr_d & anull_next_e;
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assign inst_anull_d = (|thr_anull_d[3:0]);
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assign inst_anull_d = (|thr_anull_d[3:0]);
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dff #(1) ina_ff(.din (inst_anull_d),
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dff_s #(1) ina_ff(.din (inst_anull_d),
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.q (inst_anull_e),
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.q (inst_anull_e),
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.clk (clk), .se (se), .si(), .so());
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.clk (clk), .se (se), `SIMPLY_RISC_SCANIN, .so());
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|
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assign dtu_inst_anull_e = inst_anull_e;
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assign dtu_inst_anull_e = inst_anull_e;
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|
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// mux4ds dcla_mux(.dout (this_inst_anull_e),
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// mux4ds dcla_mux(.dout (this_inst_anull_e),
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// .in0 (anull_e[0]),
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// .in0 (anull_e[0]),
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| Line 701... |
Line 708... |
.in0 (t0_fcc_d[7:0]),
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.in0 (t0_fcc_d[7:0]),
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.in1 (ffu_ifu_cc_w2[7:0]),
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.in1 (ffu_ifu_cc_w2[7:0]),
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.sel0 (~ffu_ifu_cc_vld_w2[0]),
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.sel0 (~ffu_ifu_cc_vld_w2[0]),
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.sel1 (ffu_ifu_cc_vld_w2[0]));
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.sel1 (ffu_ifu_cc_vld_w2[0]));
|
|
|
dffr #(8) t0_fcc_reg(.din (t0_fcc_nxt[7:0]),
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dffr_s #(8) t0_fcc_reg(.din (t0_fcc_nxt[7:0]),
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.q (t0_fcc_d[7:0]),
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.q (t0_fcc_d[7:0]),
|
.rst (dtu_reset),
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.rst (dtu_reset),
|
.clk (clk), .se (se), .si(), .so());
|
.clk (clk), .se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
`ifdef FPGA_SYN_1THREAD
|
|
assign fcc_d[7:0] = t0_fcc_d[7:0];
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`else
|
|
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mux2ds #(8) t1_fcc_mux(.dout (t1_fcc_nxt[7:0]),
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mux2ds #(8) t1_fcc_mux(.dout (t1_fcc_nxt[7:0]),
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.in0 (t1_fcc_d[7:0]),
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.in0 (t1_fcc_d[7:0]),
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.in1 (ffu_ifu_cc_w2[7:0]),
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.in1 (ffu_ifu_cc_w2[7:0]),
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.sel0 (~ffu_ifu_cc_vld_w2[1]),
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.sel0 (~ffu_ifu_cc_vld_w2[1]),
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| Line 729... |
Line 736... |
.sel0 (~ffu_ifu_cc_vld_w2[3]),
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.sel0 (~ffu_ifu_cc_vld_w2[3]),
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.sel1 (ffu_ifu_cc_vld_w2[3]));
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.sel1 (ffu_ifu_cc_vld_w2[3]));
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|
|
// thread0 fcc registers
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// thread0 fcc registers
|
|
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dffr #(8) t1_fcc_reg(.din (t1_fcc_nxt[7:0]),
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dffr_s #(8) t1_fcc_reg(.din (t1_fcc_nxt[7:0]),
|
.q (t1_fcc_d[7:0]),
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.q (t1_fcc_d[7:0]),
|
.rst (dtu_reset),
|
.rst (dtu_reset),
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.clk (clk), .se (se), .si(), .so());
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.clk (clk), .se (se), `SIMPLY_RISC_SCANIN, .so());
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dffr #(8) t2_fcc_reg(.din (t2_fcc_nxt[7:0]),
|
dffr_s #(8) t2_fcc_reg(.din (t2_fcc_nxt[7:0]),
|
.q (t2_fcc_d[7:0]),
|
.q (t2_fcc_d[7:0]),
|
.rst (dtu_reset),
|
.rst (dtu_reset),
|
.clk (clk), .se (se), .si(), .so());
|
.clk (clk), .se (se), `SIMPLY_RISC_SCANIN, .so());
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dffr #(8) t3_fcc_reg(.din (t3_fcc_nxt[7:0]),
|
dffr_s #(8) t3_fcc_reg(.din (t3_fcc_nxt[7:0]),
|
.q (t3_fcc_d[7:0]),
|
.q (t3_fcc_d[7:0]),
|
.rst (dtu_reset),
|
.rst (dtu_reset),
|
.clk (clk), .se (se), .si(), .so());
|
.clk (clk), .se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// choose thread
|
// choose thread
|
assign thr_dec_d[0] = swl_dcl_thr_d[0];
|
assign thr_dec_d[0] = swl_dcl_thr_d[0];
|
assign thr_dec_d[3:1] = swl_dcl_thr_d[3:1];
|
assign thr_dec_d[3:1] = swl_dcl_thr_d[3:1];
|
|
|
| Line 756... |
Line 763... |
.sel0 (thr_dec_d[0]),
|
.sel0 (thr_dec_d[0]),
|
.sel1 (thr_dec_d[1]),
|
.sel1 (thr_dec_d[1]),
|
.sel2 (thr_dec_d[2]),
|
.sel2 (thr_dec_d[2]),
|
.sel3 (thr_dec_d[3]));
|
.sel3 (thr_dec_d[3]));
|
|
|
// !`ifdef FPGA_SYN_1THREAD
|
`endif // !`ifdef FPGA_SYN_1THREAD
|
|
|
endmodule // sparc_ifu_dcl
|
endmodule // sparc_ifu_dcl
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No newline at end of file
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No newline at end of file
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