| Line 16... |
Line 16... |
// You should have received a copy of the GNU General Public
|
// You should have received a copy of the GNU General Public
|
// License along with this work; if not, write to the Free Software
|
// License along with this work; if not, write to the Free Software
|
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
|
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
|
//
|
//
|
// ========== Copyright Header End ============================================
|
// ========== Copyright Header End ============================================
|
|
`ifdef SIMPLY_RISC_TWEAKS
|
|
`define SIMPLY_RISC_SCANIN .si(0)
|
|
`else
|
|
`define SIMPLY_RISC_SCANIN .si()
|
|
`endif
|
////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////
|
/*
|
/*
|
// Module Name: sparc_ifu_dec
|
// Module Name: sparc_ifu_dec
|
// Description:
|
// Description:
|
// The decode block implements the sparc instruction decode ROM
|
// The decode block implements the sparc instruction decode ROM
|
| Line 673... |
Line 678... |
assign quad_ffuop_d = (opf[1] & opf[0] & (fpop1_d | fpop2_d) |
|
assign quad_ffuop_d = (opf[1] & opf[0] & (fpop1_d | fpop2_d) |
|
fpop1_d & opf[3] & opf[2] & // exc div
|
fpop1_d & opf[3] & opf[2] & // exc div
|
~(~opf[7] & opf[6] & ~opf[5])) &
|
~(~opf[7] & opf[6] & ~opf[5])) &
|
swl_dec_fp_enable_d & fcl_dtu_inst_vld_d;
|
swl_dec_fp_enable_d & fcl_dtu_inst_vld_d;
|
|
|
dff #(1) qope_ff(.din (quad_ffuop_d),
|
dff_s #(1) qope_ff(.din (quad_ffuop_d),
|
.q (ifu_ffu_quad_op_e),
|
.q (ifu_ffu_quad_op_e),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// quiet traps -- flush the pipe but don't take a trap till later
|
// quiet traps -- flush the pipe but don't take a trap till later
|
// assign dec_swl_qtrap_d = mem_inst & op3[5] & op3_lo[6] & fcl_dtu_inst_vld_d; // stq
|
// assign dec_swl_qtrap_d = mem_inst & op3[5] & op3_lo[6] & fcl_dtu_inst_vld_d; // stq
|
// dff #(1) qtrpe_ff(.din (dec_swl_qtrap_d),
|
// dff #(1) qtrpe_ff(.din (dec_swl_qtrap_d),
|
// .q (dtu_fcl_qtrap_e),
|
// .q (dtu_fcl_qtrap_e),
|
// .clk (clk), .se(se), .si(), .so());
|
// .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// FP Enabled check
|
// FP Enabled check
|
assign fcc_branch_d = ~op[1] & ~op[0] & op3[5] & (op3[4] | op3[3]);
|
assign fcc_branch_d = ~op[1] & ~op[0] & op3[5] & (op3[4] | op3[3]);
|
assign fcc_mov_d = op[1] & ~op[0] & op3_hi[2] & op3_lo[12] &
|
assign fcc_mov_d = op[1] & ~op[0] & op3_hi[2] & op3_lo[12] &
|
~dtu_inst_d[18];
|
~dtu_inst_d[18];
|
| Line 694... |
Line 699... |
arith_inst & op3_hi[2] & op3_lo[8] & rs1_13 | // rd gsr
|
arith_inst & op3_hi[2] & op3_lo[8] & rs1_13 | // rd gsr
|
arith_inst & op3_hi[3] & op3_lo[0] & rd_13; // wr gsr
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arith_inst & op3_hi[3] & op3_lo[0] & rd_13; // wr gsr
|
|
|
assign fpdis_trap_d = any_fpinst_d & ~swl_dec_fp_enable_d &
|
assign fpdis_trap_d = any_fpinst_d & ~swl_dec_fp_enable_d &
|
fcl_dtu_inst_vld_d;
|
fcl_dtu_inst_vld_d;
|
dff #(1) fpdise_ff(.din (fpdis_trap_d),
|
dff_s #(1) fpdise_ff(.din (fpdis_trap_d),
|
.q (fpdis_trap_e),
|
.q (fpdis_trap_e),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
assign dtu_fcl_fpdis_e = fpdis_trap_e;
|
assign dtu_fcl_fpdis_e = fpdis_trap_e;
|
|
|
// FRF dirty bits
|
// FRF dirty bits
|
// bit 0 is the msb for double and quad
|
// bit 0 is the msb for double and quad
|
assign dec_swl_frf_upper_d = rd[0] & (mem_inst & op3_lo[3] | // fld
|
assign dec_swl_frf_upper_d = rd[0] & (mem_inst & op3_lo[3] | // fld
|
| Line 790... |
Line 795... |
(op3_lo[2] & ~rd_09 | // wrpr exc. cwp
|
(op3_lo[2] & ~rd_09 | // wrpr exc. cwp
|
op3_lo[0] & ~rd_1a | // wr exc. thr
|
op3_lo[0] & ~rd_1a | // wr exc. thr
|
op3_lo[3]); // wrhpr
|
op3_lo[3]); // wrhpr
|
|
|
|
|
dff #(1) wre_ff(.din (wsr_fixed_inst_d),
|
dff_s #(1) wre_ff(.din (wsr_fixed_inst_d),
|
.clk (clk),
|
.clk (clk),
|
.q (wsr_fixed_inst_e),
|
.q (wsr_fixed_inst_e),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign wsr_inst_next_e = (~dtu_inst_anull_e) & wsr_fixed_inst_e &
|
assign wsr_inst_next_e = (~dtu_inst_anull_e) & wsr_fixed_inst_e &
|
fcl_dtu_inst_vld_e;
|
fcl_dtu_inst_vld_e;
|
|
|
dff #(1) wrm_ff(.din (wsr_inst_next_e),
|
dff_s #(1) wrm_ff(.din (wsr_inst_next_e),
|
.clk (clk),
|
.clk (clk),
|
.q (wsr_fixed_inst_m),
|
.q (wsr_fixed_inst_m),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff #(1) wrw_ff(.din (wsr_fixed_inst_m),
|
dff_s #(1) wrw_ff(.din (wsr_fixed_inst_m),
|
.clk (clk),
|
.clk (clk),
|
.q (wsr_fixed_inst_w),
|
.q (wsr_fixed_inst_w),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign use_rsr_d_l = ~(ifu_tlu_rsr_inst_d | ibr_inst_d | call_inst);
|
assign use_rsr_d_l = ~(ifu_tlu_rsr_inst_d | ibr_inst_d | call_inst);
|
|
|
dff #(1) rdsre_ff(.din (use_rsr_d_l),
|
dff_s #(1) rdsre_ff(.din (use_rsr_d_l),
|
.clk (clk),
|
.clk (clk),
|
.q (ifu_exu_use_rsr_e_l),
|
.q (ifu_exu_use_rsr_e_l),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign flush_inst_d = fcl_dtu_inst_vld_d & arith_inst &
|
assign flush_inst_d = fcl_dtu_inst_vld_d & arith_inst &
|
op3_hi[3] & op3_lo[11];
|
op3_hi[3] & op3_lo[11];
|
|
|
dff #(1) flsh_ff(.din (flush_inst_d),
|
dff_s #(1) flsh_ff(.din (flush_inst_d),
|
.q (ifu_tlu_flsh_inst_e),
|
.q (ifu_tlu_flsh_inst_e),
|
.clk (clk),
|
.clk (clk),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
|
|
// If machine state is changed kill the already fetched instructions
|
// If machine state is changed kill the already fetched instructions
|
assign state_chg_inst_d = ifu_lsu_wsr_inst_d | flush_inst_d |
|
assign state_chg_inst_d = ifu_lsu_wsr_inst_d | flush_inst_d |
|
ifu_tlu_done_inst_d | ifu_tlu_retry_inst_d;
|
ifu_tlu_done_inst_d | ifu_tlu_retry_inst_d;
|
|
|
|
|
dff #(1) schg_ff(.din (state_chg_inst_d),
|
dff_s #(1) schg_ff(.din (state_chg_inst_d),
|
.clk (clk),
|
.clk (clk),
|
.q (state_chg_inst_e),
|
.q (state_chg_inst_e),
|
// .rst (reset),
|
// .rst (reset),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// assign sta_inst_d = mem_inst & op3[4] & fcl_dtu_inst_vld_d &
|
// assign sta_inst_d = mem_inst & op3[4] & fcl_dtu_inst_vld_d &
|
// (~op3[5] & ~op3[3] & op3[2] |
|
// (~op3[5] & ~op3[3] & op3[2] |
|
// op3[5] & (op3_lo[4] | op3_lo[7]) |
|
// op3[5] & (op3_lo[4] | op3_lo[7]) |
|
// ~op3[5] & op3_lo[14]);
|
// ~op3[5] & op3_lo[14]);
|
| Line 845... |
Line 850... |
|
|
assign sta_nostf_d = mem_inst & op3[4] & fcl_dtu_inst_vld_d &
|
assign sta_nostf_d = mem_inst & op3[4] & fcl_dtu_inst_vld_d &
|
(~op3[5] & ~op3[3] & op3[2] |
|
(~op3[5] & ~op3[3] & op3[2] |
|
~op3[5] & op3_lo[14]);
|
~op3[5] & op3_lo[14]);
|
|
|
dff #(1) sta_ff (.din (sta_inst_d),
|
dff_s #(1) sta_ff (.din (sta_inst_d),
|
.clk (clk),
|
.clk (clk),
|
.q (sta_inst_e),
|
.q (sta_inst_e),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff #(1) stanf_ff (.din (sta_nostf_d),
|
dff_s #(1) stanf_ff (.din (sta_nostf_d),
|
.clk (clk),
|
.clk (clk),
|
.q (sta_nostf_e),
|
.q (sta_nostf_e),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign dec_swl_sta_inst_e = sta_nostf_e;
|
assign dec_swl_sta_inst_e = sta_nostf_e;
|
|
|
// Mov qualification with inst_vld_e to FCL? Done
|
// Mov qualification with inst_vld_e to FCL? Done
|
assign dtu_fcl_flush_sonly_e = (sta_inst_e & lsu_ifu_ldsta_internal_e |
|
assign dtu_fcl_flush_sonly_e = (sta_inst_e & lsu_ifu_ldsta_internal_e |
|
state_chg_inst_e);
|
state_chg_inst_e);
|
|
|
dff #(1) ds_ff(.din (fcl_dec_dslot_s),
|
dff_s #(1) ds_ff(.din (fcl_dec_dslot_s),
|
.q (dslot_d),
|
.q (dslot_d),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// suppress ifetch if arch state changes in delay slot (if not
|
// suppress ifetch if arch state changes in delay slot (if not
|
// suppressed, it may cause in error in the L2 for an unmapped
|
// suppressed, it may cause in error in the L2 for an unmapped
|
// address).
|
// address).
|
// assign dtu_ifq_kill_latest_d = ifu_lsu_wsr_inst_d | flush_inst_d |
|
// assign dtu_ifq_kill_latest_d = ifu_lsu_wsr_inst_d | flush_inst_d |
|
| Line 883... |
Line 888... |
// ~op3[5] & // sta - excl stf and pref
|
// ~op3[5] & // sta - excl stf and pref
|
// fcl_dtu_ely_inst_vld_d & dslot_d; // in DS
|
// fcl_dtu_ely_inst_vld_d & dslot_d; // in DS
|
|
|
// dff #(1) kfste_ff(.din (kill_for_sta_d),
|
// dff #(1) kfste_ff(.din (kill_for_sta_d),
|
// .q (kill_for_sta_e),
|
// .q (kill_for_sta_e),
|
// .clk (clk), .se(se), .si(), .so());
|
// .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
// assign dec_fcl_kill4sta_e = kill_for_sta_e;
|
// assign dec_fcl_kill4sta_e = kill_for_sta_e;
|
|
|
assign rd_ifusr_d = arith_inst & op3_hi[2] &
|
assign rd_ifusr_d = arith_inst & op3_hi[2] &
|
(op3_lo[9] & rs1_06 | // rdhpr - ver
|
(op3_lo[9] & rs1_06 | // rdhpr - ver
|
op3_lo[8] & (rs1_05 | // rdsr - pc
|
op3_lo[8] & (rs1_05 | // rdsr - pc
|
| Line 901... |
Line 906... |
op3_lo[8] & (rs1_00 | rs1_02)); // rdsr (y + ccr)
|
op3_lo[8] & (rs1_00 | rs1_02)); // rdsr (y + ccr)
|
|
|
assign rd_ffusr_d = arith_inst & op3_hi[2] &
|
assign rd_ffusr_d = arith_inst & op3_hi[2] &
|
op3_lo[8] & rs1_13; // rdsr (gsr)
|
op3_lo[8] & rs1_13; // rdsr (gsr)
|
|
|
dff #(1) ifusr_ff(.din (rd_ifusr_d),
|
dff_s #(1) ifusr_ff(.din (rd_ifusr_d),
|
.clk (clk),
|
.clk (clk),
|
.q (rd_ifusr_e),
|
.q (rd_ifusr_e),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
dff #(1) ffusr_ff(.din (rd_ffusr_d),
|
dff_s #(1) ffusr_ff(.din (rd_ffusr_d),
|
.clk (clk),
|
.clk (clk),
|
.q (rd_ffusr_e),
|
.q (rd_ffusr_e),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
dff #(1) exusr_ff(.din (rd_exusr_d),
|
dff_s #(1) exusr_ff(.din (rd_exusr_d),
|
.clk (clk),
|
.clk (clk),
|
.q (rd_exusr_e),
|
.q (rd_exusr_e),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// make sure they are exclusive
|
// make sure they are exclusive
|
assign ifu_exu_rd_ifusr_e = rd_ifusr_e;
|
assign ifu_exu_rd_ifusr_e = rd_ifusr_e;
|
assign ifu_exu_rd_exusr_e = rd_exusr_e;
|
assign ifu_exu_rd_exusr_e = rd_exusr_e;
|
assign ifu_exu_rd_ffusr_e = rd_ffusr_e;
|
assign ifu_exu_rd_ffusr_e = rd_ffusr_e;
|
| Line 928... |
Line 933... |
assign dec_fcl_rdsr_sel_thr_d = dtu_inst_d[31] & op3_hi[2] & op3_lo[8] & ~rs1[0];
|
assign dec_fcl_rdsr_sel_thr_d = dtu_inst_d[31] & op3_hi[2] & op3_lo[8] & ~rs1[0];
|
// else version reg (rdhpr 06)
|
// else version reg (rdhpr 06)
|
|
|
// dff #(1) rdfprs_ff(.din (rs1[4]),
|
// dff #(1) rdfprs_ff(.din (rs1[4]),
|
// .q (dec_swl_rdsr_sel_thr_e),
|
// .q (dec_swl_rdsr_sel_thr_e),
|
// .clk (clk), .se(se), .si(), .so());
|
// .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
assign dec_swl_rdsr_sel_thr_d = rs1[4];
|
assign dec_swl_rdsr_sel_thr_d = rs1[4];
|
|
|
assign wrt_tcr_d = arith_inst & fcl_dtu_inst_vld_d &
|
assign wrt_tcr_d = arith_inst & fcl_dtu_inst_vld_d &
|
op3_hi[3] & op3_lo[0] & rd_1a;
|
op3_hi[3] & op3_lo[0] & rd_1a;
|
|
|
dff #(1) tcre_ff(.din (wrt_tcr_d),
|
dff_s #(1) tcre_ff(.din (wrt_tcr_d),
|
.clk (clk),
|
.clk (clk),
|
.q (wrt_tcr_e),
|
.q (wrt_tcr_e),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign wrt_tcr_qual_e = wrt_tcr_e & (~dtu_inst_anull_e) &
|
assign wrt_tcr_qual_e = wrt_tcr_e & (~dtu_inst_anull_e) &
|
fcl_dtu_inst_vld_e;
|
fcl_dtu_inst_vld_e;
|
|
|
dff #(1) tcrm_ff(.din (wrt_tcr_qual_e),
|
dff_s #(1) tcrm_ff(.din (wrt_tcr_qual_e),
|
.clk (clk),
|
.clk (clk),
|
.q (wrt_tcr_m),
|
.q (wrt_tcr_m),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff #(1) tcrw_ff(.din (wrt_tcr_m),
|
dff_s #(1) tcrw_ff(.din (wrt_tcr_m),
|
.clk (clk),
|
.clk (clk),
|
.q (dec_swl_wrt_tcr_w),
|
.q (dec_swl_wrt_tcr_w),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// FPRS write
|
// FPRS write
|
assign wrt_fprs_d = arith_inst & fcl_dtu_inst_vld_d &
|
assign wrt_fprs_d = arith_inst & fcl_dtu_inst_vld_d &
|
op3_hi[3] & op3_lo[0] & rd_06;
|
op3_hi[3] & op3_lo[0] & rd_06;
|
dff #(1) fprse_ff(.din (wrt_fprs_d),
|
dff_s #(1) fprse_ff(.din (wrt_fprs_d),
|
.clk (clk),
|
.clk (clk),
|
.q (wrt_fprs_e),
|
.q (wrt_fprs_e),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
assign wrt_fprs_qual_e = wrt_fprs_e & (~dtu_inst_anull_e) &
|
assign wrt_fprs_qual_e = wrt_fprs_e & (~dtu_inst_anull_e) &
|
fcl_dtu_inst_vld_e;
|
fcl_dtu_inst_vld_e;
|
dff #(1) fprsm_ff(.din (wrt_fprs_qual_e),
|
dff_s #(1) fprsm_ff(.din (wrt_fprs_qual_e),
|
.clk (clk),
|
.clk (clk),
|
.q (wrt_fprs_m),
|
.q (wrt_fprs_m),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
dff #(1) fprsw_ff(.din (wrt_fprs_m),
|
dff_s #(1) fprsw_ff(.din (wrt_fprs_m),
|
.clk (clk),
|
.clk (clk),
|
.q (dec_swl_wrtfprs_w),
|
.q (dec_swl_wrtfprs_w),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
//----------------
|
//----------------
|
// RF/RML Controls
|
// RF/RML Controls
|
//----------------
|
//----------------
|
// Reg Valid Signals for doing ECC
|
// Reg Valid Signals for doing ECC
|
| Line 1049... |
Line 1054... |
fcl_dtu_inst_vld_d;
|
fcl_dtu_inst_vld_d;
|
assign restored_d = arith_inst & op3_hi[3] & op3_lo[1] & dtu_inst_d[25] &
|
assign restored_d = arith_inst & op3_hi[3] & op3_lo[1] & dtu_inst_d[25] &
|
fcl_dtu_inst_vld_d;
|
fcl_dtu_inst_vld_d;
|
assign flushw_d = arith_inst & op3_hi[2] & op3_lo[11] & fcl_dtu_inst_vld_d;
|
assign flushw_d = arith_inst & op3_hi[2] & op3_lo[11] & fcl_dtu_inst_vld_d;
|
|
|
dff #(1) savd_ff(.din (saved_d),
|
dff_s #(1) savd_ff(.din (saved_d),
|
.clk (clk),
|
.clk (clk),
|
.q (ifu_exu_saved_e),
|
.q (ifu_exu_saved_e),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
dff #(1) restd_ff(.din (restored_d),
|
dff_s #(1) restd_ff(.din (restored_d),
|
.clk (clk),
|
.clk (clk),
|
.q (ifu_exu_restored_e),
|
.q (ifu_exu_restored_e),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
dff #(1) flushw_ff(.din (flushw_d),
|
dff_s #(1) flushw_ff(.din (flushw_d),
|
.clk (clk),
|
.clk (clk),
|
.q (ifu_exu_flushw_e),
|
.q (ifu_exu_flushw_e),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
//-----------------------
|
//-----------------------
|
// TLU Controls and Traps
|
// TLU Controls and Traps
|
//-----------------------
|
//-----------------------
|
// Done/Retry
|
// Done/Retry
|
| Line 1082... |
Line 1087... |
//bug 6484 - flag sir instrn. to tlu only in hpriv mode
|
//bug 6484 - flag sir instrn. to tlu only in hpriv mode
|
// assign flag_sir_d = sir_inst_d & (fcl_dtu_privmode_d | fcl_dtu_hprivmode_d);
|
// assign flag_sir_d = sir_inst_d & (fcl_dtu_privmode_d | fcl_dtu_hprivmode_d);
|
|
|
assign flag_sir_d = sir_inst_d & fcl_dtu_hprivmode_d;
|
assign flag_sir_d = sir_inst_d & fcl_dtu_hprivmode_d;
|
|
|
dff #(1) sire_ff(.din (flag_sir_d),
|
dff_s #(1) sire_ff(.din (flag_sir_d),
|
.q (sir_inst_e),
|
.q (sir_inst_e),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
assign dtu_fcl_sir_inst_e = sir_inst_e;
|
assign dtu_fcl_sir_inst_e = sir_inst_e;
|
|
|
//bug 6484 - kill sir instrn. to tlu if bits other than opcode bits cause illegal instrn.
|
//bug 6484 - kill sir instrn. to tlu if bits other than opcode bits cause illegal instrn.
|
// assign flag_sir_e = sir_inst_e & fcl_dtu_inst_vld_e & ~dtu_inst_anull_e;
|
// assign flag_sir_e = sir_inst_e & fcl_dtu_inst_vld_e & ~dtu_inst_anull_e;
|
|
|
assign flag_sir_e = sir_inst_e & fcl_dtu_inst_vld_e & ~dtu_inst_anull_e & ~ill_inst_e;
|
assign flag_sir_e = sir_inst_e & fcl_dtu_inst_vld_e & ~dtu_inst_anull_e & ~ill_inst_e;
|
|
|
dff #(1) sirm_ff(.din (flag_sir_e),
|
dff_s #(1) sirm_ff(.din (flag_sir_e),
|
.q (ifu_tlu_sir_inst_m),
|
.q (ifu_tlu_sir_inst_m),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
|
|
// Privileged opcode trap
|
// Privileged opcode trap
|
assign fcn0 = ~rd[4] & ~rd[3] & ~rd[2] & ~rd[1];
|
assign fcn0 = ~rd[4] & ~rd[3] & ~rd[2] & ~rd[1];
|
|
|
| Line 1147... |
Line 1152... |
op3_hi[3] & op3_lo[0] &
|
op3_hi[3] & op3_lo[0] &
|
(rd_04 | rd_18) & fcl_dtu_privmode_d | // wrsr s/tick
|
(rd_04 | rd_18) & fcl_dtu_privmode_d | // wrsr s/tick
|
op3_hi[3] & op3_lo[2] &
|
op3_hi[3] & op3_lo[2] &
|
rd_04 & fcl_dtu_privmode_d); // wrpr
|
rd_04 & fcl_dtu_privmode_d); // wrpr
|
|
|
dff #(1) prope_ff(.din (privop_d),
|
dff_s #(1) prope_ff(.din (privop_d),
|
.q (privop_e),
|
.q (privop_e),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff #(1) hprope_ff(.din (hprivop_d),
|
dff_s #(1) hprope_ff(.din (hprivop_d),
|
.q (hprivop_e),
|
.q (hprivop_e),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
assign dtu_fcl_privop_e = privop_e & ~hprivop_e;
|
assign dtu_fcl_privop_e = privop_e & ~hprivop_e;
|
// assign dtu_fcl_hprivop_e = hprivop_e & ~dtu_inst_anull_e;
|
// assign dtu_fcl_hprivop_e = hprivop_e & ~dtu_inst_anull_e;
|
|
|
// Illegal Instruction Trap
|
// Illegal Instruction Trap
|
// when they are accessed.
|
// when they are accessed.
|
| Line 1304... |
Line 1309... |
op3[5] & op3_lo[5] & ~fcn0 | // stfsr
|
op3[5] & op3_lo[5] & ~fcn0 | // stfsr
|
~op3[5] & op3_lo[7] & rd[0]) | // std w/ odd rd
|
~op3[5] & op3_lo[7] & rd[0]) | // std w/ odd rd
|
inv_reg_access_d |
|
inv_reg_access_d |
|
rsvchk_fail_d);
|
rsvchk_fail_d);
|
|
|
dff #(1) illinste_ff(.din (ill_inst_d),
|
dff_s #(1) illinste_ff(.din (ill_inst_d),
|
.q (ill_inst_e),
|
.q (ill_inst_e),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
assign dtu_fcl_illinst_e = (ill_inst_e |
|
assign dtu_fcl_illinst_e = (ill_inst_e |
|
// imask_hit_e |
|
// imask_hit_e |
|
hprivop_e);
|
hprivop_e);
|
|
|
|
|
| Line 1396... |
Line 1401... |
assign mb_inst_d = arith_inst & op3_hi[2] & op3_lo[8] &
|
assign mb_inst_d = arith_inst & op3_hi[2] & op3_lo[8] &
|
rs1_0f & rd_00 & fcl_dtu_inst_vld_d &
|
rs1_0f & rd_00 & fcl_dtu_inst_vld_d &
|
dtu_inst_d[13] & mb_mask_d;
|
dtu_inst_d[13] & mb_mask_d;
|
|
|
|
|
dff #(3) lstype_reg(.din (lstype_d),
|
dff_s #(3) lstype_reg(.din (lstype_d),
|
.clk (clk),
|
.clk (clk),
|
.q (lstype_e),
|
.q (lstype_e),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
dff #(2) lssize_reg(.din (lssize_d),
|
dff_s #(2) lssize_reg(.din (lssize_d),
|
.clk (clk),
|
.clk (clk),
|
.q (ifu_lsu_ldst_size_e),
|
.q (ifu_lsu_ldst_size_e),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
dff #(1) lsfp_reg(.din (ldst_fp_d),
|
dff_s #(1) lsfp_reg(.din (ldst_fp_d),
|
.clk (clk),
|
.clk (clk),
|
.q (ifu_lsu_ldst_fp_e),
|
.q (ifu_lsu_ldst_fp_e),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
dff #(1) lsdbl_reg(.din (ldst_dbl_d),
|
dff_s #(1) lsdbl_reg(.din (ldst_dbl_d),
|
.clk (clk),
|
.clk (clk),
|
.q (ifu_lsu_ldst_dbl_e),
|
.q (ifu_lsu_ldst_dbl_e),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff #(1) sext_reg(.din(sext_d),
|
dff_s #(1) sext_reg(.din(sext_d),
|
.clk(clk),
|
.clk(clk),
|
.q(ifu_lsu_sign_ext_e),
|
.q(ifu_lsu_sign_ext_e),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff #(1) casa_reg(.din(casa_d),
|
dff_s #(1) casa_reg(.din(casa_d),
|
.clk(clk),
|
.clk(clk),
|
.q(casa_e),
|
.q(casa_e),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff #(1) ldstub_reg(.din(ldstub_d),
|
dff_s #(1) ldstub_reg(.din(ldstub_d),
|
.clk(clk),
|
.clk(clk),
|
.q(ifu_lsu_ldstub_e),
|
.q(ifu_lsu_ldstub_e),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff #(1) swap_reg(.din(swap_d),
|
dff_s #(1) swap_reg(.din(swap_d),
|
.clk(clk),
|
.clk(clk),
|
.q(ifu_lsu_swap_e),
|
.q(ifu_lsu_swap_e),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff #(1) pfe_ff(.din (prefetch_d),
|
dff_s #(1) pfe_ff(.din (prefetch_d),
|
.q (prefetch_e),
|
.q (prefetch_e),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff #(1) mb_ff(.din (mb_inst_d),
|
dff_s #(1) mb_ff(.din (mb_inst_d),
|
.q (mb_inst_e),
|
.q (mb_inst_e),
|
.clk (clk),
|
.clk (clk),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign ifu_lsu_casa_e = casa_e;
|
assign ifu_lsu_casa_e = casa_e;
|
assign ifu_exu_casa_d = casa_d;
|
assign ifu_exu_casa_d = casa_d;
|
|
|
// assign ifu_lsu_ld_inst_e = lstype_e[0] & (~dtu_inst_anull_e) &
|
// assign ifu_lsu_ld_inst_e = lstype_e[0] & (~dtu_inst_anull_e) &
|
| Line 1487... |
Line 1492... |
(rd_hit | ~erb_dtu_imask[37]) &
|
(rd_hit | ~erb_dtu_imask[37]) &
|
(op_hit | ~erb_dtu_imask[38]) &
|
(op_hit | ~erb_dtu_imask[38]) &
|
(|erb_dtu_imask[38:32]) &
|
(|erb_dtu_imask[38:32]) &
|
fcl_dtu_inst_vld_d;
|
fcl_dtu_inst_vld_d;
|
|
|
dff #(1) imsk_ff(.din (imask_hit),
|
dff_s #(1) imsk_ff(.din (imask_hit),
|
.q (imask_hit_e),
|
.q (imask_hit_e),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
assign dtu_fcl_imask_hit_e = imask_hit_e & swl_dec_ibe_e;
|
assign dtu_fcl_imask_hit_e = imask_hit_e & swl_dec_ibe_e;
|
|
|
|
|
//-------------
|
//-------------
|
// SPU Controls
|
// SPU Controls
|
| Line 1505... |
Line 1510... |
// ~dtu_inst_d[13] & ~dtu_inst_d[12];
|
// ~dtu_inst_d[13] & ~dtu_inst_d[12];
|
//
|
//
|
// dff #(1) scpy_ff (.din (scpy_inst_d),
|
// dff #(1) scpy_ff (.din (scpy_inst_d),
|
// .clk (clk),
|
// .clk (clk),
|
// .q (scpy_inst_e),
|
// .q (scpy_inst_e),
|
// .se (se), .si(), .so());
|
// .se (se), `SIMPLY_RISC_SCANIN, .so());
|
//
|
//
|
// assign ifu_spu_scpy_inst_e = scpy_inst_e & ~dtu_inst_anull_e &
|
// assign ifu_spu_scpy_inst_e = scpy_inst_e & ~dtu_inst_anull_e &
|
// fcl_dtu_inst_vld_e;
|
// fcl_dtu_inst_vld_e;
|
//
|
//
|
// dff #(1) scmp_ff (.din (scmp_inst_d),
|
// dff #(1) scmp_ff (.din (scmp_inst_d),
|
// .q (scmp_inst_e),
|
// .q (scmp_inst_e),
|
// .clk (clk), .se (se), .si(), .so());
|
// .clk (clk), .se (se), `SIMPLY_RISC_SCANIN, .so());
|
//
|
//
|
// assign ifu_spu_scmp_inst_e = scmp_inst_e & ~dtu_inst_anull_e &
|
// assign ifu_spu_scmp_inst_e = scmp_inst_e & ~dtu_inst_anull_e &
|
// fcl_dtu_inst_vld_e;
|
// fcl_dtu_inst_vld_e;
|
//
|
//
|
//
|
//
|
