| Line 16... |
Line 16... |
// You should have received a copy of the GNU General Public
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
|
// License along with this work; if not, write to the Free Software
|
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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//
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// ========== Copyright Header End ============================================
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// ========== Copyright Header End ============================================
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`ifdef SIMPLY_RISC_TWEAKS
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`define SIMPLY_RISC_SCANIN .si(0)
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`else
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`define SIMPLY_RISC_SCANIN .si()
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`endif
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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/*
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/*
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// Module Name: sparc_ifu_errctl
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// Module Name: sparc_ifu_errctl
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*/
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*/
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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// Global header file includes
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// Global header file includes
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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/*
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`include "lsu.h"
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/* ========== Copyright Header Begin ==========================================
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*
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* OpenSPARC T1 Processor File: lsu.h
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* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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*
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* The above named program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public
|
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* License version 2 as published by the Free Software Foundation.
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*
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* The above named program is distributed in the hope that it will be
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* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public
|
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* License along with this work; if not, write to the Free Software
|
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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*
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* ========== Copyright Header End ============================================
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*/
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//`define STB_PCX_WY_HI 107
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//`define STB_PCX_WY_LO 106
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// TLB Tag and Data Format
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// I-TLB version - lsu_tlb only.
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// Invalidate Format
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//addr<5:4>=00
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//addr<5:4>=01
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//addr<5:4>=10
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//addr<5:4>=11
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// cpuid - 4b
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// CPUany, addr<5:4>=00,10
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// CPUany, addr<5:4>=01,11
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// CPUany, addr<5:4>=01,11
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// DTAG parity error Invalidate
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// CPX BINIT STORE
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module sparc_ifu_errctl(/*AUTOARG*/
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module sparc_ifu_errctl(/*AUTOARG*/
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// Outputs
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// Outputs
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erc_erd_pgsz_b0, erc_erd_pgsz_b1, ifu_lsu_asi_rd_unc,
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erc_erd_pgsz_b0, erc_erd_pgsz_b1, ifu_lsu_asi_rd_unc,
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ifu_lsu_ldxa_tid_w2, ifu_lsu_ldxa_data_vld_w2,
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ifu_lsu_ldxa_tid_w2, ifu_lsu_ldxa_data_vld_w2,
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| Line 798... |
Line 502... |
assign clk = rclk;
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assign clk = rclk;
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// reset buffer
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// reset buffer
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dffrl_async rstff(.din (grst_l),
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dffrl_async rstff(.din (grst_l),
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.q (erb_reset_l),
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.q (erb_reset_l),
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.clk (clk), .se(se), .si(), .so(),
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.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so(),
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.rst_l (arst_l));
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.rst_l (arst_l));
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assign erb_reset = ~erb_reset_l;
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assign erb_reset = ~erb_reset_l;
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| Line 820... |
Line 524... |
// default to tte_lock_d1 = 0
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// default to tte_lock_d1 = 0
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// 05/30/03: tlb correctible errors disabled.
|
// 05/30/03: tlb correctible errors disabled.
|
// so treat as if lock = 1 and force ue.
|
// so treat as if lock = 1 and force ue.
|
// dff #(1) lk_ff(.din (erd_erc_tte_lock_s1),
|
// dff #(1) lk_ff(.din (erd_erc_tte_lock_s1),
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// .q (tte_lock_d1),
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// .q (tte_lock_d1),
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// .clk (clk), .se(se), .si(), .so());
|
// .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
//-----------------------
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//-----------------------
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// Basic pipeline signals
|
// Basic pipeline signals
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//-----------------------
|
//-----------------------
|
// thr_s1 also contains asi tid
|
// thr_s1 also contains asi tid
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dff #(2) tidd_reg(.din (ifu_lsu_thrid_s),
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dff_s #(2) tidd_reg(.din (ifu_lsu_thrid_s),
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.q (tid_d),
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.q (tid_d),
|
.clk (clk), .se(se), .si(), .so());
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.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
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assign thr_d[0] = ~tid_d[1] & ~tid_d[0];
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assign thr_d[0] = ~tid_d[1] & ~tid_d[0];
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assign thr_d[1] = ~tid_d[1] & tid_d[0];
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assign thr_d[1] = ~tid_d[1] & tid_d[0];
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assign thr_d[2] = tid_d[1] & ~tid_d[0];
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assign thr_d[2] = tid_d[1] & ~tid_d[0];
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assign thr_d[3] = tid_d[1] & tid_d[0];
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assign thr_d[3] = tid_d[1] & tid_d[0];
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dff #(4) thre_reg(.din (thr_d),
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dff_s #(4) thre_reg(.din (thr_d),
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.q (thr_e),
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.q (thr_e),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
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assign thr_d1 = thr_e;
|
assign thr_d1 = thr_e;
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dff #(4) thrm_reg(.din (thr_e),
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dff_s #(4) thrm_reg(.din (thr_e),
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.q (thr_m),
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.q (thr_m),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
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dff #(4) thrw_reg(.din (thr_m),
|
dff_s #(4) thrw_reg(.din (thr_m),
|
.q (thr_w),
|
.q (thr_w),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
|
|
//-----------------------------
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//-----------------------------
|
// lsu flops (added for timing)
|
// lsu flops (added for timing)
|
//-----------------------------
|
//-----------------------------
|
// all the lsu signals go to the final mux in the errdp, to help
|
// all the lsu signals go to the final mux in the errdp, to help
|
// with timing. This is no longer necessary, in fact it is no
|
// with timing. This is no longer necessary, in fact it is no
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// longer desired, since we have added the flop below to stage all
|
// longer desired, since we have added the flop below to stage all
|
// the lsu signals. However, the design is not changed, to save
|
// the lsu signals. However, the design is not changed, to save
|
// the extra effort in physical composition to rip up the errdp.
|
// the extra effort in physical composition to rip up the errdp.
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dff #(10) lspipe_reg(.din ({lsu_ifu_dtlb_data_su,
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dff_s #(10) lspipe_reg(.din ({lsu_ifu_dtlb_data_su,
|
lsu_ifu_dtlb_data_ue,
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lsu_ifu_dtlb_data_ue,
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lsu_ifu_dtlb_tag_ue,
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lsu_ifu_dtlb_tag_ue,
|
lsu_ifu_dcache_data_perror,
|
lsu_ifu_dcache_data_perror,
|
lsu_ifu_dcache_tag_perror,
|
lsu_ifu_dcache_tag_perror,
|
lsu_ifu_l2_unc_error,
|
lsu_ifu_l2_unc_error,
|
| Line 874... |
Line 578... |
lsu_dcache_tag_perror,
|
lsu_dcache_tag_perror,
|
lsu_l2_unc_error,
|
lsu_l2_unc_error,
|
lsu_l2_corr_error,
|
lsu_l2_corr_error,
|
lsu_io_error,
|
lsu_io_error,
|
lsu_error_tid[1:0]}),
|
lsu_error_tid[1:0]}),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign any_priv_state = tlu_lsu_pstate_priv | tlu_hpstate_priv;
|
assign any_priv_state = tlu_lsu_pstate_priv | tlu_hpstate_priv;
|
|
|
//Bug 6821: added so that lsu ue's errors pickup the delayed priv level
|
//Bug 6821: added so that lsu ue's errors pickup the delayed priv level
|
dff #(4) lsu_priv_reg(.din (any_priv_state),
|
dff_s #(4) lsu_priv_reg(.din (any_priv_state),
|
.q (any_lsu_ue_priv_state),
|
.q (any_lsu_ue_priv_state),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// thread from lsu
|
// thread from lsu
|
assign thr_lsu_err[0] = ~lsu_error_tid[1] & ~lsu_error_tid[0];
|
assign thr_lsu_err[0] = ~lsu_error_tid[1] & ~lsu_error_tid[0];
|
assign thr_lsu_err[1] = ~lsu_error_tid[1] & lsu_error_tid[0];
|
assign thr_lsu_err[1] = ~lsu_error_tid[1] & lsu_error_tid[0];
|
assign thr_lsu_err[2] = lsu_error_tid[1] & ~lsu_error_tid[0];
|
assign thr_lsu_err[2] = lsu_error_tid[1] & ~lsu_error_tid[0];
|
assign thr_lsu_err[3] = lsu_error_tid[1] & lsu_error_tid[0];
|
assign thr_lsu_err[3] = lsu_error_tid[1] & lsu_error_tid[0];
|
|
|
// thread from spu
|
// thread from spu
|
// From Farnad: tid is ready several cycles before everything else.
|
// From Farnad: tid is ready several cycles before everything else.
|
// In the ifu, I will assume 1 cycle before
|
// In the ifu, I will assume 1 cycle before
|
dff #(2) sptid_reg(.din (spu_ifu_ttype_tid_w2),
|
dff_s #(2) sptid_reg(.din (spu_ifu_ttype_tid_w2),
|
.q (spu_tid_w2),
|
.q (spu_tid_w2),
|
.clk (clk), .se(se), .so(), .si());
|
.clk (clk), .se(se), .so(), `SIMPLY_RISC_SCANIN);
|
|
|
dff #(2) spe1_reg(.din ({spu_ifu_unc_err_w1,
|
dff_s #(2) spe1_reg(.din ({spu_ifu_unc_err_w1,
|
spu_ifu_mamem_err_w1}),
|
spu_ifu_mamem_err_w1}),
|
.q ({spu_unc_err_w2,
|
.q ({spu_unc_err_w2,
|
spu_mamem_err_w2}),
|
spu_mamem_err_w2}),
|
.clk (clk), .se(se), .so(), .si());
|
.clk (clk), .se(se), .so(), `SIMPLY_RISC_SCANIN);
|
|
|
assign thr_spu_err[0] = ~spu_tid_w2[1] & ~spu_tid_w2[0];
|
assign thr_spu_err[0] = ~spu_tid_w2[1] & ~spu_tid_w2[0];
|
assign thr_spu_err[1] = ~spu_tid_w2[1] & spu_tid_w2[0];
|
assign thr_spu_err[1] = ~spu_tid_w2[1] & spu_tid_w2[0];
|
assign thr_spu_err[2] = spu_tid_w2[1] & ~spu_tid_w2[0];
|
assign thr_spu_err[2] = spu_tid_w2[1] & ~spu_tid_w2[0];
|
assign thr_spu_err[3] = spu_tid_w2[1] & spu_tid_w2[0];
|
assign thr_spu_err[3] = spu_tid_w2[1] & spu_tid_w2[0];
|
|
|
// thread from ifq
|
// thread from ifq
|
dff #(2) ifqthr_reg(.din (ifq_erb_l2err_tid),
|
dff_s #(2) ifqthr_reg(.din (ifq_erb_l2err_tid),
|
.q (l2ierr_tid),
|
.q (l2ierr_tid),
|
.clk (clk), .se(se), .so(), .si());
|
.clk (clk), .se(se), .so(), `SIMPLY_RISC_SCANIN);
|
|
|
assign thr_l2ie[0] = ~l2ierr_tid[1] & ~l2ierr_tid[0];
|
assign thr_l2ie[0] = ~l2ierr_tid[1] & ~l2ierr_tid[0];
|
assign thr_l2ie[1] = ~l2ierr_tid[1] & l2ierr_tid[0];
|
assign thr_l2ie[1] = ~l2ierr_tid[1] & l2ierr_tid[0];
|
assign thr_l2ie[2] = l2ierr_tid[1] & ~l2ierr_tid[0];
|
assign thr_l2ie[2] = l2ierr_tid[1] & ~l2ierr_tid[0];
|
assign thr_l2ie[3] = l2ierr_tid[1] & l2ierr_tid[0];
|
assign thr_l2ie[3] = l2ierr_tid[1] & l2ierr_tid[0];
|
| Line 925... |
Line 629... |
//---------------------------------------
|
//---------------------------------------
|
// itlb inst fetch errors
|
// itlb inst fetch errors
|
assign itlb_feterr_s1 = (erd_erc_tlbd_pe_s1[0] ^ erd_erc_tlbd_pe_s1[1]) &
|
assign itlb_feterr_s1 = (erd_erc_tlbd_pe_s1[0] ^ erd_erc_tlbd_pe_s1[1]) &
|
fcl_erb_immuevld_s1;
|
fcl_erb_immuevld_s1;
|
assign erb_ifq_itlberr_s1 = itlb_feterr_s1 & nceen_d;
|
assign erb_ifq_itlberr_s1 = itlb_feterr_s1 & nceen_d;
|
dff #(1) itfete_ff(.din (itlb_feterr_s1),
|
dff_s #(1) itfete_ff(.din (itlb_feterr_s1),
|
.q (tlb_feterr_d1),
|
.q (tlb_feterr_d1),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign itlb_errtr_s1_l = ~erb_ifq_itlberr_s1;
|
assign itlb_errtr_s1_l = ~erb_ifq_itlberr_s1;
|
dff #(1) itume_ff(.din (itlb_errtr_s1_l),
|
dff_s #(1) itume_ff(.din (itlb_errtr_s1_l),
|
.q (itlb_errtr_d1_l),
|
.q (itlb_errtr_d1_l),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// assign tlb_fet_ce_d1 = tlb_feterr_d1 & ~tte_lock_d1;
|
// assign tlb_fet_ce_d1 = tlb_feterr_d1 & ~tte_lock_d1;
|
// assign tlb_fet_ue_d1 = tlb_feterr_d1 & tte_lock_d1;
|
// assign tlb_fet_ue_d1 = tlb_feterr_d1 & tte_lock_d1;
|
assign tlb_fet_ce_d1 = 1'b0;
|
assign tlb_fet_ce_d1 = 1'b0;
|
assign tlb_fet_ue_d1 = tlb_feterr_d1;
|
assign tlb_fet_ue_d1 = tlb_feterr_d1;
|
| Line 945... |
Line 649... |
// instruction errors
|
// instruction errors
|
// assign insterr_s1 = (erd_erc_nirpe_s1 | erd_erc_fetpe_s1) &
|
// assign insterr_s1 = (erd_erc_nirpe_s1 | erd_erc_fetpe_s1) &
|
// fcl_erb_ievld_s1;
|
// fcl_erb_ievld_s1;
|
// dff #(1) inserr_ff(.din (insterr_s1),
|
// dff #(1) inserr_ff(.din (insterr_s1),
|
// .q (insterr_d1),
|
// .q (insterr_d1),
|
// .clk (clk), .se(se), .si(), .so());
|
// .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign insterr_s1 = (erd_erc_fetpe_s1 | erd_erc_nirpe_s1) &
|
assign insterr_s1 = (erd_erc_fetpe_s1 | erd_erc_nirpe_s1) &
|
fcl_erb_ievld_s1;
|
fcl_erb_ievld_s1;
|
|
|
dff #(1) feterr_ff(.din (insterr_s1),
|
dff_s #(1) feterr_ff(.din (insterr_s1),
|
.q (insterr_d1),
|
.q (insterr_d1),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
// dff #(1) nirerr_ff(.din (erd_erc_nirpe_s1),
|
// dff #(1) nirerr_ff(.din (erd_erc_nirpe_s1),
|
// .q (nirpe_d1),
|
// .q (nirpe_d1),
|
// .clk (clk), .se(se), .si(), .so());
|
// .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
// dff #(1) ievld1_ff(.din (fcl_erb_ievld_s1),
|
// dff #(1) ievld1_ff(.din (fcl_erb_ievld_s1),
|
// .q (ievld_d1),
|
// .q (ievld_d1),
|
// .clk (clk), .se(se), .si(), .so());
|
// .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign insterr_qual_d1 = insterr_d1 & ~tlb_feterr_d1;
|
assign insterr_qual_d1 = insterr_d1 & ~tlb_feterr_d1;
|
|
|
// tag errors
|
// tag errors
|
dff #(4) vld_reg(.din (icv_itlb_valid_f),
|
dff_s #(4) vld_reg(.din (icv_itlb_valid_f),
|
.q (valid_s1),
|
.q (valid_s1),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
assign alltag_err_s1 = erd_erc_tagpe_s1 & valid_s1;
|
assign alltag_err_s1 = erd_erc_tagpe_s1 & valid_s1;
|
|
|
assign ictagerr_s1 = (|alltag_err_s1[3:0]) & fcl_erb_tevld_s1;
|
assign ictagerr_s1 = (|alltag_err_s1[3:0]) & fcl_erb_tevld_s1;
|
dff #(1) itagerr_ff(.din (ictagerr_s1),
|
dff_s #(1) itagerr_ff(.din (ictagerr_s1),
|
.q (ictagerr_d1),
|
.q (ictagerr_d1),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign ictagerr_qual_d1 = ictagerr_d1 & ~insterr_d1 &
|
assign ictagerr_qual_d1 = ictagerr_d1 & ~insterr_d1 &
|
~tlb_feterr_d1;
|
~tlb_feterr_d1;
|
|
|
// Corrective action for IFU errors
|
// Corrective action for IFU errors
|
| Line 1007... |
Line 711... |
assign itlb_tagerr_s1 = (erd_erc_tlbt_pe_s1[0] ^ erd_erc_tlbt_pe_s1[1]) &
|
assign itlb_tagerr_s1 = (erd_erc_tlbt_pe_s1[0] ^ erd_erc_tlbt_pe_s1[1]) &
|
asi_ttevld_s1;
|
asi_ttevld_s1;
|
assign itlb_dataerr_s1 = (erd_erc_tlbd_pe_s1[0] ^ erd_erc_tlbd_pe_s1[1]) &
|
assign itlb_dataerr_s1 = (erd_erc_tlbd_pe_s1[0] ^ erd_erc_tlbd_pe_s1[1]) &
|
asi_tdevld_s1;
|
asi_tdevld_s1;
|
|
|
dff #(1) itdate_ff(.din (itlb_dataerr_s1),
|
dff_s #(1) itdate_ff(.din (itlb_dataerr_s1),
|
.q (asi_daterr_d1),
|
.q (asi_daterr_d1),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff #(1) ittage_ff(.din (itlb_tagerr_s1),
|
dff_s #(1) ittage_ff(.din (itlb_tagerr_s1),
|
.q (asi_tagerr_d1),
|
.q (asi_tagerr_d1),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign asi_rd_err_d1 = asi_daterr_d1 | asi_tagerr_d1;
|
assign asi_rd_err_d1 = asi_daterr_d1 | asi_tagerr_d1;
|
assign ifu_lsu_asi_rd_unc = asi_rd_err_d1;
|
assign ifu_lsu_asi_rd_unc = asi_rd_err_d1;
|
|
|
assign any_tlbasi_err = {4{asi_rd_err_d1}} & asi_thr_w2;
|
assign any_tlbasi_err = {4{asi_rd_err_d1}} & asi_thr_w2;
|
|
|
|
|
//------------------------------
|
//------------------------------
|
// RF errors
|
// RF errors
|
//------------------------------
|
//------------------------------
|
dff #(1) irfu_ff(.din (exu_ifu_ecc_ue_m),
|
dff_s #(1) irfu_ff(.din (exu_ifu_ecc_ue_m),
|
.q (irf_ue_unq),
|
.q (irf_ue_unq),
|
.clk (clk), .se (se), .si(), .so());
|
.clk (clk), .se (se), `SIMPLY_RISC_SCANIN, .so());
|
dff #(1) irfc_ff(.din (exu_ifu_ecc_ce_m),
|
dff_s #(1) irfc_ff(.din (exu_ifu_ecc_ce_m),
|
.q (irf_ce_unq),
|
.q (irf_ce_unq),
|
.clk (clk), .se (se), .si(), .so());
|
.clk (clk), .se (se), `SIMPLY_RISC_SCANIN, .so());
|
assign irf_ce_w = irf_ce_unq & ifu_tlu_inst_vld_w;
|
assign irf_ce_w = irf_ce_unq & ifu_tlu_inst_vld_w;
|
assign irf_ue_w = irf_ue_unq & ifu_tlu_inst_vld_w;
|
assign irf_ue_w = irf_ue_unq & ifu_tlu_inst_vld_w;
|
|
|
//------------------
|
//------------------
|
// Error Logging
|
// Error Logging
|
| Line 1122... |
Line 826... |
// tlb asi read error
|
// tlb asi read error
|
assign imt_nxt = {4{asi_tagerr_d1 & ~erb_reset}} & asi_thr_w2 &
|
assign imt_nxt = {4{asi_tagerr_d1 & ~erb_reset}} & asi_thr_w2 &
|
~any_ue_vld |
|
~any_ue_vld |
|
imt & ~({4{imt_wrt_data}} & asi_wrt_err_stat);
|
imt & ~({4{imt_wrt_data}} & asi_wrt_err_stat);
|
|
|
dff #(2) ffu_err_reg(.din ({ffu_ifu_ecc_ce_w2,
|
dff_s #(2) ffu_err_reg(.din ({ffu_ifu_ecc_ce_w2,
|
ffu_ifu_ecc_ue_w2}),
|
ffu_ifu_ecc_ue_w2}),
|
.q ({ffu_ce_w3,
|
.q ({ffu_ce_w3,
|
ffu_ue_w3}),
|
ffu_ue_w3}),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff #(2) fptid_reg(.din (ffu_ifu_tid_w2[1:0]),
|
dff_s #(2) fptid_reg(.din (ffu_ifu_tid_w2[1:0]),
|
.q (ffu_tid_w3[1:0]),
|
.q (ffu_tid_w3[1:0]),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign ffu_thr_w3[0] = ~ffu_tid_w3[1] & ~ffu_tid_w3[0];
|
assign ffu_thr_w3[0] = ~ffu_tid_w3[1] & ~ffu_tid_w3[0];
|
assign ffu_thr_w3[1] = ~ffu_tid_w3[1] & ffu_tid_w3[0];
|
assign ffu_thr_w3[1] = ~ffu_tid_w3[1] & ffu_tid_w3[0];
|
assign ffu_thr_w3[2] = ffu_tid_w3[1] & ~ffu_tid_w3[0];
|
assign ffu_thr_w3[2] = ffu_tid_w3[1] & ~ffu_tid_w3[0];
|
assign ffu_thr_w3[3] = ffu_tid_w3[1] & ffu_tid_w3[0];
|
assign ffu_thr_w3[3] = ffu_tid_w3[1] & ffu_tid_w3[0];
|
| Line 1184... |
Line 888... |
imdu & ~({4{imdu_wrt_data}} & asi_wrt_err_stat);
|
imdu & ~({4{imdu_wrt_data}} & asi_wrt_err_stat);
|
|
|
// assign imdc_nxt = mov_ely_reg_w & ~any_err_vld & early_imdc |
|
// assign imdc_nxt = mov_ely_reg_w & ~any_err_vld & early_imdc |
|
// imdc & ~({4{imdc_wrt_data}} & asi_wrt_err_stat);
|
// imdc & ~({4{imdc_wrt_data}} & asi_wrt_err_stat);
|
|
|
dff #(64) errvec_reg(.din ({imt_nxt, imdu_nxt, idc_nxt, itc_nxt,
|
dff_s #(64) errvec_reg(.din ({imt_nxt, imdu_nxt, idc_nxt, itc_nxt,
|
iru_nxt, irc_nxt, fru_nxt, frc_nxt,
|
iru_nxt, irc_nxt, fru_nxt, frc_nxt,
|
dmt_nxt, dmdu_nxt, dmsu_nxt, ddc_nxt, dtc_nxt,
|
dmt_nxt, dmdu_nxt, dmsu_nxt, ddc_nxt, dtc_nxt,
|
ldau_nxt, ncu_nxt, mau_nxt}),
|
ldau_nxt, ncu_nxt, mau_nxt}),
|
.q ({imt, imdu, idc, itc,
|
.q ({imt, imdu, idc, itc,
|
iru, irc, fru, frc,
|
iru, irc, fru, frc,
|
dmt, dmdu, dmsu, ddc, dtc,
|
dmt, dmdu, dmsu, ddc, dtc,
|
ldau, ncu, mau}),
|
ldau, ncu, mau}),
|
.clk (clk),
|
.clk (clk),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign any_err_vld = imt | imdu | idc | itc | iru | irc | fru | frc |
|
assign any_err_vld = imt | imdu | idc | itc | iru | irc | fru | frc |
|
dmt | dmdu | dmsu | ddc | dtc | ldau | ncu | mau;
|
dmt | dmdu | dmsu | ddc | dtc | ldau | ncu | mau;
|
|
|
assign any_ue_vld = imt | imdu | iru | fru |
|
assign any_ue_vld = imt | imdu | iru | fru |
|
| Line 1259... |
Line 963... |
assign early_l2ce_nxt = {4{ifq_erb_ifet_ce}} & thr_l2ie &
|
assign early_l2ce_nxt = {4{ifq_erb_ifet_ce}} & thr_l2ie &
|
~any_iferr_vld & ~any_rf_err & ~any_lsu_err |
|
~any_iferr_vld & ~any_rf_err & ~any_lsu_err |
|
early_l2ce & ~clear_iferr_d1 &
|
early_l2ce & ~clear_iferr_d1 &
|
~mov_ely_reg_w;
|
~mov_ely_reg_w;
|
|
|
dffr #(24) elyerr_reg(.din ({early_idc_nxt,
|
dffr_s #(24) elyerr_reg(.din ({early_idc_nxt,
|
early_itc_nxt,
|
early_itc_nxt,
|
early_imdu_nxt,
|
early_imdu_nxt,
|
early_ldau_nxt,
|
early_ldau_nxt,
|
early_ncu_nxt,
|
early_ncu_nxt,
|
early_l2ce_nxt}),
|
early_l2ce_nxt}),
|
| Line 1273... |
Line 977... |
early_ldau,
|
early_ldau,
|
early_ncu,
|
early_ncu,
|
early_l2ce}),
|
early_l2ce}),
|
.clk (clk),
|
.clk (clk),
|
.rst (erb_reset),
|
.rst (erb_reset),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// Multipl errors
|
// Multipl errors
|
assign meu_nxt = any_ue_vld & (any_lsu_ue | any_rf_ue | any_tlbasi_err |
|
assign meu_nxt = any_ue_vld & (any_lsu_ue | any_rf_ue | any_tlbasi_err |
|
any_spu_ue |
|
any_spu_ue |
|
mov_ely_reg_w & ifet_ue_vld) |
|
mov_ely_reg_w & ifet_ue_vld) |
|
| Line 1295... |
Line 999... |
assign priv_nxt = ~any_err_vld & (any_lsu_ue_priv_state & any_lsu_ue |
|
assign priv_nxt = ~any_err_vld & (any_lsu_ue_priv_state & any_lsu_ue |
|
any_priv_state & (any_lsu_ce | any_rf_err | any_tlbasi_err) |
|
any_priv_state & (any_lsu_ce | any_rf_err | any_tlbasi_err) |
|
mov_ely_reg_w & early_priv) |
|
mov_ely_reg_w & early_priv) |
|
priv & ~({4{priv_wrt_data}} & asi_wrt_err_stat);
|
priv & ~({4{priv_wrt_data}} & asi_wrt_err_stat);
|
|
|
dffr #(12) me_reg(.din ({meu_nxt,
|
dffr_s #(12) me_reg(.din ({meu_nxt,
|
mec_nxt,
|
mec_nxt,
|
priv_nxt}),
|
priv_nxt}),
|
.q ({meu,
|
.q ({meu,
|
mec,
|
mec,
|
priv}),
|
priv}),
|
.clk (clk),
|
.clk (clk),
|
.rst (erb_reset),
|
.rst (erb_reset),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// Early multiple errors
|
// Early multiple errors
|
assign early_meu_nxt = any_ifu_ue & ifet_ue_vld |
|
assign early_meu_nxt = any_ifu_ue & ifet_ue_vld |
|
early_meu & ~clear_iferr_d1 & ~mov_ely_reg_w;
|
early_meu & ~clear_iferr_d1 & ~mov_ely_reg_w;
|
|
|
| Line 1316... |
Line 1020... |
|
|
// bug 6155 & 6821
|
// bug 6155 & 6821
|
assign early_priv_nxt = any_priv_state & ~any_iferr_vld & ~any_rf_err & ~any_lsu_err & any_ifu_err |
|
assign early_priv_nxt = any_priv_state & ~any_iferr_vld & ~any_rf_err & ~any_lsu_err & any_ifu_err |
|
early_priv & ~clear_iferr_d1 & ~mov_ely_reg_w;
|
early_priv & ~clear_iferr_d1 & ~mov_ely_reg_w;
|
|
|
dffr #(12) elyme_reg(.din ({early_meu_nxt,
|
dffr_s #(12) elyme_reg(.din ({early_meu_nxt,
|
early_mec_nxt,
|
early_mec_nxt,
|
early_priv_nxt}),
|
early_priv_nxt}),
|
.q ({early_meu,
|
.q ({early_meu,
|
early_mec,
|
early_mec,
|
early_priv}),
|
early_priv}),
|
.clk (clk),
|
.clk (clk),
|
.rst (erb_reset),
|
.rst (erb_reset),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// pipeline progress
|
// pipeline progress
|
dff #(1) clre_ff(.din (fcl_erb_inst_issue_d),
|
dff_s #(1) clre_ff(.din (fcl_erb_inst_issue_d),
|
.q (clr_elyff_e),
|
.q (clr_elyff_e),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
assign early_err_vec_e = (any_iferr_vld | early_l2ce) & thr_e;
|
assign early_err_vec_e = (any_iferr_vld | early_l2ce) & thr_e;
|
assign clr_err_qual_e = (|early_err_vec_e[3:0]) & clr_elyff_e;
|
assign clr_err_qual_e = (|early_err_vec_e[3:0]) & clr_elyff_e;
|
|
|
dff #(1) clrm_ff(.din (clr_err_qual_e),
|
dff_s #(1) clrm_ff(.din (clr_err_qual_e),
|
.q (clr_elyff_m),
|
.q (clr_elyff_m),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff #(1) clrw_ff(.din (clr_elyff_m),
|
dff_s #(1) clrw_ff(.din (clr_elyff_m),
|
.q (clr_elyff_w),
|
.q (clr_elyff_w),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// fix for 6142 and 6159
|
// fix for 6142 and 6159
|
// delay err reg clear by one cycle to prevent clearing your own errors
|
// delay err reg clear by one cycle to prevent clearing your own errors
|
dff #(4) clree_reg(.din (fcl_erb_clear_iferr),
|
dff_s #(4) clree_reg(.din (fcl_erb_clear_iferr),
|
.q (clear_iferr_d1),
|
.q (clear_iferr_d1),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
|
|
assign clear_ely_reg_w = {4{clr_elyff_w}} & thr_w &
|
assign clear_ely_reg_w = {4{clr_elyff_w}} & thr_w &
|
(any_iferr_vld | early_l2ce); // why again?
|
(any_iferr_vld | early_l2ce); // why again?
|
assign mov_ely_reg_w = clear_ely_reg_w &
|
assign mov_ely_reg_w = clear_ely_reg_w &
|
| Line 1478... |
Line 1182... |
~asi_wrt_err_en & nceen;
|
~asi_wrt_err_en & nceen;
|
|
|
assign ceen_nxt = asi_wrt_err_en & {4{ceen_wrt_data}} |
|
assign ceen_nxt = asi_wrt_err_en & {4{ceen_wrt_data}} |
|
~asi_wrt_err_en & ceen;
|
~asi_wrt_err_en & ceen;
|
|
|
dffr #(8) err_en_reg(.din ({nceen_nxt, ceen_nxt}),
|
dffr_s #(8) err_en_reg(.din ({nceen_nxt, ceen_nxt}),
|
.q ({nceen, ceen}),
|
.q ({nceen, ceen}),
|
.rst (erb_reset),
|
.rst (erb_reset),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign nceen_d = (thr_d[0] & nceen[0] |
|
assign nceen_d = (thr_d[0] & nceen[0] |
|
thr_d[1] & nceen[1] |
|
thr_d[1] & nceen[1] |
|
thr_d[2] & nceen[2] |
|
thr_d[2] & nceen[2] |
|
thr_d[3] & nceen[3]);
|
thr_d[3] & nceen[3]);
|
|
|
dff #(1) nce_ff(.din (nceen_d),
|
dff_s #(1) nce_ff(.din (nceen_d),
|
.q (ifu_exu_nceen_e),
|
.q (ifu_exu_nceen_e),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign ifu_lsu_nceen = nceen;
|
assign ifu_lsu_nceen = nceen;
|
assign ifu_spu_nceen = nceen;
|
assign ifu_spu_nceen = nceen;
|
|
|
assign ifu_ce_trap = mov_ely_reg_w & ifet_ce_vld;
|
assign ifu_ce_trap = mov_ely_reg_w & ifet_ce_vld;
|
| Line 1502... |
Line 1206... |
any_rf_ce |
|
any_rf_ce |
|
{4{ifq_erb_ce_rep}} & thr_l2ie |
|
{4{ifq_erb_ce_rep}} & thr_l2ie |
|
any_spu_ce |
|
any_spu_ce |
|
any_lsu_ce) & ceen;
|
any_lsu_ce) & ceen;
|
|
|
dff #(4) ceint_reg(.din (ce_trapvec),
|
dff_s #(4) ceint_reg(.din (ce_trapvec),
|
.q (erb_fcl_ce_trapvec),
|
.q (erb_fcl_ce_trapvec),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign ue_trapvec = ({4{ifq_erb_ue_rep}} & thr_l2ie |
|
assign ue_trapvec = ({4{ifq_erb_ue_rep}} & thr_l2ie |
|
any_spu_ue & {4{spu_ifu_int_w2}}) & nceen;
|
any_spu_ue & {4{spu_ifu_int_w2}}) & nceen;
|
|
|
assign erb_fcl_spu_uetrap = any_spu_ue & nceen;
|
assign erb_fcl_spu_uetrap = any_spu_ue & nceen;
|
|
|
dff #(4) ueint_reg(.din (ue_trapvec),
|
dff_s #(4) ueint_reg(.din (ue_trapvec),
|
.q (erb_fcl_ue_trapvec),
|
.q (erb_fcl_ue_trapvec),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
|
|
mux4ds #(2) err_en_asi(.dout (erc_erd_erren_asidata),
|
mux4ds #(2) err_en_asi(.dout (erc_erd_erren_asidata),
|
.in0 ({nceen[0], ceen[0]}),
|
.in0 ({nceen[0], ceen[0]}),
|
.in1 ({nceen[1], ceen[1]}),
|
.in1 ({nceen[1], ceen[1]}),
|
| Line 1541... |
Line 1245... |
// correct for single shot
|
// correct for single shot
|
assign errinj_vec_nxt[5:0] = wrt_errinj_i2 ? ifq_erb_asidata_i2[29:24] :
|
assign errinj_vec_nxt[5:0] = wrt_errinj_i2 ? ifq_erb_asidata_i2[29:24] :
|
errinj_ctl[0] ? corr_errinj_vec :
|
errinj_ctl[0] ? corr_errinj_vec :
|
errinj_vec;
|
errinj_vec;
|
|
|
dffr #(16) errinj_reg(.din ({errinj_ctl_nxt,
|
dffr_s #(16) errinj_reg(.din ({errinj_ctl_nxt,
|
errinj_vec_nxt,
|
errinj_vec_nxt,
|
ecc_mask_nxt}),
|
ecc_mask_nxt}),
|
.q ({errinj_ctl,
|
.q ({errinj_ctl,
|
errinj_vec,
|
errinj_vec,
|
ecc_mask}),
|
ecc_mask}),
|
.rst (erb_reset),
|
.rst (erb_reset),
|
.clk (clk), .se (se), .si(), .so());
|
.clk (clk), .se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign ifu_exu_ecc_mask = ecc_mask;
|
assign ifu_exu_ecc_mask = ecc_mask;
|
assign ifu_exu_inj_irferr = errinj_vec[1] & errinj_ctl[1];
|
assign ifu_exu_inj_irferr = errinj_vec[1] & errinj_ctl[1];
|
assign ifu_ffu_inj_frferr = errinj_vec[0] & errinj_ctl[1];
|
assign ifu_ffu_inj_frferr = errinj_vec[0] & errinj_ctl[1];
|
assign ifu_lsu_error_inj[3:0] = errinj_vec[5:2] & {4{errinj_ctl[1]}};
|
assign ifu_lsu_error_inj[3:0] = errinj_vec[5:2] & {4{errinj_ctl[1]}};
|
| Line 1567... |
Line 1271... |
|
|
//--------------------------
|
//--------------------------
|
// ASI Stuff
|
// ASI Stuff
|
//--------------------------
|
//--------------------------
|
|
|
dff #(2) asiways_reg(.din (ifq_erb_asiway_f),
|
dff_s #(2) asiways_reg(.din (ifq_erb_asiway_f),
|
.q (asi_way_s1),
|
.q (asi_way_s1),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign dec_asiway_s1[0] = ~asi_way_s1[1] & ~asi_way_s1[0];
|
assign dec_asiway_s1[0] = ~asi_way_s1[1] & ~asi_way_s1[0];
|
assign dec_asiway_s1[1] = ~asi_way_s1[1] & asi_way_s1[0];
|
assign dec_asiway_s1[1] = ~asi_way_s1[1] & asi_way_s1[0];
|
assign dec_asiway_s1[2] = asi_way_s1[1] & ~asi_way_s1[0];
|
assign dec_asiway_s1[2] = asi_way_s1[1] & ~asi_way_s1[0];
|
assign dec_asiway_s1[3] = asi_way_s1[1] & asi_way_s1[0];
|
assign dec_asiway_s1[3] = asi_way_s1[1] & asi_way_s1[0];
|
| Line 1583... |
Line 1287... |
assign asi_thr_i2[0] = ~ifq_fcl_asi_tid_bf[1] & ~ifq_fcl_asi_tid_bf[0];
|
assign asi_thr_i2[0] = ~ifq_fcl_asi_tid_bf[1] & ~ifq_fcl_asi_tid_bf[0];
|
assign asi_thr_i2[1] = ~ifq_fcl_asi_tid_bf[1] & ifq_fcl_asi_tid_bf[0];
|
assign asi_thr_i2[1] = ~ifq_fcl_asi_tid_bf[1] & ifq_fcl_asi_tid_bf[0];
|
assign asi_thr_i2[2] = ifq_fcl_asi_tid_bf[1] & ~ifq_fcl_asi_tid_bf[0];
|
assign asi_thr_i2[2] = ifq_fcl_asi_tid_bf[1] & ~ifq_fcl_asi_tid_bf[0];
|
assign asi_thr_i2[3] = ifq_fcl_asi_tid_bf[1] & ifq_fcl_asi_tid_bf[0];
|
assign asi_thr_i2[3] = ifq_fcl_asi_tid_bf[1] & ifq_fcl_asi_tid_bf[0];
|
|
|
dff #(2) asi_tids_reg(.din (fcl_erb_asi_tid_f),
|
dff_s #(2) asi_tids_reg(.din (fcl_erb_asi_tid_f),
|
.q (asi_tid_s1),
|
.q (asi_tid_s1),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff #(2) asi_tidw2_reg(.din (asi_tid_s1),
|
dff_s #(2) asi_tidw2_reg(.din (asi_tid_s1),
|
.q (asi_tid_w2),
|
.q (asi_tid_w2),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
assign ifu_lsu_ldxa_tid_w2 = asi_tid_w2;
|
assign ifu_lsu_ldxa_tid_w2 = asi_tid_w2;
|
|
|
assign erc_erd_asi_thr_l = ~asi_thr_s;
|
assign erc_erd_asi_thr_l = ~asi_thr_s;
|
|
|
assign asi_thr_s[0] = ~asi_tid_s1[1] & ~asi_tid_s1[0];
|
assign asi_thr_s[0] = ~asi_tid_s1[1] & ~asi_tid_s1[0];
|
| Line 1605... |
Line 1309... |
assign asi_thr_w2[2] = asi_tid_w2[1] & ~asi_tid_w2[0];
|
assign asi_thr_w2[2] = asi_tid_w2[1] & ~asi_tid_w2[0];
|
assign asi_thr_w2[3] = asi_tid_w2[1] & asi_tid_w2[0];
|
assign asi_thr_w2[3] = asi_tid_w2[1] & asi_tid_w2[0];
|
|
|
|
|
// F stage flops
|
// F stage flops
|
dff #(1) asi_en_ff(.din (ifq_erb_asi_erren_i2),
|
dff_s #(1) asi_en_ff(.din (ifq_erb_asi_erren_i2),
|
.q (asi_erren_f),
|
.q (asi_erren_f),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff #(1) asi_stat_ff(.din (ifq_erb_asi_errstat_i2),
|
dff_s #(1) asi_stat_ff(.din (ifq_erb_asi_errstat_i2),
|
.q (asi_errstat_f),
|
.q (asi_errstat_f),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff #(1) asi_addr_ff(.din (ifq_erb_asi_erraddr_i2),
|
dff_s #(1) asi_addr_ff(.din (ifq_erb_asi_erraddr_i2),
|
.q (asi_erraddr_f),
|
.q (asi_erraddr_f),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff #(1) asi_inj_ff(.din (ifq_erb_asi_errinj_i2),
|
dff_s #(1) asi_inj_ff(.din (ifq_erb_asi_errinj_i2),
|
.q (asi_errinj_f),
|
.q (asi_errinj_f),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff #(1) asi_im_ff(.din (ifq_erb_asi_imask_i2),
|
dff_s #(1) asi_im_ff(.din (ifq_erb_asi_imask_i2),
|
.q (asi_imask_f),
|
.q (asi_imask_f),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// S stage Flops
|
// S stage Flops
|
dff #(1) asi_ens_ff(.din (asi_erren_f),
|
dff_s #(1) asi_ens_ff(.din (asi_erren_f),
|
.q (asi_erren_s),
|
.q (asi_erren_s),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff #(1) asi_stats_ff(.din (asi_errstat_f),
|
dff_s #(1) asi_stats_ff(.din (asi_errstat_f),
|
.q (asi_errstat_s),
|
.q (asi_errstat_s),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff #(1) asi_addrs_ff(.din (asi_erraddr_f),
|
dff_s #(1) asi_addrs_ff(.din (asi_erraddr_f),
|
.q (asi_erraddr_s),
|
.q (asi_erraddr_s),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff #(1) asi_injs_ff(.din (asi_errinj_f),
|
dff_s #(1) asi_injs_ff(.din (asi_errinj_f),
|
.q (asi_errinj_s),
|
.q (asi_errinj_s),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff #(1) asi_ims_ff(.din (asi_imask_f),
|
dff_s #(1) asi_ims_ff(.din (asi_imask_f),
|
.q (asi_imask_s),
|
.q (asi_imask_s),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// ASI Reads
|
// ASI Reads
|
// All ASI reads except TLB
|
// All ASI reads except TLB
|
dff #(1) asi_rdf_ff(.din (ifq_fcl_asird_bf),
|
dff_s #(1) asi_rdf_ff(.din (ifq_fcl_asird_bf),
|
.q (asird_f),
|
.q (asird_f),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff #(1) asi_rds_ff(.din (asird_f),
|
dff_s #(1) asi_rds_ff(.din (asird_f),
|
.q (asird_s),
|
.q (asird_s),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// fwd reads
|
// fwd reads
|
dff #(1) fwd_rdf_ff(.din (ifq_erb_fwdrd_bf),
|
dff_s #(1) fwd_rdf_ff(.din (ifq_erb_fwdrd_bf),
|
.q (fwdrd_f),
|
.q (fwdrd_f),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff #(1) fwd_rds_ff(.din (fwdrd_f),
|
dff_s #(1) fwd_rds_ff(.din (fwdrd_f),
|
.q (fwdrd_s),
|
.q (fwdrd_s),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff #(1) fwd_rdd_ff(.din (fwdrd_s),
|
dff_s #(1) fwd_rdd_ff(.din (fwdrd_s),
|
.q (fwdrd_d),
|
.q (fwdrd_d),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign ifu_lsu_fwd_data_vld = fwdrd_d;
|
assign ifu_lsu_fwd_data_vld = fwdrd_d;
|
assign asifwd_rd_s = asird_s | fwdrd_s;
|
assign asifwd_rd_s = asird_s | fwdrd_s;
|
|
|
|
|
// asi reads from icache
|
// asi reads from icache
|
dff #(1) ic_rdts_ff(.din (ifq_erb_rdtag_f),
|
dff_s #(1) ic_rdts_ff(.din (ifq_erb_rdtag_f),
|
.q (rdtag_s),
|
.q (rdtag_s),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// forward requests also read instruction memory
|
// forward requests also read instruction memory
|
assign rdinst_f = fwdrd_f | ifq_erb_rdinst_f;
|
assign rdinst_f = fwdrd_f | ifq_erb_rdinst_f;
|
|
|
dff #(1) ic_rdds_ff(.din (rdinst_f),
|
dff_s #(1) ic_rdds_ff(.din (rdinst_f),
|
.q (rdinst_s),
|
.q (rdinst_s),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
|
|
// assign rst_tri_en = 1'b0;
|
// assign rst_tri_en = 1'b0;
|
|
|
// pick err asi source
|
// pick err asi source
|
| Line 1714... |
Line 1418... |
assign asi_tdevld_s1 = fcl_erb_itlbrd_vld_s & fcl_erb_itlbrd_data_s;
|
assign asi_tdevld_s1 = fcl_erb_itlbrd_vld_s & fcl_erb_itlbrd_data_s;
|
|
|
assign ldxa_data_vld_s = fcl_erb_itlbrd_vld_s | asird_s;
|
assign ldxa_data_vld_s = fcl_erb_itlbrd_vld_s | asird_s;
|
// assign ifu_lsu_ldxa_data_vld_w1 = ldxa_data_vld_s;
|
// assign ifu_lsu_ldxa_data_vld_w1 = ldxa_data_vld_s;
|
|
|
dff #(1) asirdd_ff(.din (ldxa_data_vld_s),
|
dff_s #(1) asirdd_ff(.din (ldxa_data_vld_s),
|
.q (ldxa_data_vld_d),
|
.q (ldxa_data_vld_d),
|
.clk (clk),
|
.clk (clk),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign ifu_lsu_ldxa_data_vld_w2 = ldxa_data_vld_d;
|
assign ifu_lsu_ldxa_data_vld_w2 = ldxa_data_vld_d;
|
|
|
|
|
// ASI Writes
|
// ASI Writes
|
