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[/] [s1_core/] [trunk/] [hdl/] [rtl/] [sparc_core/] [sparc_ifu_errdp.v] - Diff between revs 105 and 113

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Line 16... Line 16... 
// You should have received a copy of the GNU General Public
 
// You should have received a copy of the GNU General Public
 
// License along with this work; if not, write to the Free Software
 
// License along with this work; if not, write to the Free Software
 
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
 
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
 
// 
// 
// ========== Copyright Header End ============================================
 
// ========== Copyright Header End ============================================
 
 
 
`ifdef SIMPLY_RISC_TWEAKS
 
 
 
`define SIMPLY_RISC_SCANIN .si(0)
 
 
 
`else
 
 
 
`define SIMPLY_RISC_SCANIN .si()
 
 
 
`endif
 
////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////
 
/*
 
/*
 
//  Module Name:  sparc_ifu_errdp
 
//  Module Name:  sparc_ifu_errdp
 
*/
 
*/
 
////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////
 
// Global header file includes
 
// Global header file includes
 
////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////
 
 
 
 
 
/*
 
`include "lsu.h"
 
/* ========== Copyright Header Begin ==========================================
 
`include "ifu.h"
 
*
 
 
 
* OpenSPARC T1 Processor File: lsu.h
 
 
 
* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
 
 
 
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
 
 
 
*
 
 
 
* The above named program is free software; you can redistribute it and/or
 
 
 
* modify it under the terms of the GNU General Public
 
 
 
* License version 2 as published by the Free Software Foundation.
 
 
 
*
 
 
 
* The above named program is distributed in the hope that it will be
 
 
 
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
 
 
 
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 
 
 
* General Public License for more details.
 
 
 
*
 
 
 
* You should have received a copy of the GNU General Public
 
 
 
* License along with this work; if not, write to the Free Software
 
 
 
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
 
 
 
*
 
 
 
* ========== Copyright Header End ============================================
 
 
 
*/
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//`define STB_PCX_WY_HI   107
 
 
 
//`define STB_PCX_WY_LO   106
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// TLB Tag and Data Format
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// I-TLB version - lsu_tlb only.
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Invalidate Format
 
 
 
//addr<5:4>=00
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//addr<5:4>=01
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//addr<5:4>=10
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//addr<5:4>=11
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// cpuid - 4b
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// CPUany, addr<5:4>=00,10
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// CPUany, addr<5:4>=01,11
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// CPUany, addr<5:4>=01,11
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// DTAG parity error Invalidate
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// CPX BINIT STORE
 
 
 
 
 
 
 
/*
 
 
 
/* ========== Copyright Header Begin ==========================================
 
 
 
*
 
 
 
* OpenSPARC T1 Processor File: ifu.h
 
 
 
* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
 
 
 
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
 
 
 
*
 
 
 
* The above named program is free software; you can redistribute it and/or
 
 
 
* modify it under the terms of the GNU General Public
 
 
 
* License version 2 as published by the Free Software Foundation.
 
 
 
*
 
 
 
* The above named program is distributed in the hope that it will be
 
 
 
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
 
 
 
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 
 
 
* General Public License for more details.
 
 
 
*
 
 
 
* You should have received a copy of the GNU General Public
 
 
 
* License along with this work; if not, write to the Free Software
 
 
 
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
 
 
 
*
 
 
 
* ========== Copyright Header End ============================================
 
 
 
*/
 
 
 
////////////////////////////////////////////////////////////////////////
 
 
 
/*
 
 
 
//
 
 
 
//  Module Name: ifu.h
 
 
 
//  Description:
 
 
 
//  All ifu defines
 
 
 
*/
 
 
 
 
 
 
 
//--------------------------------------------
 
 
 
// Icache Values in IFU::ICD/ICV/ICT/FDP/IFQDP
 
 
 
//--------------------------------------------
 
 
 
// Set Values
 
 
 
 
 
 
 
// IC_IDX_HI = log(icache_size/4ways) - 1
 
 
 
 
 
 
 
 
 
 
 
// !!IMPORTANT!! a change to IC_LINE_SZ will mean a change to the code as
 
 
 
//   well.  Unfortunately this has not been properly parametrized.
 
 
 
//   Changing the IC_LINE_SZ param alone is *not* enough.
 
 
 
 
 
 
 
 
 
 
 
// !!IMPORTANT!! a change to IC_TAG_HI will mean a change to the code as
 
 
 
//   well.  Changing the IC_TAG_HI param alone is *not* enough to
 
 
 
//   change the PA range. 
 
 
// highest bit of PA
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Derived Values
 
 
 
// 4095
 
 
 
 
 
 
 
 
 
 
 
// number of entries - 1 = 511
 
 
 
 
 
 
 
 
 
 
 
// 12
 
 
 
 
 
 
 
 
 
 
 
// 28
 
 
 
 
 
 
 
 
 
 
 
// 7
 
 
 
 
 
 
 
 
 
 
 
// tags for all 4 ways + parity
 
 
 
// 116
 
 
 
 
 
 
 
 
 
 
 
// 115
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//----------------------------------------------------------------------
 
 
 
// For thread scheduler in IFU::DTU::SWL
 
 
 
//----------------------------------------------------------------------
 
 
 
// thread states:  (thr_state[4:0])
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// thread configuration register bit fields
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//----------------------------------------------------------------------
 
 
 
// For MIL fsm in IFU::IFQ
 
 
 
//----------------------------------------------------------------------
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//---------------------------------------------------
 
 
 
// Interrupt Block
 
 
 
//---------------------------------------------------
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//-------------------------------------
 
 
 
// IFQ
 
 
 
//-------------------------------------
 
 
 
// valid bit plus ifill
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//`ifdef SPARC_L2_64B
 
 
 
 
 
 
 
 
 
 
 
//`else
 
 
 
//`define BANK_ID_HI 8
 
 
 
//`define BANK_ID_LO 7
 
 
 
//`endif
 
 
 
 
 
 
 
//`define CPX_INV_PA_HI  116
 
 
 
//`define CPX_INV_PA_LO  112
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//----------------------------------------
 
 
 
// IFU Traps
 
 
 
//----------------------------------------
 
 
 
// precise
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// disrupting
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
module sparc_ifu_errdp(/*AUTOARG*/
 
module sparc_ifu_errdp(/*AUTOARG*/
 
   // Outputs
 
   // Outputs
 
   so, ifu_lsu_ldxa_data_w2, erb_dtu_imask, erd_erc_tlbt_pe_s1,
 
   so, ifu_lsu_ldxa_data_w2, erb_dtu_imask, erd_erc_tlbt_pe_s1,
 
   erd_erc_tlbd_pe_s1, erd_erc_tagpe_s1, erd_erc_nirpe_s1,
 
   erd_erc_tlbd_pe_s1, erd_erc_tagpe_s1, erd_erc_nirpe_s1,
Line 549... Line 74... 
   input [39:10] itlb_ifq_paddr_s;
 
   input [39:10] itlb_ifq_paddr_s;
 
   input [33:0] wsel_fdp_fetdata_s1,
 
   input [33:0] wsel_fdp_fetdata_s1,
 
                            wsel_fdp_topdata_s1;
 
                            wsel_fdp_topdata_s1;
 
   input [33:0] wsel_erb_asidata_s;
 
   input [33:0] wsel_erb_asidata_s;
 
 
 
 
 
   input [(((39 - 11) * 4) + 3):0] ict_itlb_tags_f;
 
   input [`IC_TAG_ALL_HI:0] ict_itlb_tags_f;
 
   input [3:0]              icv_itlb_valid_f;
 
   input [3:0]              icv_itlb_valid_f;
 
 
 
 
 
   input [47:4]  lsu_ifu_err_addr;
 
   input [47:4]  lsu_ifu_err_addr;
 
   input [39:4]  spu_ifu_err_addr_w2;
 
   input [39:4]  spu_ifu_err_addr_w2;
 
   input [47:0]  fdp_erb_pc_f;
 
   input [47:0]  fdp_erb_pc_f;
Line 570... Line 95... 
   input [1:0]   erc_erd_erren_asidata;
 
   input [1:0]   erc_erd_erren_asidata;
 
   input [22:0]  erc_erd_errstat_asidata;
 
   input [22:0]  erc_erd_errstat_asidata;
 
   input [31:0]  erc_erd_errinj_asidata;
 
   input [31:0]  erc_erd_errinj_asidata;
 
   input [47:0]  ifq_erb_asidata_i2;
 
   input [47:0]  ifq_erb_asidata_i2;
 
 
 
 
 
   input [(39 - 11)-1:0] ifq_erb_wrtag_f;
 
   input [`IC_TAG_SZ-1:0] ifq_erb_wrtag_f;
 
   input [11:4]   ifq_erb_wrindex_f;
 
   input [`IC_IDX_HI:4]   ifq_erb_wrindex_f;
 
 
 
 
 
   // mux selects
 
   // mux selects
 
   input [3:0]  erc_erd_asiway_s1_l;
 
   input [3:0]  erc_erd_asiway_s1_l;
 
   input        fcl_erb_itlbrd_data_s;
 
   input        fcl_erb_itlbrd_data_s;
 
   input        erc_erd_ld_imask;
 
   input        erc_erd_ld_imask;
Line 630... Line 155... 
// local signals   
// local signals   
//
 
//
 
 
 
 
 
   wire [47:4]   lsu_err_addr;
 
   wire [47:4]   lsu_err_addr;
 
 
 
 
 
   wire [(((39 - 11) * 4) + 3):0]  ictags_s1;
 
   wire [`IC_TAG_ALL_HI:0]  ictags_s1;
 
   wire [3:0]               icv_data_s1;
 
   wire [3:0]               icv_data_s1;
 
   wire [31:0]              tag_asi_data;
 
   wire [31:0]              tag_asi_data;
 
 
 
 
 
   wire [47:4]              t0_eadr_mx0_out,
 
   wire [47:4]              t0_eadr_mx0_out,
 
                                        t1_eadr_mx0_out,
 
                                        t1_eadr_mx0_out,
Line 687... Line 212... 
   assign                   clk = rclk;
 
   assign                   clk = rclk;
 
 
 
 
 
//-------------
 
//-------------
 
// Tags
 
// Tags
 
//-------------   
//-------------   
   dff #((((39 - 11) * 4) + 4)) tags_reg(.din (ict_itlb_tags_f),
 
   dff_s #(`IC_TAG_ALL) tags_reg(.din (ict_itlb_tags_f),
 
                                           .q   (ictags_s1),
 
                                           .q   (ictags_s1),
 
                                           .clk (clk),
 
                                           .clk (clk),
 
                                           .se  (se), .si(), .so());
 
                                           .se  (se), `SIMPLY_RISC_SCANIN, .so());
 
 
 
 
 
   dff #(4) vbits_reg(.din (icv_itlb_valid_f[3:0]),
 
   dff_s #(4) vbits_reg(.din (icv_itlb_valid_f[3:0]),
 
                                  .q   (icv_data_s1),
 
                                  .q   (icv_data_s1),
 
                                  .clk (clk), .se(se), .si(), .so());
 
                                  .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
 
 
 
 
 
   // check parity
 
   // check parity
 
   sparc_ifu_par32  tag_par0(.in  ({3'b0, ictags_s1[(39 - 11):0]}),
 
   sparc_ifu_par32  tag_par0(.in  ({3'b0, ictags_s1[`IC_TAG_SZ:0]}),
 
                                               .out (erd_erc_tagpe_s1[0]));
 
                                               .out (erd_erc_tagpe_s1[0]));
 
   sparc_ifu_par32  tag_par1(.in  ({3'b0, ictags_s1[((2*(39 - 11)) + 1):((39 - 11)+1)]}),
 
   sparc_ifu_par32  tag_par1(.in  ({3'b0, ictags_s1[((2*`IC_TAG_SZ) + 1):(`IC_TAG_SZ+1)]}),
 
                                               .out (erd_erc_tagpe_s1[1]));
 
                                               .out (erd_erc_tagpe_s1[1]));
 
   sparc_ifu_par32  tag_par2(.in  ({3'b0, ictags_s1[((3*(39 - 11)) + 2):(2*((39 - 11))+2)]}),
 
   sparc_ifu_par32  tag_par2(.in  ({3'b0, ictags_s1[((3*`IC_TAG_SZ) + 2):(2*(`IC_TAG_SZ)+2)]}),
 
                                               .out (erd_erc_tagpe_s1[2]));
 
                                               .out (erd_erc_tagpe_s1[2]));
 
   sparc_ifu_par32  tag_par3(.in  ({3'b0, ictags_s1[((4*(39 - 11)) + 3):(3*((39 - 11))+3)]}),
 
   sparc_ifu_par32  tag_par3(.in  ({3'b0, ictags_s1[((4*`IC_TAG_SZ) + 3):(3*(`IC_TAG_SZ)+3)]}),
 
                                               .out (erd_erc_tagpe_s1[3]));
 
                                               .out (erd_erc_tagpe_s1[3]));
 
 
 
 
 
   dp_mux4ds #(32) asitag_mux(.dout (tag_asi_data[31:0]),
 
   dp_mux4ds #(32) asitag_mux(.dout (tag_asi_data[31:0]),
 
                         .in0  ({icv_data_s1[0], 1'b0, ictags_s1[28], 1'b0, ictags_s1[27:0]}),
 
                         .in0  ({icv_data_s1[0], 1'b0, ictags_s1[28], 1'b0, ictags_s1[27:0]}),
 
                         .in1  ({icv_data_s1[1], 1'b0, ictags_s1[57], 1'b0, ictags_s1[56:29]}),
 
                         .in1  ({icv_data_s1[1], 1'b0, ictags_s1[57], 1'b0, ictags_s1[56:29]}),
Line 758... Line 283... 
 
 
 
 
//   assign erd_erc_tte_lock_s1 = itlb_rd_tte_data[`STLB_DATA_L];
 
//   assign erd_erc_tte_lock_s1 = itlb_rd_tte_data[`STLB_DATA_L];
 
 
 
 
 
 
 
 
 
//`ifdef        SPARC_HPV_EN
 
//`ifdef        SPARC_HPV_EN
 
   assign erd_erc_tte_pgsz[2:0] = {itlb_rd_tte_data[23],
 
   assign erd_erc_tte_pgsz[2:0] = {itlb_rd_tte_data[`STLB_DATA_27_22_SEL],
 
                                                           itlb_rd_tte_data[16],
 
                                                           itlb_rd_tte_data[`STLB_DATA_21_16_SEL],
 
                                                           itlb_rd_tte_data[12]};
 
                                                           itlb_rd_tte_data[`STLB_DATA_15_13_SEL]};
 
 
 
 
 
   assign formatted_tte_tag[63:0] =
 
   assign formatted_tte_tag[63:0] =
 
          {
 
          {
 
//           `ifdef SUN4V_TAG_RD
 
//           `ifdef SUN4V_TAG_RD
 
           // implement this!
 
           // implement this!
 
           itlb_rd_tte_tag[58:55],
 
           itlb_rd_tte_tag[58:55],
 
//           `else
 
//           `else
 
//         {4{itlb_rd_tte_tag[53]}},                                     // 4b
 
//         {4{itlb_rd_tte_tag[53]}},                                     // 4b
 
//           `endif
 
//           `endif
 
 
 
 
 
           itlb_rd_tte_tag[54],     // Parity                 1b
 
           itlb_rd_tte_tag[`STLB_TAG_PARITY],     // Parity                 1b
 
           itlb_rd_tte_tag[27], // mxsel2 - b27:22 vld    1b
 
           itlb_rd_tte_tag[`STLB_TAG_VA_27_22_V], // mxsel2 - b27:22 vld    1b
 
           itlb_rd_tte_tag[17], // mxsel1 - b21:16 vld    1b
 
           itlb_rd_tte_tag[`STLB_TAG_VA_21_16_V], // mxsel1 - b21:16 vld    1b
 
           itlb_rd_tte_tag[13], // mxsel0 - b15:13 vld    1b
 
           itlb_rd_tte_tag[`STLB_TAG_VA_15_13_V], // mxsel0 - b15:13 vld    1b
 
 
 
 
 
           {8{itlb_rd_tte_tag[53]}},                                     // 8b
 
           {8{itlb_rd_tte_tag[53]}},                                     // 8b
 
           itlb_rd_tte_tag[53:34], // 20b
 
           itlb_rd_tte_tag[`STLB_TAG_VA_47_28_HI:`STLB_TAG_VA_47_28_LO], // 20b
 
           itlb_rd_tte_tag[33:28], // 6b
 
           itlb_rd_tte_tag[`STLB_TAG_VA_27_22_HI:`STLB_TAG_VA_27_22_LO], // 6b
 
           itlb_rd_tte_tag[23:18], // 6b
 
           itlb_rd_tte_tag[`STLB_TAG_VA_21_16_HI:`STLB_TAG_VA_21_16_LO], // 6b
 
           itlb_rd_tte_tag[16:14], // 3b
 
           itlb_rd_tte_tag[`STLB_TAG_VA_15_13_HI:`STLB_TAG_VA_15_13_LO], // 3b
 
           itlb_rd_tte_tag[12:0]// 13b
 
           itlb_rd_tte_tag[`STLB_TAG_CTXT_12_0_HI:`STLB_TAG_CTXT_12_0_LO]// 13b
 
           } ;
 
           } ;
 
//`else
 
//`else
 
//   assign erd_erc_tte_pgsz[2:0] = {itlb_rd_tte_data[`STLB_DATA_21_19_SEL],
 
//   assign erd_erc_tte_pgsz[2:0] = {itlb_rd_tte_data[`STLB_DATA_21_19_SEL],
 
//                                                         itlb_rd_tte_data[`STLB_DATA_18_16_SEL],
 
//                                                         itlb_rd_tte_data[`STLB_DATA_18_16_SEL],
 
//                                                         itlb_rd_tte_data[`STLB_DATA_15_13_SEL]};
 
//                                                         itlb_rd_tte_data[`STLB_DATA_15_13_SEL]};
Line 807... Line 332... 
 
 
 
 
 
 
 
 
//`ifdef        SPARC_HPV_EN
 
//`ifdef        SPARC_HPV_EN
 
   assign formatted_tte_data[63:0] =
 
   assign formatted_tte_data[63:0] =
 
          {
 
          {
 
           itlb_rd_tte_tag[26],           // V    (1b)
 
           itlb_rd_tte_tag[`STLB_TAG_V],           // V    (1b)
 
           erc_erd_pgsz_b1,                        // pg SZ msb 4m or 512k
 
           erc_erd_pgsz_b1,                        // pg SZ msb 4m or 512k
 
           erc_erd_pgsz_b0,                        // pg sz lsb 4m or 64k
 
           erc_erd_pgsz_b0,                        // pg sz lsb 4m or 64k
 
           itlb_rd_tte_data[10],       // NFO  (1b)
 
           itlb_rd_tte_data[`STLB_DATA_NFO],       // NFO  (1b)
 
           itlb_rd_tte_data[9],        // IE   (1b)
 
           itlb_rd_tte_data[`STLB_DATA_IE],        // IE   (1b)
 
           10'b0,                                  // soft2 
           10'b0,                                  // soft2 
           itlb_rd_tte_data[23], // pgsz b2
 
           itlb_rd_tte_data[`STLB_DATA_27_22_SEL], // pgsz b2
 
           itlb_rd_tte_tag[24],
 
           itlb_rd_tte_tag[`STLB_TAG_U],
 
 
 
 
 
           itlb_rd_tte_data[42],      // Parity   (1b)
 
           itlb_rd_tte_data[`STLB_DATA_PARITY],      // Parity   (1b)
 
           itlb_rd_tte_data[23],   // mxsel2_l (1b)
 
           itlb_rd_tte_data[`STLB_DATA_27_22_SEL],   // mxsel2_l (1b)
 
           itlb_rd_tte_data[16],   // mxsel1_l (1b)
 
           itlb_rd_tte_data[`STLB_DATA_21_16_SEL],   // mxsel1_l (1b)
 
           itlb_rd_tte_data[12],   // mxsel0_l (1b)
 
           itlb_rd_tte_data[`STLB_DATA_15_13_SEL],   // mxsel0_l (1b)
 
 
 
 
 
           2'b0,                                   // unused diag 2b
 
           2'b0,                                   // unused diag 2b
 
           1'b0,                                   // ?? PA   (28b)
 
           1'b0,                                   // ?? PA   (28b)
 
           itlb_rd_tte_data[41:30],
 
           itlb_rd_tte_data[`STLB_DATA_PA_39_28_HI:`STLB_DATA_PA_39_28_LO],
 
           itlb_rd_tte_data[29:24],
 
           itlb_rd_tte_data[`STLB_DATA_PA_27_22_HI:`STLB_DATA_PA_27_22_LO],
 
           itlb_rd_tte_data[22:17],
 
           itlb_rd_tte_data[`STLB_DATA_PA_21_16_HI:`STLB_DATA_PA_21_16_LO],
 
           itlb_rd_tte_data[15:13],
 
           itlb_rd_tte_data[`STLB_DATA_PA_15_13_HI:`STLB_DATA_PA_15_13_LO],
 
           6'b0,                                   // ?? 12-7 (6b)
 
           6'b0,                                   // ?? 12-7 (6b)
 
           itlb_rd_tte_data[8],         // L    (1b)
 
           itlb_rd_tte_data[`STLB_DATA_L],         // L    (1b)
 
           itlb_rd_tte_data[7],        // CP   (1b)
 
           itlb_rd_tte_data[`STLB_DATA_CP],        // CP   (1b)
 
           itlb_rd_tte_data[6],        // CV   (1b)
 
           itlb_rd_tte_data[`STLB_DATA_CV],        // CV   (1b)
 
           itlb_rd_tte_data[5],         // E    (1b)
 
           itlb_rd_tte_data[`STLB_DATA_E],         // E    (1b)
 
           itlb_rd_tte_data[4],         // P    (1b)
 
           itlb_rd_tte_data[`STLB_DATA_P],         // P    (1b)
 
           itlb_rd_tte_data[3],         // W    (1b)
 
           itlb_rd_tte_data[`STLB_DATA_W],         // W    (1b)
 
                 1'b0
 
                 1'b0
 
        } ;
 
        } ;
 
//`else // !`ifdef SPARC_HPV_EN
 
//`else // !`ifdef SPARC_HPV_EN
 
//
 
//
 
//   assign formatted_tte_data[63:0] =
 
//   assign formatted_tte_data[63:0] =
Line 907... Line 432... 
                               .sel0_l (erc_erd_asisrc_sel_itlb_s_l),
 
                               .sel0_l (erc_erd_asisrc_sel_itlb_s_l),
 
                               .sel1_l (erc_erd_asisrc_sel_err_s_l),
 
                               .sel1_l (erc_erd_asisrc_sel_err_s_l),
 
                               .sel2_l (erc_erd_asisrc_sel_misc_s_l),
 
                               .sel2_l (erc_erd_asisrc_sel_misc_s_l),
 
                               .sel3_l (erc_erd_asisrc_sel_icd_s_l));
 
                               .sel3_l (erc_erd_asisrc_sel_icd_s_l));
 
 
 
 
 
   dff #(64) ldxa_reg(.din (ldxa_data_s),
 
   dff_s #(64) ldxa_reg(.din (ldxa_data_s),
 
                      .q   (ldxa_data_d),
 
                      .q   (ldxa_data_d),
 
                      .clk (clk), .se(se), .si(), .so());
 
                      .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
 
   assign ifu_lsu_ldxa_data_w2 = ldxa_data_d;
 
   assign ifu_lsu_ldxa_data_w2 = ldxa_data_d;
 
 
 
 
 
 
 
 
 
//----------------------------------------
 
//----------------------------------------
 
// Error Address
 
// Error Address
 
//----------------------------------------   
//----------------------------------------   
 
 
 
 
   assign ifet_addr_f = {ifq_erb_wrtag_f[(39 - 11)-1:0],
 
   assign ifet_addr_f = {ifq_erb_wrtag_f[`IC_TAG_SZ-1:0],
 
                         ifq_erb_wrindex_f[11:4]};
 
                         ifq_erb_wrindex_f[`IC_IDX_HI:4]};
 
 
 
 
 
   // pc of latest access
 
   // pc of latest access
 
   dff #(48) pcs1_reg(.din (fdp_erb_pc_f[47:0]),
 
   dff_s #(48) pcs1_reg(.din (fdp_erb_pc_f[47:0]),
 
                                  .q   (pc_s1[47:0]),
 
                                  .q   (pc_s1[47:0]),
 
                                  .clk (clk), .se(se), .si(), .so());
 
                                  .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
 
 
 
 
 
   // Physical address
 
   // Physical address
 
   assign paddr_s1[39:10] = itlb_ifq_paddr_s[39:10];
 
   assign paddr_s1[39:10] = itlb_ifq_paddr_s[39:10];
 
   assign paddr_s1[9:4]   = pc_s1[9:4];
 
   assign paddr_s1[9:4]   = pc_s1[9:4];
 
   dff #(36) padd_reg(.din (paddr_s1[39:4]),
 
   dff_s #(36) padd_reg(.din (paddr_s1[39:4]),
 
                                  .q   (paddr_d1[39:4]),
 
                                  .q   (paddr_d1[39:4]),
 
                                  .clk (clk), .se(se), .si(), .so());
 
                                  .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
 
 
 
 
 
//   assign erb_ifq_paddr_s[9:0] = pc_s1[9:0];
 
//   assign erb_ifq_paddr_s[9:0] = pc_s1[9:0];
 
 
 
 
 
   // stage PC one more cycle
 
   // stage PC one more cycle
 
   dff #(44) pcd1_reg(.din (pc_s1[47:4]),
 
   dff_s #(44) pcd1_reg(.din (pc_s1[47:4]),
 
                                  .q   (pc_d1[47:4]),
 
                                  .q   (pc_d1[47:4]),
 
                                  .clk (clk), .se(se), .si(), .so());
 
                                  .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
 
 
 
 
 
   // IRF address
 
   // IRF address
 
   dff #(16) irf_reg(.din ({exu_ifu_err_reg_m[7:0],
 
   dff_s #(16) irf_reg(.din ({exu_ifu_err_reg_m[7:0],
 
                            exu_ifu_err_synd_m[7:0]}),
 
                            exu_ifu_err_synd_m[7:0]}),
 
                                 .q   ({irfaddr_w[7:5],
 
                                 .q   ({irfaddr_w[7:5],
 
                            irfaddr_4_w,
 
                            irfaddr_4_w,
 
                            irfaddr_w[3:0],
 
                            irfaddr_w[3:0],
 
                            irfsynd_w[7:0]}),
 
                            irfsynd_w[7:0]}),
 
                                 .clk (clk), .se(se), .si(), .so());
 
                                 .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
 
 
 
 
 
   // fix for bug 5594
 
   // fix for bug 5594
 
   // nand2 + xnor
 
   // nand2 + xnor
 
   assign irfaddr_w[4] = irfaddr_4_w ^ (irfaddr_w[5] & irfaddr_w[3]);
 
   assign irfaddr_w[4] = irfaddr_4_w ^ (irfaddr_w[5] & irfaddr_w[3]);
 
 
 
 
 
   // itlb asi address
 
   // itlb asi address
 
   dff #(6) itlbidx_reg(.din (tlu_itlb_rw_index_g),
 
   dff_s #(6) itlbidx_reg(.din (tlu_itlb_rw_index_g),
 
                        .q   (itlb_asi_index),
 
                        .q   (itlb_asi_index),
 
                        .clk (clk), .se(se), .si(), .so());
 
                        .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
 
 
 
 
 
 
 
 
 
   // lsu error address
 
   // lsu error address
 
   dff #(44) lsadr_reg(.din (lsu_ifu_err_addr),
 
   dff_s #(44) lsadr_reg(.din (lsu_ifu_err_addr),
 
                       .q   (lsu_err_addr),
 
                       .q   (lsu_err_addr),
 
                       .clk (clk), .se(se), .si(), .so());
 
                       .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
 
 
 
 
 
 
 
 
 
   // mux in the different error addresses
 
   // mux in the different error addresses
 
   // thread 0
 
   // thread 0
 
   dp_mux4ds #(44) t0_eadr_mx0(.dout  (t0_eadr_mx0_out),
 
   dp_mux4ds #(44) t0_eadr_mx0(.dout  (t0_eadr_mx0_out),
Line 998... Line 523... 
                             .sel0_l (erc_erd_eadr2_sel_mx0_l[0]),
 
                             .sel0_l (erc_erd_eadr2_sel_mx0_l[0]),
 
                             .sel1_l (erc_erd_eadr2_sel_mx1_l[0]),
 
                             .sel1_l (erc_erd_eadr2_sel_mx1_l[0]),
 
                             .sel2_l (erc_erd_eadr2_sel_wrt_l[0]),
 
                             .sel2_l (erc_erd_eadr2_sel_wrt_l[0]),
 
                             .sel3_l (erc_erd_eadr2_sel_old_l[0]));
 
                             .sel3_l (erc_erd_eadr2_sel_old_l[0]));
 
 
 
 
 
   dff #(44) t0_eadr_reg(.din (t0_err_addr_nxt),
 
   dff_s #(44) t0_eadr_reg(.din (t0_err_addr_nxt),
 
                       .q   (t0_err_addr),
 
                       .q   (t0_err_addr),
 
                       .clk (clk), .se(se), .si(), .so());
 
                       .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
`ifdef FPGA_SYN_1THREAD
 
 
 
        assign err_addr_asidata = t0_err_addr;
 
 
 
`else
 
   // thread 1
 
   // thread 1
 
   dp_mux4ds #(44) t1_eadr_mx0(.dout  (t1_eadr_mx0_out),
 
   dp_mux4ds #(44) t1_eadr_mx0(.dout  (t1_eadr_mx0_out),
 
                             .in0   ({24'b0, irfsynd_w[7:0], 4'b0, irfaddr_w[7:0]}),
 
                             .in0   ({24'b0, irfsynd_w[7:0], 4'b0, irfaddr_w[7:0]}),
 
                             .in1   ({38'b0, itlb_asi_index}),
 
                             .in1   ({38'b0, itlb_asi_index}),
 
                             .in2   ({17'b0, ffu_ifu_err_synd_w2[13:7],
 
                             .in2   ({17'b0, ffu_ifu_err_synd_w2[13:7],
Line 1039... Line 564... 
                             .sel0_l (erc_erd_eadr2_sel_mx0_l[1]),
 
                             .sel0_l (erc_erd_eadr2_sel_mx0_l[1]),
 
                             .sel1_l (erc_erd_eadr2_sel_mx1_l[1]),
 
                             .sel1_l (erc_erd_eadr2_sel_mx1_l[1]),
 
                             .sel2_l (erc_erd_eadr2_sel_wrt_l[1]),
 
                             .sel2_l (erc_erd_eadr2_sel_wrt_l[1]),
 
                             .sel3_l (erc_erd_eadr2_sel_old_l[1]));
 
                             .sel3_l (erc_erd_eadr2_sel_old_l[1]));
 
 
 
 
 
   dff #(44) t1_eadr_reg(.din (t1_err_addr_nxt),
 
   dff_s #(44) t1_eadr_reg(.din (t1_err_addr_nxt),
 
                       .q   (t1_err_addr),
 
                       .q   (t1_err_addr),
 
                       .clk (clk), .se(se), .si(), .so());
 
                       .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
 
 
 
 
 
   // thread 2
 
   // thread 2
 
   dp_mux4ds #(44) t2_eadr_mx0(.dout  (t2_eadr_mx0_out),
 
   dp_mux4ds #(44) t2_eadr_mx0(.dout  (t2_eadr_mx0_out),
 
                             .in0   ({24'b0, irfsynd_w[7:0], 4'b0, irfaddr_w[7:0]}),
 
                             .in0   ({24'b0, irfsynd_w[7:0], 4'b0, irfaddr_w[7:0]}),
 
                             .in1   ({38'b0, itlb_asi_index}),
 
                             .in1   ({38'b0, itlb_asi_index}),
Line 1077... Line 602... 
                             .sel0_l (erc_erd_eadr2_sel_mx0_l[2]),
 
                             .sel0_l (erc_erd_eadr2_sel_mx0_l[2]),
 
                             .sel1_l (erc_erd_eadr2_sel_mx1_l[2]),
 
                             .sel1_l (erc_erd_eadr2_sel_mx1_l[2]),
 
                             .sel2_l (erc_erd_eadr2_sel_wrt_l[2]),
 
                             .sel2_l (erc_erd_eadr2_sel_wrt_l[2]),
 
                             .sel3_l (erc_erd_eadr2_sel_old_l[2]));
 
                             .sel3_l (erc_erd_eadr2_sel_old_l[2]));
 
 
 
 
 
   dff #(44) t2_eadr_reg(.din (t2_err_addr_nxt),
 
   dff_s #(44) t2_eadr_reg(.din (t2_err_addr_nxt),
 
                       .q   (t2_err_addr),
 
                       .q   (t2_err_addr),
 
                       .clk (clk), .se(se), .si(), .so());
 
                       .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
 
 
 
 
 
   // thread 3
 
   // thread 3
 
   dp_mux4ds #(44) t3_eadr_mx0(.dout  (t3_eadr_mx0_out),
 
   dp_mux4ds #(44) t3_eadr_mx0(.dout  (t3_eadr_mx0_out),
 
                             .in0   ({24'b0, irfsynd_w[7:0], 4'b0, irfaddr_w[7:0]}),
 
                             .in0   ({24'b0, irfsynd_w[7:0], 4'b0, irfaddr_w[7:0]}),
 
                             .in1   ({38'b0, itlb_asi_index}),
 
                             .in1   ({38'b0, itlb_asi_index}),
Line 1115... Line 640... 
                             .sel0_l (erc_erd_eadr2_sel_mx0_l[3]),
 
                             .sel0_l (erc_erd_eadr2_sel_mx0_l[3]),
 
                             .sel1_l (erc_erd_eadr2_sel_mx1_l[3]),
 
                             .sel1_l (erc_erd_eadr2_sel_mx1_l[3]),
 
                             .sel2_l (erc_erd_eadr2_sel_wrt_l[3]),
 
                             .sel2_l (erc_erd_eadr2_sel_wrt_l[3]),
 
                             .sel3_l (erc_erd_eadr2_sel_old_l[3]));
 
                             .sel3_l (erc_erd_eadr2_sel_old_l[3]));
 
 
 
 
 
   dff #(44) t3_eadr_reg(.din (t3_err_addr_nxt),
 
   dff_s #(44) t3_eadr_reg(.din (t3_err_addr_nxt),
 
                       .q   (t3_err_addr),
 
                       .q   (t3_err_addr),
 
                       .clk (clk), .se(se), .si(), .so());
 
                       .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
 
 
 
 
 
 
 
 
 
   // asi read
 
   // asi read
 
   dp_mux4ds #(44) asi_eadr_mx(.dout (err_addr_asidata),
 
   dp_mux4ds #(44) asi_eadr_mx(.dout (err_addr_asidata),
 
                             .in0  (t0_err_addr),
 
                             .in0  (t0_err_addr),
Line 1130... Line 655... 
                             .in3  (t3_err_addr),
 
                             .in3  (t3_err_addr),
 
                             .sel0_l (erc_erd_asi_thr_l[0]),
 
                             .sel0_l (erc_erd_asi_thr_l[0]),
 
                             .sel1_l (erc_erd_asi_thr_l[1]),
 
                             .sel1_l (erc_erd_asi_thr_l[1]),
 
                             .sel2_l (erc_erd_asi_thr_l[2]),
 
                             .sel2_l (erc_erd_asi_thr_l[2]),
 
                             .sel3_l (erc_erd_asi_thr_l[3]));
 
                             .sel3_l (erc_erd_asi_thr_l[3]));
 
 
 
`endif
 
 
 
 
 
   // Instruction Mask
 
   // Instruction Mask
 
   dp_mux2es #(39) imask_en_mux(.dout (imask_next),
 
   dp_mux2es #(39) imask_en_mux(.dout (imask_next),
 
                              .in0  (erb_dtu_imask),
 
                              .in0  (erb_dtu_imask),
 
                              .in1  (ifq_erb_asidata_i2[38:0]),
 
                              .in1  (ifq_erb_asidata_i2[38:0]),
 
                              .sel  (erc_erd_ld_imask));
 
                              .sel  (erc_erd_ld_imask));
 
 
 
 
 
   // need to reset top 7 bits only
 
   // need to reset top 7 bits only
 
   dffr #(39) imask_reg(.din (imask_next),
 
   dffr_s #(39) imask_reg(.din (imask_next),
 
                      .q   (erb_dtu_imask),
 
                      .q   (erb_dtu_imask),
 
                      .rst (erb_reset),
 
                      .rst (erb_reset),
 
                      .clk (clk), .se(se), .si(), .so());
 
                      .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
 
 
 
 
 
   sink #(4) s0(.in (pc_s1[3:0]));
 
   sink #(4) s0(.in (pc_s1[3:0]));
 
 
 
 
 
endmodule // sparc_ifu_erb
 
endmodule // sparc_ifu_erb
 
 
 
 

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