| Line 16... |
Line 16... |
// You should have received a copy of the GNU General Public
|
// You should have received a copy of the GNU General Public
|
// License along with this work; if not, write to the Free Software
|
// License along with this work; if not, write to the Free Software
|
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
|
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
|
//
|
//
|
// ========== Copyright Header End ============================================
|
// ========== Copyright Header End ============================================
|
|
`ifdef SIMPLY_RISC_TWEAKS
|
|
`define SIMPLY_RISC_SCANIN .si(0)
|
|
`else
|
|
`define SIMPLY_RISC_SCANIN .si()
|
|
`endif
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
/*
|
/*
|
// Module Name: sparc_ifu_fcl
|
// Module Name: sparc_ifu_fcl
|
// Description:
|
// Description:
|
// The FCL is the fetch control logic. It controls the PC datapath
|
// The FCL is the fetch control logic. It controls the PC datapath
|
| Line 35... |
Line 40... |
*/
|
*/
|
////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////
|
// Global header file includes
|
// Global header file includes
|
////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////
|
|
|
/*
|
`include "ifu.h"
|
/* ========== Copyright Header Begin ==========================================
|
|
*
|
|
* OpenSPARC T1 Processor File: ifu.h
|
|
* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
|
|
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
|
|
*
|
|
* The above named program is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU General Public
|
|
* License version 2 as published by the Free Software Foundation.
|
|
*
|
|
* The above named program is distributed in the hope that it will be
|
|
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
|
* General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public
|
|
* License along with this work; if not, write to the Free Software
|
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
|
|
*
|
|
* ========== Copyright Header End ============================================
|
|
*/
|
|
////////////////////////////////////////////////////////////////////////
|
|
/*
|
|
//
|
|
// Module Name: ifu.h
|
|
// Description:
|
|
// All ifu defines
|
|
*/
|
|
|
|
//--------------------------------------------
|
|
// Icache Values in IFU::ICD/ICV/ICT/FDP/IFQDP
|
|
//--------------------------------------------
|
|
// Set Values
|
|
|
|
// IC_IDX_HI = log(icache_size/4ways) - 1
|
|
|
|
|
|
// !!IMPORTANT!! a change to IC_LINE_SZ will mean a change to the code as
|
|
// well. Unfortunately this has not been properly parametrized.
|
|
// Changing the IC_LINE_SZ param alone is *not* enough.
|
|
|
|
|
|
// !!IMPORTANT!! a change to IC_TAG_HI will mean a change to the code as
|
|
// well. Changing the IC_TAG_HI param alone is *not* enough to
|
|
// change the PA range.
|
|
// highest bit of PA
|
|
|
|
|
|
|
|
// Derived Values
|
|
// 4095
|
|
|
|
|
|
// number of entries - 1 = 511
|
|
|
|
|
|
// 12
|
|
|
|
|
|
// 28
|
|
|
|
|
|
// 7
|
|
|
|
|
|
// tags for all 4 ways + parity
|
|
// 116
|
|
|
|
|
|
// 115
|
|
|
|
|
|
|
|
//----------------------------------------------------------------------
|
|
// For thread scheduler in IFU::DTU::SWL
|
|
//----------------------------------------------------------------------
|
|
// thread states: (thr_state[4:0])
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// thread configuration register bit fields
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
//----------------------------------------------------------------------
|
|
// For MIL fsm in IFU::IFQ
|
|
//----------------------------------------------------------------------
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
//---------------------------------------------------
|
|
// Interrupt Block
|
|
//---------------------------------------------------
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
//-------------------------------------
|
|
// IFQ
|
|
//-------------------------------------
|
|
// valid bit plus ifill
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
//`ifdef SPARC_L2_64B
|
|
|
|
|
|
//`else
|
|
//`define BANK_ID_HI 8
|
|
//`define BANK_ID_LO 7
|
|
//`endif
|
|
|
|
//`define CPX_INV_PA_HI 116
|
|
//`define CPX_INV_PA_LO 112
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
//----------------------------------------
|
|
// IFU Traps
|
|
//----------------------------------------
|
|
// precise
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// disrupting
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module sparc_ifu_fcl(/*AUTOARG*/
|
module sparc_ifu_fcl(/*AUTOARG*/
|
// Outputs
|
// Outputs
|
fcl_icd_rdreq_bf, fcl_icv_rdreq_bf, fcl_icd_wrreq_bf,
|
fcl_icd_rdreq_bf, fcl_icv_rdreq_bf, fcl_icd_wrreq_bf,
|
| Line 1196... |
Line 1022... |
//----------------------------------------------------------------------
|
//----------------------------------------------------------------------
|
|
|
// reset buffer
|
// reset buffer
|
dffrl_async rstff(.din (grst_l),
|
dffrl_async rstff(.din (grst_l),
|
.q (fcl_reset_l),
|
.q (fcl_reset_l),
|
.clk (clk), .se(se), .si(), .so(),
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so(),
|
.rst_l (arst_l));
|
.rst_l (arst_l));
|
|
|
assign fcl_reset = ~fcl_reset_l;
|
assign fcl_reset = ~fcl_reset_l;
|
assign ifu_reset_l = fcl_reset_l;
|
assign ifu_reset_l = fcl_reset_l;
|
|
|
|
|
//-----------------------------------
|
//-----------------------------------
|
// TLB Operations
|
// TLB Operations
|
//-----------------------------------
|
//-----------------------------------
|
|
|
dff #(4) real_reg(.din (lsu_ifu_addr_real_l),
|
dff_s #(4) real_reg(.din (lsu_ifu_addr_real_l),
|
.q (itlb_addr_real_l),
|
.q (itlb_addr_real_l),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
assign itlb_addr_real = ~itlb_addr_real_l;
|
assign itlb_addr_real = ~itlb_addr_real_l;
|
|
|
// ITLB on signal
|
// ITLB on signal
|
|
|
//`ifdef SPARC_HPV_EN
|
//`ifdef SPARC_HPV_EN
|
| Line 1223... |
Line 1049... |
|
|
//`else
|
//`else
|
// assign xlate_en = lsu_ifu_addr_real_l;
|
// assign xlate_en = lsu_ifu_addr_real_l;
|
//`endif
|
//`endif
|
|
|
dff #(4) xlate_reg(.din (xlate_en),
|
dff_s #(4) xlate_reg(.din (xlate_en),
|
.q (xlate_en_d1),
|
.q (xlate_en_d1),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// assign sw_itlb_on = ((nextthr_bf_buf & xlate_en_d1) == 4'b0) ?
|
// assign sw_itlb_on = ((nextthr_bf_buf & xlate_en_d1) == 4'b0) ?
|
// 1'b0 : 1'b1;
|
// 1'b0 : 1'b1;
|
// assign this_itlb_on = ((thr_f & xlate_en_d1) == 4'b0) ?
|
// assign this_itlb_on = ((thr_f & xlate_en_d1) == 4'b0) ?
|
// 1'b0 : 1'b1;
|
// 1'b0 : 1'b1;
|
| Line 1295... |
Line 1121... |
.sel0 (pid_sel_sw),
|
.sel0 (pid_sel_sw),
|
.sel1 (pid_sel_curr),
|
.sel1 (pid_sel_curr),
|
.sel2 (pid_sel_dmp));
|
.sel2 (pid_sel_dmp));
|
|
|
// ITLB address mask
|
// ITLB address mask
|
dff #(4) am_reg(.din (tlu_lsu_pstate_am),
|
dff_s #(4) am_reg(.din (tlu_lsu_pstate_am),
|
.q (pstate_am_d1),
|
.q (pstate_am_d1),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign sw_itlb_am = ((nextthr_bf_buf & pstate_am_d1) == 4'b0) ?
|
assign sw_itlb_am = ((nextthr_bf_buf & pstate_am_d1) == 4'b0) ?
|
1'b0 : 1'b1;
|
1'b0 : 1'b1;
|
assign fcl_itlb_addr_mask_l = switch_bf ?
|
assign fcl_itlb_addr_mask_l = switch_bf ?
|
~sw_itlb_am : ~fcl_fdp_mask32b_f;
|
~sw_itlb_am : ~fcl_fdp_mask32b_f;
|
|
|
dff #(4) tlz_reg(.din ({lsu_ifu_t3_tlz,
|
dff_s #(4) tlz_reg(.din ({lsu_ifu_t3_tlz,
|
lsu_ifu_t2_tlz,
|
lsu_ifu_t2_tlz,
|
lsu_ifu_t1_tlz,
|
lsu_ifu_t1_tlz,
|
lsu_ifu_t0_tlz}),
|
lsu_ifu_t0_tlz}),
|
.q (tlzero_vec_d1[3:0]),
|
.q (tlzero_vec_d1[3:0]),
|
.clk (clk), .se (se), .si(), .so());
|
.clk (clk), .se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
|
|
// TLB context select
|
// TLB context select
|
assign fcl_fdp_tctxt_sel_prim = tlzero_vec_d1 & itlb_addr_real_l;
|
assign fcl_fdp_tctxt_sel_prim = tlzero_vec_d1 & itlb_addr_real_l;
|
// assign fcl_fdp_tctxt_sel_prim[1] = lsu_ifu_t1_tlz & itlb_addr_real_l[1];
|
// assign fcl_fdp_tctxt_sel_prim[1] = lsu_ifu_t1_tlz & itlb_addr_real_l[1];
|
| Line 1326... |
Line 1152... |
assign cam_vld_bf = itlb_on & inst_access_bf;
|
assign cam_vld_bf = itlb_on & inst_access_bf;
|
|
|
assign fcl_itlb_cam_vld_bf = cam_vld_bf;
|
assign fcl_itlb_cam_vld_bf = cam_vld_bf;
|
assign fcl_itlb_cam_bypass_bf = ~cam_vld_bf;
|
assign fcl_itlb_cam_bypass_bf = ~cam_vld_bf;
|
|
|
dff #(1) itlb_onf_ff(.din (cam_vld_bf),
|
dff_s #(1) itlb_onf_ff(.din (cam_vld_bf),
|
.q (cam_vld_f),
|
.q (cam_vld_f),
|
.clk (clk),
|
.clk (clk),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff #(1) itlb_ons1_ff(.din (cam_vld_f),
|
dff_s #(1) itlb_ons1_ff(.din (cam_vld_f),
|
.q (cam_vld_s1),
|
.q (cam_vld_s1),
|
.clk (clk),
|
.clk (clk),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// allow rd/wr/demap access to tlb
|
// allow rd/wr/demap access to tlb
|
// itlb access is granted only every other cycle
|
// itlb access is granted only every other cycle
|
// (not enough time to turn the request from mmu around)
|
// (not enough time to turn the request from mmu around)
|
// assign itlb_access_en = ~cam_vld_bf & ~ifq_fcl_asird_bf &
|
// assign itlb_access_en = ~cam_vld_bf & ~ifq_fcl_asird_bf &
|
| Line 1360... |
Line 1186... |
~itlb_access_done;
|
~itlb_access_done;
|
|
|
// reset tlb
|
// reset tlb
|
// dff #(1) itlbrst_ff(.din (tlu_itlb_invalidate_all_g),
|
// dff #(1) itlbrst_ff(.din (tlu_itlb_invalidate_all_g),
|
// .q (tlb_invall_req_bf),
|
// .q (tlb_invall_req_bf),
|
// .clk (clk), .se(se), .si(), .so());
|
// .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
// assign tlb_invall_bf = tlb_invall_req_bf & ~itlb_access_done;
|
// assign tlb_invall_bf = tlb_invall_req_bf & ~itlb_access_done;
|
assign tlb_invall_bf = sehold ? tlb_invall_f :
|
assign tlb_invall_bf = sehold ? tlb_invall_f :
|
(tlu_itlb_invalidate_all_g & itlb_access_en);
|
(tlu_itlb_invalidate_all_g & itlb_access_en);
|
dff #(1) itlbrstf_ff(.din (tlb_invall_bf),
|
dff_s #(1) itlbrstf_ff(.din (tlb_invall_bf),
|
.q (tlb_invall_f),
|
.q (tlb_invall_f),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign fcl_itlb_wr_vld_bf = tlu_itlb_wr_vld_g & itlb_write_en;
|
assign fcl_itlb_wr_vld_bf = tlu_itlb_wr_vld_g & itlb_write_en;
|
assign fcl_itlb_dmp_vld_bf = tlu_itlb_dmp_vld_g & itlb_access_en;
|
assign fcl_itlb_dmp_vld_bf = tlu_itlb_dmp_vld_g & itlb_access_en;
|
assign fcl_itlb_dmp_all_bf = tlu_itlb_dmp_all_g & tlu_itlb_dmp_vld_g &
|
assign fcl_itlb_dmp_all_bf = tlu_itlb_dmp_all_g & tlu_itlb_dmp_vld_g &
|
itlb_access_en;
|
itlb_access_en;
|
| Line 1410... |
Line 1236... |
fcl_itlb_tag_rd_vld_bf |
|
fcl_itlb_tag_rd_vld_bf |
|
// tlb_invall_bf & itlb_access_en |
|
// tlb_invall_bf & itlb_access_en |
|
tlb_invall_bf |
|
tlb_invall_bf |
|
fcl_itlb_dmp_vld_bf);
|
fcl_itlb_dmp_vld_bf);
|
|
|
dff #(1) tlb_gnt1_ff(.din (itlb_access_gnt),
|
dff_s #(1) tlb_gnt1_ff(.din (itlb_access_gnt),
|
.q (itlb_access_done),
|
.q (itlb_access_done),
|
.clk (clk), .se (se), .si(), .so());
|
.clk (clk), .se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff #(1) tlb_rd_ff(.din (itlb_rd_req_bf),
|
dff_s #(1) tlb_rd_ff(.din (itlb_rd_req_bf),
|
.q (itlb_rd_req_f),
|
.q (itlb_rd_req_f),
|
.clk (clk), .se (se), .si(), .so());
|
.clk (clk), .se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff #(1) tlb_wrt1_ff(.din (fcl_itlb_wr_vld_bf),
|
dff_s #(1) tlb_wrt1_ff(.din (fcl_itlb_wr_vld_bf),
|
.q (itlb_write_done),
|
.q (itlb_write_done),
|
.clk (clk), .se (se), .si(), .so());
|
.clk (clk), .se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
|
|
// TBD:
|
// TBD:
|
// reads need to wait one more cycle. Others can ack without this
|
// reads need to wait one more cycle. Others can ack without this
|
// second delay.
|
// second delay.
|
assign itlb_rd_access_done = itlb_rd_req_f & itlb_access_done;
|
assign itlb_rd_access_done = itlb_rd_req_f & itlb_access_done;
|
|
|
dff #(1) tlb_rd1_ff(.din (itlb_rd_access_done),
|
dff_s #(1) tlb_rd1_ff(.din (itlb_rd_access_done),
|
.q (itlb_rd_access_done_d1),
|
.q (itlb_rd_access_done_d1),
|
.clk (clk), .se (se), .si(), .so());
|
.clk (clk), .se (se), `SIMPLY_RISC_SCANIN, .so());
|
dff #(1) tlb_rd2_ff(.din (itlb_rd_access_done_d1),
|
dff_s #(1) tlb_rd2_ff(.din (itlb_rd_access_done_d1),
|
.q (itlb_rd_access_done_d2),
|
.q (itlb_rd_access_done_d2),
|
.clk (clk), .se (se), .si(), .so());
|
.clk (clk), .se (se), `SIMPLY_RISC_SCANIN, .so());
|
assign ifu_tlu_itlb_done = ~itlb_rd_req_f & itlb_access_done |
|
assign ifu_tlu_itlb_done = ~itlb_rd_req_f & itlb_access_done |
|
itlb_write_done |
|
itlb_write_done |
|
itlb_rd_access_done_d2;
|
itlb_rd_access_done_d2;
|
|
|
assign fcl_erb_itlbrd_vld_s = itlb_rd_access_done_d1;
|
assign fcl_erb_itlbrd_vld_s = itlb_rd_access_done_d1;
|
|
|
assign asi_tid_bf = ifq_fcl_asird_bf ? ifq_fcl_asi_tid_bf :
|
assign asi_tid_bf = ifq_fcl_asird_bf ? ifq_fcl_asi_tid_bf :
|
tlu_idtlb_dmp_thrid_g;
|
tlu_idtlb_dmp_thrid_g;
|
|
|
dff #(2) asi_tid_reg(.din (asi_tid_bf),
|
dff_s #(2) asi_tid_reg(.din (asi_tid_bf),
|
.q (fcl_erb_asi_tid_f),
|
.q (fcl_erb_asi_tid_f),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
|
|
// Remember if we read tag or data
|
// Remember if we read tag or data
|
dff #(1) tlb_rddf_ff(.din (fcl_itlb_data_rd_vld_bf),
|
dff_s #(1) tlb_rddf_ff(.din (fcl_itlb_data_rd_vld_bf),
|
.q (itlb_data_rd_f),
|
.q (itlb_data_rd_f),
|
.clk (clk), .se (se), .si(), .so());
|
.clk (clk), .se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff #(1) tlb_rdds_ff(.din (itlb_data_rd_f),
|
dff_s #(1) tlb_rdds_ff(.din (itlb_data_rd_f),
|
.q (itlb_data_rd_s),
|
.q (itlb_data_rd_s),
|
.clk (clk), .se (se), .si(), .so());
|
.clk (clk), .se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// pick itlb ldxa data
|
// pick itlb ldxa data
|
assign fcl_erb_itlbrd_data_s = itlb_data_rd_s;
|
assign fcl_erb_itlbrd_data_s = itlb_data_rd_s;
|
|
|
// Demap thread
|
// Demap thread
|
| Line 1535... |
Line 1361... |
// earlier version for critical stuff
|
// earlier version for critical stuff
|
assign no_instacc_bf = all_stallreq | fcl_reset | rst_stallreq |
|
assign no_instacc_bf = all_stallreq | fcl_reset | rst_stallreq |
|
~dtu_fcl_ntr_s & (ely_stall_thisthr_f | usep_bf);
|
~dtu_fcl_ntr_s & (ely_stall_thisthr_f | usep_bf);
|
|
|
// check if icache is on
|
// check if icache is on
|
dff #(4) ic_en_reg(.din (lsu_ifu_icache_en),
|
dff_s #(4) ic_en_reg(.din (lsu_ifu_icache_en),
|
.q (icache_en_d1),
|
.q (icache_en_d1),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// assign sw_icache_on = (nextthr_bf_buf[0] & icache_en_d1[0] |
|
// assign sw_icache_on = (nextthr_bf_buf[0] & icache_en_d1[0] |
|
// nextthr_bf_buf[1] & icache_en_d1[1] |
|
// nextthr_bf_buf[1] & icache_en_d1[1] |
|
// nextthr_bf_buf[2] & icache_en_d1[2] |
|
// nextthr_bf_buf[2] & icache_en_d1[2] |
|
// nextthr_bf_buf[3] & icache_en_d1[3]);
|
// nextthr_bf_buf[3] & icache_en_d1[3]);
|
| Line 1555... |
Line 1381... |
nextthr_final_bf[1] & icache_en_d1[1] |
|
nextthr_final_bf[1] & icache_en_d1[1] |
|
nextthr_final_bf[2] & icache_en_d1[2] |
|
nextthr_final_bf[2] & icache_en_d1[2] |
|
nextthr_final_bf[3] & icache_en_d1[3]);
|
nextthr_final_bf[3] & icache_en_d1[3]);
|
|
|
// remember if icache was turned on
|
// remember if icache was turned on
|
dff #(1) icef_ff(.din (icache_on_bf),
|
dff_s #(1) icef_ff(.din (icache_on_bf),
|
.q (icache_on_f),
|
.q (icache_on_f),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff #(1) ices_ff(.din (icache_on_f),
|
dff_s #(1) ices_ff(.din (icache_on_f),
|
.q (icache_on_s1),
|
.q (icache_on_s1),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// check if cp is set
|
// check if cp is set
|
assign uncached_page_s1 = ~itlb_fcl_cp_s1 & cam_vld_s1;
|
assign uncached_page_s1 = ~itlb_fcl_cp_s1 & cam_vld_s1;
|
assign fcl_ifq_icache_en_s_l = ~icache_on_s1 | uncached_page_s1;
|
assign fcl_ifq_icache_en_s_l = ~icache_on_s1 | uncached_page_s1;
|
|
|
| Line 1578... |
Line 1404... |
|
|
// split off driver to icv to reduce load
|
// split off driver to icv to reduce load
|
assign fcl_icv_rdreq_bf = rdreq_bf | ifq_fcl_rdreq_bf;
|
assign fcl_icv_rdreq_bf = rdreq_bf | ifq_fcl_rdreq_bf;
|
|
|
// Read req pipe
|
// Read req pipe
|
dffr #(1) rdreq_ff(.din (rdreq_bf),
|
dffr_s #(1) rdreq_ff(.din (rdreq_bf),
|
.clk (clk),
|
.clk (clk),
|
.rst (fcl_reset),
|
.rst (fcl_reset),
|
.q (rdreq_f),
|
.q (rdreq_f),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
// Remember if we fetched in the last cycle
|
// Remember if we fetched in the last cycle
|
dff #(1) rdreqs1_ff (.din (rdreq_f),
|
dff_s #(1) rdreqs1_ff (.din (rdreq_f),
|
.clk (clk),
|
.clk (clk),
|
.q (rdreq_s1),
|
.q (rdreq_s1),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
assign fcl_ifq_rdreq_s1 = ~stall_s1;
|
assign fcl_ifq_rdreq_s1 = ~stall_s1;
|
|
|
// Use NIR pipe
|
// Use NIR pipe
|
assign usenir_bf = switch_bf ? usen_bf : usep_bf;
|
assign usenir_bf = switch_bf ? usen_bf : usep_bf;
|
|
|
dffr #(1) unf_ff(.din (usenir_bf),
|
dffr_s #(1) unf_ff(.din (usenir_bf),
|
.clk (clk),
|
.clk (clk),
|
.rst (fcl_reset),
|
.rst (fcl_reset),
|
.q (usenir_f),
|
.q (usenir_f),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
// Remember if we fetched in the last cycle
|
// Remember if we fetched in the last cycle
|
dff #(1) uns1_ff (.din (usenir_f),
|
dff_s #(1) uns1_ff (.din (usenir_f),
|
.clk (clk),
|
.clk (clk),
|
.q (usenir_s1),
|
.q (usenir_s1),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
|
|
// Write signal to icache if no access from pipe
|
// Write signal to icache if no access from pipe
|
assign ic_wrreq_bf = allow_ifq_access_icd_bf & ifq_fcl_wrreq_bf;
|
assign ic_wrreq_bf = allow_ifq_access_icd_bf & ifq_fcl_wrreq_bf;
|
|
|
| Line 1619... |
Line 1445... |
always @ (posedge clk)
|
always @ (posedge clk)
|
begin
|
begin
|
if (fcl_icd_rdreq_bf & fcl_icd_wrreq_bf)
|
if (fcl_icd_rdreq_bf & fcl_icd_wrreq_bf)
|
begin
|
begin
|
// 0in <fire -message "ERROR: sparc_ifu_fcl: rd and wr req to I$ at the same time"
|
// 0in <fire -message "ERROR: sparc_ifu_fcl: rd and wr req to I$ at the same time"
|
|
`ifdef DEFINE_0IN
|
|
`else
|
|
`ifdef MODELSIM
|
|
|
|
|
$display("CACHE_CONTENTION", "ERROR: sparc_ifu_fcl: rd and wr req to I$ at the same time");
|
$display("CACHE_CONTENTION", "ERROR: sparc_ifu_fcl: rd and wr req to I$ at the same time");
|
|
`else
|
|
$error("CACHE_CONTENTION", "ERROR: sparc_ifu_fcl: rd and wr req to I$ at the same time");
|
|
`endif
|
|
`endif
|
end
|
end
|
end
|
end
|
// synopsys translate_on
|
// synopsys translate_on
|
|
|
|
|
//-------------------------
|
//-------------------------
|
// Valid Instruction Pipe
|
// Valid Instruction Pipe
|
//-------------------------
|
//-------------------------
|
// F stage
|
// F stage
|
assign inst_vld_bf = fetch_bf;
|
assign inst_vld_bf = fetch_bf;
|
dff #(1) inst_vld_ff(.din (inst_vld_bf),
|
dff_s #(1) inst_vld_ff(.din (inst_vld_bf),
|
.clk (clk),
|
.clk (clk),
|
.q (inst_vld_f),
|
.q (inst_vld_f),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign stall_f = ~inst_vld_f | kill_curr_f;
|
assign stall_f = ~inst_vld_f | kill_curr_f;
|
assign stall_thisthr_f = stall_f | imsto_thisthr_s1 | // intrto_thisthr_d |
|
assign stall_thisthr_f = stall_f | imsto_thisthr_s1 | // intrto_thisthr_d |
|
kill_thread_s2 | rb_stg_s | ~dtu_fcl_running_s |
|
kill_thread_s2 | rb_stg_s | ~dtu_fcl_running_s |
|
iferrto_thisthr_d1;
|
iferrto_thisthr_d1;
|
| Line 1659... |
Line 1485... |
|
|
// assign stall_s1_nxt = stall_thisthr_f | intr_vld_s | tmsto_thisthr_f;
|
// assign stall_s1_nxt = stall_thisthr_f | intr_vld_s | tmsto_thisthr_f;
|
assign stall_s1_nxt = stall_thisthr_f; //| intr_vld_s;
|
assign stall_s1_nxt = stall_thisthr_f; //| intr_vld_s;
|
|
|
// S1 stage
|
// S1 stage
|
dff #(1) stalld_ff(.din (stall_s1_nxt),
|
dff_s #(1) stalld_ff(.din (stall_s1_nxt),
|
.clk (clk),
|
.clk (clk),
|
.q (stall_s1),
|
.q (stall_s1),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign inst_vld_s1 = ~stall_s1 & ~ic_miss_s1 & ~kill_curr_d;
|
assign inst_vld_s1 = ~stall_s1 & ~ic_miss_s1 & ~kill_curr_d;
|
assign val_thr_s1 = thr_s1 & {4{inst_vld_s1}}; // 4b
|
assign val_thr_s1 = thr_s1 & {4{inst_vld_s1}}; // 4b
|
|
|
// S2 stage
|
// S2 stage
|
| Line 1680... |
Line 1506... |
tinst_vld_s & ~val_thr_f) &
|
tinst_vld_s & ~val_thr_f) &
|
~(clear_s_d1 |
|
~(clear_s_d1 |
|
{4{erb_dtu_ifeterr_d1 & inst_vld_d1 &
|
{4{erb_dtu_ifeterr_d1 & inst_vld_d1 &
|
~rb_stg_e}} & thr_e); // reset
|
~rb_stg_e}} & thr_e); // reset
|
|
|
dffr #(4) tinst_reg(.din (tinst_vld_nxt),
|
dffr_s #(4) tinst_reg(.din (tinst_vld_nxt),
|
.clk (clk),
|
.clk (clk),
|
.rst (fcl_reset),
|
.rst (fcl_reset),
|
.q (tinst_vld_s),
|
.q (tinst_vld_s),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// Does current thread have valid inst in s2
|
// Does current thread have valid inst in s2
|
assign inst_vld_s2 = ((thr_f_crit & tinst_vld_s) == 4'b0000) ?
|
assign inst_vld_s2 = ((thr_f_crit & tinst_vld_s) == 4'b0000) ?
|
{1'b0} : {1'b1};
|
{1'b0} : {1'b1};
|
|
|
| Line 1702... |
Line 1528... |
~(ely_kill_thread_s2 | rb_stg_s);
|
~(ely_kill_thread_s2 | rb_stg_s);
|
|
|
assign running_s2 = inst_vld_s & ~stall_thisthr_f;// f and s2 have
|
assign running_s2 = inst_vld_s & ~stall_thisthr_f;// f and s2 have
|
// same thread
|
// same thread
|
// D stage
|
// D stage
|
dff #(1) rund_ff(.din (running_s2),
|
dff_s #(1) rund_ff(.din (running_s2),
|
.clk (clk),
|
.clk (clk),
|
.q (inst_vld_d),
|
.q (inst_vld_d),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
dff #(1) eivd_ff(.din (running_s2),
|
dff_s #(1) eivd_ff(.din (running_s2),
|
.clk (clk),
|
.clk (clk),
|
.q (inst_vld_d_crit),
|
.q (inst_vld_d_crit),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
assign fcl_erb_inst_issue_d = inst_vld_d & ~intr_vld_d;
|
assign fcl_erb_inst_issue_d = inst_vld_d & ~intr_vld_d;
|
assign running_d = inst_vld_d & ~kill_thread_d & ~rb_stg_d &
|
assign running_d = inst_vld_d & ~kill_thread_d & ~rb_stg_d &
|
~intr_vld_d;
|
~intr_vld_d;
|
|
|
// E stage
|
// E stage
|
dff #(1) rune_ff(.din (running_d),
|
dff_s #(1) rune_ff(.din (running_d),
|
.clk (clk),
|
.clk (clk),
|
.q (inst_vld_e),
|
.q (inst_vld_e),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign running_e = inst_vld_e & ~dtu_inst_anull_e &
|
assign running_e = inst_vld_e & ~dtu_inst_anull_e &
|
~kill_curr_e & ~rb_stg_e &
|
~kill_curr_e & ~rb_stg_e &
|
~(thr_match_em & ifu_tlu_flush_m);
|
~(thr_match_em & ifu_tlu_flush_m);
|
assign inst_vld_qual_e = inst_vld_e & ~rb_stg_e;
|
assign inst_vld_qual_e = inst_vld_e & ~rb_stg_e;
|
assign val_thr_e = thr_e_v2 & {4{inst_vld_qual_e}} & ~late_flush_w2 &
|
assign val_thr_e = thr_e_v2 & {4{inst_vld_qual_e}} & ~late_flush_w2 &
|
~(thr_w & {4{utrap_flush_w}});
|
~(thr_w & {4{utrap_flush_w}});
|
|
|
|
|
// M stage
|
// M stage
|
dff #(1) runm_ff(.din (running_e),
|
dff_s #(1) runm_ff(.din (running_e),
|
.clk (clk),
|
.clk (clk),
|
.q (inst_vld_m),
|
.q (inst_vld_m),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
assign running_m = (inst_vld_m | intr_vld_m) & ~kill_thread_m;
|
assign running_m = (inst_vld_m | intr_vld_m) & ~kill_thread_m;
|
|
|
assign ifu_tlu_inst_vld_m = (inst_vld_m | intr_vld_m) & ~kill_curr_m;
|
assign ifu_tlu_inst_vld_m = (inst_vld_m | intr_vld_m) & ~kill_curr_m;
|
// less critical
|
// less critical
|
// assign ifu_lsu_inst_vld_m = ifu_tlu_inst_vld_m;
|
// assign ifu_lsu_inst_vld_m = ifu_tlu_inst_vld_m;
|
|
|
// W stage
|
// W stage
|
dff #(1) runw_ff(.din (running_m),
|
dff_s #(1) runw_ff(.din (running_m),
|
.q (inst_vld_w),
|
.q (inst_vld_w),
|
.clk (clk), .se (se), .si(), .so());
|
.clk (clk), .se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff #(1) iw_ff(.din (running_m),
|
dff_s #(1) iw_ff(.din (running_m),
|
.q (inst_vld_w_crit),
|
.q (inst_vld_w_crit),
|
.clk (clk), .se (se), .si(), .so());
|
.clk (clk), .se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// synopsys translate_off
|
// synopsys translate_off
|
// wire sas_m,
|
// wire sas_m,
|
// inst_done_w_for_sas;
|
// inst_done_w_for_sas;
|
|
|
| Line 1758... |
Line 1584... |
// ~(exu_ifu_ecc_ce_m & inst_vld_m & ~trap_m);
|
// ~(exu_ifu_ecc_ce_m & inst_vld_m & ~trap_m);
|
|
|
// dff #(1) sasw_ff(.din (sas_m),
|
// dff #(1) sasw_ff(.din (sas_m),
|
// .clk (clk),
|
// .clk (clk),
|
// .q (inst_done_w_for_sas),
|
// .q (inst_done_w_for_sas),
|
// .se (se), .si(), .so());
|
// .se (se), `SIMPLY_RISC_SCANIN, .so());
|
// synopsys translate_on
|
// synopsys translate_on
|
|
|
// need to kill branch by E stage, so qual with rb_stg_X
|
// need to kill branch by E stage, so qual with rb_stg_X
|
assign fcl_dtu_inst_vld_e = inst_vld_e & ~rb_stg_e & ~kill_curr_e;
|
assign fcl_dtu_inst_vld_e = inst_vld_e & ~rb_stg_e & ~kill_curr_e;
|
assign fcl_dtu_intr_vld_e = intr_vld_e & ~rb_stg_e & ~kill_curr_e;
|
assign fcl_dtu_intr_vld_e = intr_vld_e & ~rb_stg_e & ~kill_curr_e;
|
| Line 1777... |
Line 1603... |
assign flush_sonly_qual_e = dtu_fcl_flush_sonly_e & inst_vld_e &
|
assign flush_sonly_qual_e = dtu_fcl_flush_sonly_e & inst_vld_e &
|
// ~dec_fcl_kill4sta_e &
|
// ~dec_fcl_kill4sta_e &
|
~rb_stg_e & ~dtu_inst_anull_e & ~kill_curr_e;
|
~rb_stg_e & ~dtu_inst_anull_e & ~kill_curr_e;
|
|
|
|
|
dff #(1) flshm_ff(.din (flush_sonly_qual_e),
|
dff_s #(1) flshm_ff(.din (flush_sonly_qual_e),
|
.q (flush_sonly_m),
|
.q (flush_sonly_m),
|
.clk (clk),
|
.clk (clk),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff #(1) imflshm_ff(.din (ifq_fcl_flush_sonly_e),
|
dff_s #(1) imflshm_ff(.din (ifq_fcl_flush_sonly_e),
|
.q (ims_flush_sonly_m),
|
.q (ims_flush_sonly_m),
|
.clk (clk),
|
.clk (clk),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
// detect collision between two different types of retractions
|
// detect collision between two different types of retractions
|
assign ims_flush_coll_m = ims_flush_sonly_m & ~canthr_sm &
|
assign ims_flush_coll_m = ims_flush_sonly_m & ~canthr_sm &
|
retract_iferr_e;
|
retract_iferr_e;
|
dff #(1) imflshw_ff(.din (ims_flush_coll_m),
|
dff_s #(1) imflshw_ff(.din (ims_flush_coll_m),
|
.q (ims_flush_sonly_w),
|
.q (ims_flush_sonly_w),
|
.clk (clk),
|
.clk (clk),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
assign ims_flush_coll_w = ims_flush_sonly_w & ~canthr_sw;
|
assign ims_flush_coll_w = ims_flush_sonly_w & ~canthr_sw;
|
assign flush_sonly_qual_m = (ims_flush_sonly_m & ~canthr_sm &
|
assign flush_sonly_qual_m = (ims_flush_sonly_m & ~canthr_sm &
|
~retract_iferr_e |
|
~retract_iferr_e |
|
flush_sonly_m & inst_vld_m & ~kill_local_m &
|
flush_sonly_m & inst_vld_m & ~kill_local_m &
|
~kill_curr_m);
|
~kill_curr_m);
|
| Line 1840... |
Line 1666... |
|
|
assign flush_pipe_w = rb_stg_w | tlu_ifu_flush_pipe_w;
|
assign flush_pipe_w = rb_stg_w | tlu_ifu_flush_pipe_w;
|
// assign part_flush_w = ifu_tlu_flush_w | tlu_ifu_flush_pipe_w;
|
// assign part_flush_w = ifu_tlu_flush_w | tlu_ifu_flush_pipe_w;
|
// assign kill_nextthr_w = thr_match_nw & flush_pipe_w;
|
// assign kill_nextthr_w = thr_match_nw & flush_pipe_w;
|
assign flush_thr_w = thr_w & {4{flush_pipe_w}};
|
assign flush_thr_w = thr_w & {4{flush_pipe_w}};
|
dff #(1) fp_ff(.din (flush_pipe_w),
|
dff_s #(1) fp_ff(.din (flush_pipe_w),
|
.q (flush_pipe_w2),
|
.q (flush_pipe_w2),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// assign clear_s_stage = thr_e & {4{flush_sonly_qual_e}};
|
// assign clear_s_stage = thr_e & {4{flush_sonly_qual_e}};
|
// assign clear_s_stage = trap_thr & {4{trappc_vld_w2}} |
|
// assign clear_s_stage = trap_thr & {4{trappc_vld_w2}} |
|
// {4{dummy_flush_ireg}} |
|
// {4{dummy_flush_ireg}} |
|
// thr_e & {4{flush_sonly_qual_e}};
|
// thr_e & {4{flush_sonly_qual_e}};
|
| Line 1855... |
Line 1681... |
assign canthr_f = thr_e & {4{flush_sonly_qual_e}} |
|
assign canthr_f = thr_e & {4{flush_sonly_qual_e}} |
|
(rb_w2 & ~rb_for_iferr_e) | rb_froms;
|
(rb_w2 & ~rb_for_iferr_e) | rb_froms;
|
|
|
// dff #(4) cls_reg(.din (clear_s_stage),
|
// dff #(4) cls_reg(.din (clear_s_stage),
|
// .q (clear_s_early),
|
// .q (clear_s_early),
|
// .clk (clk), .se(se), .si(), .so());
|
// .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// ***NOTE***
|
// ***NOTE***
|
// Don't use clear_s_d1 to generate fcl_ifq_canthr, since clear_s_d1
|
// Don't use clear_s_d1 to generate fcl_ifq_canthr, since clear_s_d1
|
// includes ifeterr!
|
// includes ifeterr!
|
// first term could be just flush_sonly_m & inst_vld_m & thr_m
|
// first term could be just flush_sonly_m & inst_vld_m & thr_m
|
| Line 1871... |
Line 1697... |
flush_sonly_m}} |
|
flush_sonly_m}} |
|
late_flush_w2 |
|
late_flush_w2 |
|
trap_thr & {4{trappc_vld_w2}};
|
trap_thr & {4{trappc_vld_w2}};
|
|
|
|
|
dff #(4) cm_reg(.din (canthr_f),
|
dff_s #(4) cm_reg(.din (canthr_f),
|
.q (canthr_s_early),
|
.q (canthr_s_early),
|
.clk (clk),
|
.clk (clk),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign canthr_s = canthr_s_early | late_flush_w2 |
|
assign canthr_s = canthr_s_early | late_flush_w2 |
|
trap_thr & {4{trappc_vld_w2}};
|
trap_thr & {4{trappc_vld_w2}};
|
|
|
// assign fcl_ifq_canthr = clear_s_stage | rb_w2 | rb_froms |
|
// assign fcl_ifq_canthr = clear_s_stage | rb_w2 | rb_froms |
|
| Line 1899... |
Line 1725... |
canthr_s[1] & thr_d[1] |
|
canthr_s[1] & thr_d[1] |
|
canthr_s[2] & thr_d[2] |
|
canthr_s[2] & thr_d[2] |
|
canthr_s[3] & thr_d[3]) |
|
canthr_s[3] & thr_d[3]) |
|
thr_match_dw & utrap_flush_w;
|
thr_match_dw & utrap_flush_w;
|
|
|
dff #(4) fpw2_reg(.din (flush_thr_w),
|
dff_s #(4) fpw2_reg(.din (flush_thr_w),
|
.q (late_flush_w2),
|
.q (late_flush_w2),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// assign late_flush_w2 = thr_w2 & {4{flush_pipe_w2}};
|
// assign late_flush_w2 = thr_w2 & {4{flush_pipe_w2}};
|
|
|
assign kill_curr_f = (thr_f_crit[0] & late_flush_w2[0] |
|
assign kill_curr_f = (thr_f_crit[0] & late_flush_w2[0] |
|
thr_f_crit[1] & late_flush_w2[1] |
|
thr_f_crit[1] & late_flush_w2[1] |
|
| Line 1932... |
Line 1758... |
//------------------------------
|
//------------------------------
|
|
|
// force a miss if a fetch and icache is off
|
// force a miss if a fetch and icache is off
|
// forcemiss triggers a fill vld_grequest to L2, so set to zero by default
|
// forcemiss triggers a fill vld_grequest to L2, so set to zero by default
|
assign forcemiss_f = inst_vld_f & ~icache_on_f;
|
assign forcemiss_f = inst_vld_f & ~icache_on_f;
|
dffr #(1) miss_ff(.din (forcemiss_f),
|
dffr_s #(1) miss_ff(.din (forcemiss_f),
|
.clk (clk),
|
.clk (clk),
|
.rst (fcl_reset),
|
.rst (fcl_reset),
|
.q (forcemiss_s1),
|
.q (forcemiss_s1),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
//ooooooooooooooooooooooooooooooooooooooooooooooooooooooo
|
//ooooooooooooooooooooooooooooooooooooooooooooooooooooooo
|
// removed imiss_s_l from this signal for timing fix
|
// removed imiss_s_l from this signal for timing fix
|
// Perf Hit: 0.2% TPCC, 0.4% JBB
|
// Perf Hit: 0.2% TPCC, 0.4% JBB
|
// assign ic_miss_sw_s1 = (~itlb_fcl_imiss_s_l & rdreq_s1 |
|
// assign ic_miss_sw_s1 = (~itlb_fcl_imiss_s_l & rdreq_s1 |
|
| Line 1961... |
Line 1787... |
|
|
// assign fcl_ifq_icmiss_s1 = ic_miss_s1 & ~ely_kill_thread_d; // use buffer
|
// assign fcl_ifq_icmiss_s1 = ic_miss_s1 & ~ely_kill_thread_d; // use buffer
|
assign fcl_ifq_icmiss_s1 = ic_miss_s1; // use buffer
|
assign fcl_ifq_icmiss_s1 = ic_miss_s1; // use buffer
|
|
|
// for perf counters (d1=e)
|
// for perf counters (d1=e)
|
dff #(1) icmd1_ff(.din (icmiss_for_perf),
|
dff_s #(1) icmd1_ff(.din (icmiss_for_perf),
|
.q (ifu_tlu_icmiss_e),
|
.q (ifu_tlu_icmiss_e),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// I$ miss is always to thr_s1. Below we check to see if this is
|
// I$ miss is always to thr_s1. Below we check to see if this is
|
// the same as thr_f (=thr_s2) which is the "current thread"
|
// the same as thr_f (=thr_s2) which is the "current thread"
|
// assign imsto_thisthr_s1 = thr_match_fd & ic_miss_s1;
|
// assign imsto_thisthr_s1 = thr_match_fd & ic_miss_s1;
|
// assign imsto_nextthr_s1 = thr_match_nd & (ic_miss_s1 | tlbmiss_s1);
|
// assign imsto_nextthr_s1 = thr_match_nd & (ic_miss_s1 | tlbmiss_s1);
|
| Line 1984... |
Line 1810... |
// track itlb misses
|
// track itlb misses
|
//------------------------------
|
//------------------------------
|
|
|
// default to hit when camming is turned off
|
// default to hit when camming is turned off
|
assign tlb_cam_miss_f = ~itlb_fcl_tlbmiss_f_l & cam_vld_f;
|
assign tlb_cam_miss_f = ~itlb_fcl_tlbmiss_f_l & cam_vld_f;
|
dff #(1) tlbmsf_ff(.din (tlb_cam_miss_f),
|
dff_s #(1) tlbmsf_ff(.din (tlb_cam_miss_f),
|
.clk (clk),
|
.clk (clk),
|
.q (tlb_cam_miss_s1),
|
.q (tlb_cam_miss_s1),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// tlb miss logic
|
// tlb miss logic
|
// va hole has higher priority than immu miss
|
// va hole has higher priority than immu miss
|
assign tlbmiss_s2 = (({4{tlbmiss_s1 & ~pc_oor_s1 & ~rb_stg_d}} & thr_s1) |
|
assign tlbmiss_s2 = (({4{tlbmiss_s1 & ~pc_oor_s1 & ~rb_stg_d}} & thr_s1) |
|
({4{erb_fcl_itlb_ce_d1 & inst_vld_d1 &
|
({4{erb_fcl_itlb_ce_d1 & inst_vld_d1 &
|
| Line 2005... |
Line 1831... |
// assign tlbmiss_s2 = (({4{tlbmiss_s1 & ~pc_oor_s1 & ~rb_stg_d}} & thr_s1) |
|
// assign tlbmiss_s2 = (({4{tlbmiss_s1 & ~pc_oor_s1 & ~rb_stg_d}} & thr_s1) |
|
// ({4{erb_fcl_itlb_ce_d1 & inst_vld_qual_d1}} & thr_e |
|
// ({4{erb_fcl_itlb_ce_d1 & inst_vld_qual_d1}} & thr_e |
|
// tlbmiss_d & (~thr_e | {4{~inst_vld_qual_e}}) &
|
// tlbmiss_d & (~thr_e | {4{~inst_vld_qual_e}}) &
|
// ~rb_w2) & ~(clear_s_stage); // reset
|
// ~rb_w2) & ~(clear_s_stage); // reset
|
|
|
dffr #(4) tlbmiss_reg(.din (tlbmiss_s2),
|
dffr_s #(4) tlbmiss_reg(.din (tlbmiss_s2),
|
.q (tlbmiss_d),
|
.q (tlbmiss_d),
|
.clk (clk),
|
.clk (clk),
|
.rst (fcl_reset),
|
.rst (fcl_reset),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign immu_fault_f = (thr_f_crit[0] & (tlbmiss_d[0] | inst_acc_vec_d[0]) |
|
assign immu_fault_f = (thr_f_crit[0] & (tlbmiss_d[0] | inst_acc_vec_d[0]) |
|
thr_f_crit[1] & (tlbmiss_d[1] | inst_acc_vec_d[1]) |
|
thr_f_crit[1] & (tlbmiss_d[1] | inst_acc_vec_d[1]) |
|
thr_f_crit[2] & (tlbmiss_d[2] | inst_acc_vec_d[2]) |
|
thr_f_crit[2] & (tlbmiss_d[2] | inst_acc_vec_d[2]) |
|
thr_f_crit[3] & (tlbmiss_d[3] | inst_acc_vec_d[3])) &
|
thr_f_crit[3] & (tlbmiss_d[3] | inst_acc_vec_d[3])) &
|
| Line 2035... |
Line 1861... |
assign immu_miss_qual_d = immu_miss_d & ~kill_thread_d &
|
assign immu_miss_qual_d = immu_miss_d & ~kill_thread_d &
|
~(immu_miss_e & thr_match_de &
|
~(immu_miss_e & thr_match_de &
|
inst_vld_e & ~dtu_inst_anull_e & ~rb_stg_e &
|
inst_vld_e & ~dtu_inst_anull_e & ~rb_stg_e &
|
~kill_curr_e);
|
~kill_curr_e);
|
|
|
dff immu_misse_ff(.din (immu_miss_qual_d),
|
dff_s immu_misse_ff(.din (immu_miss_qual_d),
|
.clk (clk),
|
.clk (clk),
|
.q (immu_miss_e),
|
.q (immu_miss_e),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
|
|
// flop this and send in M
|
// flop this and send in M
|
// assign ifu_tlu_immu_miss_e = immu_miss_e & ~addr_real_e &
|
// assign ifu_tlu_immu_miss_e = immu_miss_e & ~addr_real_e &
|
// inst_vld_e & ~dtu_inst_anull_e & ~rb_stg_e;
|
// inst_vld_e & ~dtu_inst_anull_e & ~rb_stg_e;
|
| Line 2051... |
Line 1877... |
// assign immu_miss_qual_e = immu_miss_e & //~addr_real_e &
|
// assign immu_miss_qual_e = immu_miss_e & //~addr_real_e &
|
// // ~(immu_miss_m & thr_match_em) &
|
// // ~(immu_miss_m & thr_match_em) &
|
// inst_vld_e & ~dtu_inst_anull_e & ~rb_stg_e;
|
// inst_vld_e & ~dtu_inst_anull_e & ~rb_stg_e;
|
|
|
// dff #(1) immu_msm_ff(.din (immu_miss_qual_e),
|
// dff #(1) immu_msm_ff(.din (immu_miss_qual_e),
|
dff #(1) immu_msm_ff(.din (immu_miss_e),
|
dff_s #(1) immu_msm_ff(.din (immu_miss_e),
|
.q (immu_miss_m),
|
.q (immu_miss_m),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign ifu_tlu_immu_miss_m = immu_miss_m & inst_vld_m & ~kill_curr_m;
|
assign ifu_tlu_immu_miss_m = immu_miss_m & inst_vld_m & ~kill_curr_m;
|
|
|
assign addr_real_e = (itlb_addr_real[0] & thr_e[0] |
|
assign addr_real_e = (itlb_addr_real[0] & thr_e[0] |
|
itlb_addr_real[1] & thr_e[1] |
|
itlb_addr_real[1] & thr_e[1] |
|
| Line 2066... |
Line 1892... |
|
|
// store tlbmiss state for NIR
|
// store tlbmiss state for NIR
|
assign nir_tlbmiss_next = ({4{tlb_cam_miss_s1 & ~stall_s1}} & thr_s1 |
|
assign nir_tlbmiss_next = ({4{tlb_cam_miss_s1 & ~stall_s1}} & thr_s1 |
|
nir_tlbmiss_vec & (~thr_s1 | {4{stall_s1}}));
|
nir_tlbmiss_vec & (~thr_s1 | {4{stall_s1}}));
|
|
|
dffr #(4) nirtlbm_reg(.din (nir_tlbmiss_next),
|
dffr_s #(4) nirtlbm_reg(.din (nir_tlbmiss_next),
|
.clk (clk),
|
.clk (clk),
|
.q (nir_tlbmiss_vec),
|
.q (nir_tlbmiss_vec),
|
.rst (fcl_reset),
|
.rst (fcl_reset),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign nir_tlbmiss_s1 = (nir_tlbmiss_vec[0] & thr_s1[0] |
|
assign nir_tlbmiss_s1 = (nir_tlbmiss_vec[0] & thr_s1[0] |
|
nir_tlbmiss_vec[1] & thr_s1[1] |
|
nir_tlbmiss_vec[1] & thr_s1[1] |
|
nir_tlbmiss_vec[2] & thr_s1[2] |
|
nir_tlbmiss_vec[2] & thr_s1[2] |
|
nir_tlbmiss_vec[3] & thr_s1[3]);
|
nir_tlbmiss_vec[3] & thr_s1[3]);
|
| Line 2095... |
Line 1921... |
assign fcl_fdp_mask32b_f = (thr_f[0] & pstate_am_d1[0] |
|
assign fcl_fdp_mask32b_f = (thr_f[0] & pstate_am_d1[0] |
|
thr_f[1] & pstate_am_d1[1] |
|
thr_f[1] & pstate_am_d1[1] |
|
thr_f[2] & pstate_am_d1[2] |
|
thr_f[2] & pstate_am_d1[2] |
|
thr_f[3] & pstate_am_d1[3]);
|
thr_f[3] & pstate_am_d1[3]);
|
|
|
dff #(1) amd_ff(.din (fcl_fdp_mask32b_f),
|
dff_s #(1) amd_ff(.din (fcl_fdp_mask32b_f),
|
.q (fcl_fdp_addr_mask_d),
|
.q (fcl_fdp_addr_mask_d),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// keep track of whether pc is outside va hole
|
// keep track of whether pc is outside va hole
|
assign set_oor_m = exu_ifu_va_oor_m & brtaken_m & ~addr_mask_32b_m;
|
assign set_oor_m = exu_ifu_va_oor_m & brtaken_m & ~addr_mask_32b_m;
|
assign fcl_fdp_pcoor_vec_f = fdp_fcl_pc_oor_vec_f | {4{set_oor_m}} & thr_m;
|
assign fcl_fdp_pcoor_vec_f = fdp_fcl_pc_oor_vec_f | {4{set_oor_m}} & thr_m;
|
|
|
| Line 2109... |
Line 1935... |
thr_f[1] & fcl_fdp_pcoor_vec_f[1] |
|
thr_f[1] & fcl_fdp_pcoor_vec_f[1] |
|
thr_f[2] & fcl_fdp_pcoor_vec_f[2] |
|
thr_f[2] & fcl_fdp_pcoor_vec_f[2] |
|
thr_f[3] & fcl_fdp_pcoor_vec_f[3]);
|
thr_f[3] & fcl_fdp_pcoor_vec_f[3]);
|
|
|
assign pc_oor_f = fcl_fdp_pcoor_f & ~part_stall_thisthr_f;
|
assign pc_oor_f = fcl_fdp_pcoor_f & ~part_stall_thisthr_f;
|
dff oors1_ff(.din (pc_oor_f),
|
dff_s oors1_ff(.din (pc_oor_f),
|
.q (pc_oor_s1),
|
.q (pc_oor_s1),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// track privilege mode of current page
|
// track privilege mode of current page
|
assign priv_mode_f = (thr_f[0] & tlu_lsu_pstate_priv[0] |
|
assign priv_mode_f = (thr_f[0] & tlu_lsu_pstate_priv[0] |
|
thr_f[1] & tlu_lsu_pstate_priv[1] |
|
thr_f[1] & tlu_lsu_pstate_priv[1] |
|
thr_f[2] & tlu_lsu_pstate_priv[2] |
|
thr_f[2] & tlu_lsu_pstate_priv[2] |
|
thr_f[3] & tlu_lsu_pstate_priv[3]);
|
thr_f[3] & tlu_lsu_pstate_priv[3]);
|
|
|
dff #(1) priv_ff(.din (priv_mode_f),
|
dff_s #(1) priv_ff(.din (priv_mode_f),
|
.q (priv_mode_s1),
|
.q (priv_mode_s1),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// s1 and d are the same thread
|
// s1 and d are the same thread
|
assign fcl_dtu_privmode_d = priv_mode_s1;
|
assign fcl_dtu_privmode_d = priv_mode_s1;
|
|
|
// hyper privilege
|
// hyper privilege
|
| Line 2137... |
Line 1963... |
assign hpriv_mode_w = (thr_w[0] & tlu_hpstate_priv[0] |
|
assign hpriv_mode_w = (thr_w[0] & tlu_hpstate_priv[0] |
|
thr_w[1] & tlu_hpstate_priv[1] |
|
thr_w[1] & tlu_hpstate_priv[1] |
|
thr_w[2] & tlu_hpstate_priv[2] |
|
thr_w[2] & tlu_hpstate_priv[2] |
|
thr_w[3] & tlu_hpstate_priv[3]);
|
thr_w[3] & tlu_hpstate_priv[3]);
|
|
|
dff #(1) hprivd_ff(.din (hpriv_mode_f),
|
dff_s #(1) hprivd_ff(.din (hpriv_mode_f),
|
.q (hpriv_mode_s1),
|
.q (hpriv_mode_s1),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign fcl_dtu_hprivmode_d = hpriv_mode_s1;
|
assign fcl_dtu_hprivmode_d = hpriv_mode_s1;
|
|
|
dff #(1) hprivw2_ff(.din (hpriv_mode_w),
|
dff_s #(1) hprivw2_ff(.din (hpriv_mode_w),
|
.q (hpriv_mode_w2),
|
.q (hpriv_mode_w2),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
assign fcl_dtu_hprivmode_w2 = hpriv_mode_w2;
|
assign fcl_dtu_hprivmode_w2 = hpriv_mode_w2;
|
|
|
// determine if priv page has been accessed in non priv mode
|
// determine if priv page has been accessed in non priv mode
|
// or if we have fallen into the VA hole
|
// or if we have fallen into the VA hole
|
assign inst_acc_exc_s1 = (priv_inst_s1 & ~(priv_mode_s1 | hpriv_mode_s1) &
|
assign inst_acc_exc_s1 = (priv_inst_s1 & ~(priv_mode_s1 | hpriv_mode_s1) &
|
| Line 2166... |
Line 1992... |
({4{inst_acc_exc_d}} & rb_fromd & ~rb_frome) |
|
({4{inst_acc_exc_d}} & rb_fromd & ~rb_frome) |
|
inst_acc_vec_d & (~thr_d | {4{~inst_vld_d}}) &
|
inst_acc_vec_d & (~thr_d | {4{~inst_vld_d}}) &
|
~rb_w2) &
|
~rb_w2) &
|
~(clear_s_d1);
|
~(clear_s_d1);
|
|
|
dffr #(4) instaccd_reg(.din (inst_acc_vec_s2),
|
dffr_s #(4) instaccd_reg(.din (inst_acc_vec_s2),
|
.q (inst_acc_vec_d),
|
.q (inst_acc_vec_d),
|
.rst (fcl_reset),
|
.rst (fcl_reset),
|
.clk (clk), .se (se), .si(), .so());
|
.clk (clk), .se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign inst_acc_exc_d = (thr_d[0] & inst_acc_vec_d[0] |
|
assign inst_acc_exc_d = (thr_d[0] & inst_acc_vec_d[0] |
|
thr_d[1] & inst_acc_vec_d[1] |
|
thr_d[1] & inst_acc_vec_d[1] |
|
thr_d[2] & inst_acc_vec_d[2] |
|
thr_d[2] & inst_acc_vec_d[2] |
|
thr_d[3] & inst_acc_vec_d[3]);
|
thr_d[3] & inst_acc_vec_d[3]);
|
|
|
dff #(1) instacce_ff(.din (inst_acc_exc_d),
|
dff_s #(1) instacce_ff(.din (inst_acc_exc_d),
|
.q (inst_acc_exc_e),
|
.q (inst_acc_exc_e),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// TLU needs to know if this is a priv violtn
|
// TLU needs to know if this is a priv violtn
|
assign priv_violtn_e = inst_acc_exc_e & ~fdp_fcl_pc_oor_e;
|
assign priv_violtn_e = inst_acc_exc_e & ~fdp_fcl_pc_oor_e;
|
dff #(1) privm_ff(.din (priv_violtn_e),
|
dff_s #(1) privm_ff(.din (priv_violtn_e),
|
.q (priv_violtn_m),
|
.q (priv_violtn_m),
|
.clk (clk), .se (se), .si(), .so());
|
.clk (clk), .se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign ifu_tlu_priv_violtn_m = priv_violtn_m & inst_vld_m & ~kill_curr_m;
|
assign ifu_tlu_priv_violtn_m = priv_violtn_m & inst_vld_m & ~kill_curr_m;
|
|
|
// NIR privilege bit
|
// NIR privilege bit
|
assign next_nir_privvec = {4{itlb_fcl_priv_s1 & ~stall_s1 &
|
assign next_nir_privvec = {4{itlb_fcl_priv_s1 & ~stall_s1 &
|
cam_vld_s1}} & thr_s1 |
|
cam_vld_s1}} & thr_s1 |
|
nir_privvec & (~thr_s1 | {4{stall_s1}});
|
nir_privvec & (~thr_s1 | {4{stall_s1}});
|
|
|
dffr #(4) nir_priv_reg(.din (next_nir_privvec),
|
dffr_s #(4) nir_priv_reg(.din (next_nir_privvec),
|
.q (nir_privvec),
|
.q (nir_privvec),
|
.rst (fcl_reset),
|
.rst (fcl_reset),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign nir_priv_s1 = (nir_privvec[0] & thr_s1[0] |
|
assign nir_priv_s1 = (nir_privvec[0] & thr_s1[0] |
|
nir_privvec[1] & thr_s1[1] |
|
nir_privvec[1] & thr_s1[1] |
|
nir_privvec[2] & thr_s1[2] |
|
nir_privvec[2] & thr_s1[2] |
|
nir_privvec[3] & thr_s1[3]);
|
nir_privvec[3] & thr_s1[3]);
|
| Line 2225... |
Line 2051... |
assign fcl_erb_immuevld_s1 = ely_running_s1 & cam_vld_s1;
|
assign fcl_erb_immuevld_s1 = ely_running_s1 & cam_vld_s1;
|
|
|
// assign fcl_erb_ttevld_s1 = asird_s & rdtag_s;
|
// assign fcl_erb_ttevld_s1 = asird_s & rdtag_s;
|
// assign fcl_erb_tdevld_s1 = asird_s & ~rdtag_s;
|
// assign fcl_erb_tdevld_s1 = asird_s & ~rdtag_s;
|
|
|
dff #(1) d1vld_ff(.din (running_s1),
|
dff_s #(1) d1vld_ff(.din (running_s1),
|
.q (inst_vld_d1),
|
.q (inst_vld_d1),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
// assign inst_vld_qual_d1 = inst_vld_d1 & ~kill_thread_e &
|
// assign inst_vld_qual_d1 = inst_vld_d1 & ~kill_thread_e &
|
// ~flush_sonly_qual_e & ~rb_stg_e;
|
// ~flush_sonly_qual_e & ~rb_stg_e;
|
assign fcl_erb_inst_vld_d1 = inst_vld_d1;
|
assign fcl_erb_inst_vld_d1 = inst_vld_d1;
|
|
|
|
|
// ifetch unc. error
|
// ifetch unc. error
|
assign ifet_ue_vec_d1 = (erb_fcl_ifet_uevec_d1 |
|
assign ifet_ue_vec_d1 = (erb_fcl_ifet_uevec_d1 |
|
ifet_ue_vec_e & ~val_thr_e) & // reset
|
ifet_ue_vec_e & ~val_thr_e) & // reset
|
~(clear_s_d1); // wins
|
~(clear_s_d1); // wins
|
|
|
dffr #(4) ifuerr_reg(.din (ifet_ue_vec_d1),
|
dffr_s #(4) ifuerr_reg(.din (ifet_ue_vec_d1),
|
.q (ifet_ue_vec_e),
|
.q (ifet_ue_vec_e),
|
.rst (fcl_reset),
|
.rst (fcl_reset),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign ifet_ue_e = (ifet_ue_vec_e[0] & thr_e[0] |
|
assign ifet_ue_e = (ifet_ue_vec_e[0] & thr_e[0] |
|
ifet_ue_vec_e[1] & thr_e[1] |
|
ifet_ue_vec_e[1] & thr_e[1] |
|
ifet_ue_vec_e[2] & thr_e[2] |
|
ifet_ue_vec_e[2] & thr_e[2] |
|
ifet_ue_vec_e[3] & thr_e[3]);
|
ifet_ue_vec_e[3] & thr_e[3]);
|
| Line 2257... |
Line 2083... |
// Determine if we are in Trap Level 0
|
// Determine if we are in Trap Level 0
|
assign tlzero_s2 = (thr_f[0] & tlzero_vec_d1[0] |
|
assign tlzero_s2 = (thr_f[0] & tlzero_vec_d1[0] |
|
thr_f[1] & tlzero_vec_d1[1] |
|
thr_f[1] & tlzero_vec_d1[1] |
|
thr_f[2] & tlzero_vec_d1[2] |
|
thr_f[2] & tlzero_vec_d1[2] |
|
thr_f[3] & tlzero_vec_d1[3]);
|
thr_f[3] & tlzero_vec_d1[3]);
|
dff #(1) tlzd_ff(.din (tlzero_s2),
|
dff_s #(1) tlzd_ff(.din (tlzero_s2),
|
.q (fcl_dtu_tlzero_d),
|
.q (fcl_dtu_tlzero_d),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// Collect all IFU traps
|
// Collect all IFU traps
|
assign trap_e = (immu_miss_e | inst_acc_exc_e | dtu_fcl_illinst_e |
|
assign trap_e = (immu_miss_e | inst_acc_exc_e | dtu_fcl_illinst_e |
|
dtu_fcl_fpdis_e | dtu_fcl_privop_e | ifet_ue_e |
|
dtu_fcl_fpdis_e | dtu_fcl_privop_e | ifet_ue_e |
|
dtu_fcl_imask_hit_e | dtu_fcl_sir_inst_e) &
|
dtu_fcl_imask_hit_e | dtu_fcl_sir_inst_e) &
|
inst_vld_e;
|
inst_vld_e;
|
|
|
dff trapm_ff(.din (trap_e),
|
dff_s trapm_ff(.din (trap_e),
|
.q (trap_m),
|
.q (trap_m),
|
.clk (clk),
|
.clk (clk),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign no_iftrap_m = ~ifu_tlu_ttype_vld_m;
|
assign no_iftrap_m = ~ifu_tlu_ttype_vld_m;
|
dff trapw_ff(.din (no_iftrap_m),
|
dff_s trapw_ff(.din (no_iftrap_m),
|
.q (no_iftrap_w),
|
.q (no_iftrap_w),
|
.clk (clk),
|
.clk (clk),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// south is very critical
|
// south is very critical
|
assign ifu_tlu_ttype_vld_m = (trap_m & inst_vld_m |
|
assign ifu_tlu_ttype_vld_m = (trap_m & inst_vld_m |
|
disr_trap_m) & ~kill_curr_m & ~kill_local_m;
|
disr_trap_m) & ~kill_curr_m & ~kill_local_m;
|
// less critical going east
|
// less critical going east
|
| Line 2334... |
Line 2160... |
assign ttype_sel_fpdis_e = ~fdp_fcl_pc_oor_e & ~immu_miss_e &
|
assign ttype_sel_fpdis_e = ~fdp_fcl_pc_oor_e & ~immu_miss_e &
|
~inst_acc_exc_e & ~dtu_fcl_illinst_e &
|
~inst_acc_exc_e & ~dtu_fcl_illinst_e &
|
dtu_fcl_fpdis_e;
|
dtu_fcl_fpdis_e;
|
|
|
// mux in the trap type
|
// mux in the trap type
|
assign ttype_e[8:0] = ttype_sel_unc_err_e ? 9'h078 :
|
assign ttype_e[8:0] = ttype_sel_unc_err_e ? `DATA_ERR :
|
ttype_sel_hstk_cmp_e ? 9'h05e :
|
ttype_sel_hstk_cmp_e ? `HSTICK_CMP :
|
ttype_sel_spuma_e ? 9'h074 :
|
ttype_sel_spuma_e ? `SPU_MAINT :
|
ttype_sel_spuenc_e ? 9'h070 :
|
ttype_sel_spuenc_e ? `SPU_ENCINT :
|
ttype_sel_corr_err_e ? 9'h063 :
|
ttype_sel_corr_err_e ? `CORR_ECC_ERR :
|
ttype_sel_res_err_e ? 9'h07e :
|
ttype_sel_res_err_e ? `RESUMABLE_ERR :
|
|
|
ttype_sel_pcoor_e ? 9'h008 :
|
ttype_sel_pcoor_e ? `INST_ACC_EXC :
|
ttype_sel_immu_miss_e ? 9'h064 :
|
ttype_sel_immu_miss_e ? `FAST_MMU_MS :
|
ttype_sel_real_trans_e ? 9'h03e :
|
ttype_sel_real_trans_e ? `REAL_TRANS_MS :
|
ttype_sel_icache_err_e ? 9'h00a :
|
ttype_sel_icache_err_e ? `INST_ACC_ERR :
|
ttype_sel_priv_viol_e ? 9'h008 :
|
ttype_sel_priv_viol_e ? `INST_ACC_EXC :
|
ttype_sel_ibe_e ? 9'h076 :
|
ttype_sel_ibe_e ? `INST_BRK_PT :
|
ttype_sel_privop_e ? 9'h011 :
|
ttype_sel_privop_e ? `PRIV_OPC :
|
ttype_sel_illinst_e ? 9'h010 :
|
ttype_sel_illinst_e ? `ILL_INST :
|
ttype_sel_sir_e ? 9'h004 :
|
ttype_sel_sir_e ? `SIR :
|
ttype_sel_fpdis_e ? 9'h020 :
|
ttype_sel_fpdis_e ? `FP_DISABLED :
|
9'h1ff;
|
9'h1ff;
|
|
|
dff #(9) ttype_reg(.din (ttype_e[8:0]),
|
dff_s #(9) ttype_reg(.din (ttype_e[8:0]),
|
.q (ifu_tlu_ttype_m[8:0]),
|
.q (ifu_tlu_ttype_m[8:0]),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
//------------------------------
|
//------------------------------
|
// Interrupts and Resets
|
// Interrupts and Resets
|
//------------------------------
|
//------------------------------
|
// Process resets to see if they are sync or async
|
// Process resets to see if they are sync or async
|
| Line 2370... |
Line 2196... |
|
|
// assign async_rst_i2 = tlu_ifu_rstthr_i2 & {4{tlu_ifu_rstint_i2}} &
|
// assign async_rst_i2 = tlu_ifu_rstthr_i2 & {4{tlu_ifu_rstint_i2}} &
|
assign async_rst_i3 = (rstint_i3 | nuke_thr_i3 | resumint_i3) &
|
assign async_rst_i3 = (rstint_i3 | nuke_thr_i3 | resumint_i3) &
|
~dtu_fcl_thr_active & ~intr_in_pipe;
|
~dtu_fcl_thr_active & ~intr_in_pipe;
|
|
|
dff #(4) asyrst4_reg(.din (async_rst_i3),
|
dff_s #(4) asyrst4_reg(.din (async_rst_i3),
|
.q (async_rst_i4),
|
.q (async_rst_i4),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// stall pipe before switching in rst thread
|
// stall pipe before switching in rst thread
|
assign rst_stallreq_d0 = (|async_rst_i4[3:0]);
|
assign rst_stallreq_d0 = (|async_rst_i4[3:0]);
|
assign rst_stallreq = rst_stallreq_d0 | rst_stallreq_d1 | rst_stallreq_d2;
|
assign rst_stallreq = rst_stallreq_d0 | rst_stallreq_d1 | rst_stallreq_d2;
|
|
|
dff #(2) stlreq_reg(.din ({lsu_ifu_stallreq,
|
dff_s #(2) stlreq_reg(.din ({lsu_ifu_stallreq,
|
ffu_ifu_stallreq}),
|
ffu_ifu_stallreq}),
|
.q ({lsu_stallreq_d1,
|
.q ({lsu_stallreq_d1,
|
ffu_stallreq_d1}),
|
ffu_stallreq_d1}),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign all_stallreq = ifq_fcl_stallreq | lsu_stallreq_d1 |
|
assign all_stallreq = ifq_fcl_stallreq | lsu_stallreq_d1 |
|
ffu_stallreq_d1 | itlb_starv_alert;
|
ffu_stallreq_d1 | itlb_starv_alert;
|
|
|
// leave out stall from ifq which goes directly to swl
|
// leave out stall from ifq which goes directly to swl
|
| Line 2402... |
Line 2228... |
async_rst_i4[2];
|
async_rst_i4[2];
|
assign rstint_penc[3] = ~async_rst_i4[0] & ~async_rst_i4[1] &
|
assign rstint_penc[3] = ~async_rst_i4[0] & ~async_rst_i4[1] &
|
~async_rst_i4[2];
|
~async_rst_i4[2];
|
|
|
// BF - switch in rst thread
|
// BF - switch in rst thread
|
dff #(1) asyncr1_ff(.din (rst_stallreq_d0),
|
dff_s #(1) asyncr1_ff(.din (rst_stallreq_d0),
|
.q (rst_stallreq_d1),
|
.q (rst_stallreq_d1),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
assign arst_vld_f_l = ~arst_vld_f;
|
assign arst_vld_f_l = ~arst_vld_f;
|
assign arst_vld_s_l = ~arst_vld_s;
|
assign arst_vld_s_l = ~arst_vld_s;
|
bw_u1_nand3_4x UZsize_rstsw_n3(.z (rst_sw_bf_l),
|
bw_u1_nand3_4x UZsize_rstsw_n3(.z (rst_sw_bf_l),
|
.a (arst_vld_f_l),
|
.a (arst_vld_f_l),
|
.b (arst_vld_s_l),
|
.b (arst_vld_s_l),
|
| Line 2417... |
Line 2243... |
|
|
// double check if asyn intrs are still valid
|
// double check if asyn intrs are still valid
|
assign sw_for_real_rst_bf = rst_sw_bf & rst_stallreq_d0;
|
assign sw_for_real_rst_bf = rst_sw_bf & rst_stallreq_d0;
|
|
|
// F
|
// F
|
dff #(1) asyncr2_ff(.din (sw_for_real_rst_bf),
|
dff_s #(1) asyncr2_ff(.din (sw_for_real_rst_bf),
|
.q (rst_stallreq_d2),
|
.q (rst_stallreq_d2),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
// assign arst_vld_f = rst_stallreq_d2 & any_rstnuke_f;
|
// assign arst_vld_f = rst_stallreq_d2 & any_rstnuke_f;
|
assign arst_vld_f = rst_stallreq_d2;
|
assign arst_vld_f = rst_stallreq_d2;
|
|
|
// hold thread till reset of curr thread is processed
|
// hold thread till reset of curr thread is processed
|
// assign rst_thr_bf = arst_vld_f ? thr_f : rstint_penc;
|
// assign rst_thr_bf = arst_vld_f ? thr_f : rstint_penc;
|
|
|
// S issue to pipe
|
// S issue to pipe
|
dff #(1) rstvlds_ff(.din (arst_vld_f),
|
dff_s #(1) rstvlds_ff(.din (arst_vld_f),
|
.q (arst_vld_s),
|
.q (arst_vld_s),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
assign async_intr_vld_s = arst_vld_s & ~kill_intr_f; // & any_rstnuke_f
|
assign async_intr_vld_s = arst_vld_s & ~kill_intr_f; // & any_rstnuke_f
|
|
|
|
|
//
|
//
|
// thread wise interrupts
|
// thread wise interrupts
|
| Line 2463... |
Line 2289... |
assign next_ueint_i2 = erb_fcl_ue_trapvec |
|
assign next_ueint_i2 = erb_fcl_ue_trapvec |
|
ueint_i3 & (~(thr_w & {4{ueint_qual_w}}));
|
ueint_i3 & (~(thr_w & {4{ueint_qual_w}}));
|
|
|
// From Farnad: tid is ready several cycles before everything else
|
// From Farnad: tid is ready several cycles before everything else
|
// I will assume 1 cycle before in the ifu
|
// I will assume 1 cycle before in the ifu
|
dff #(2) sptid_reg(.din (spu_ifu_ttype_tid_w2),
|
dff_s #(2) sptid_reg(.din (spu_ifu_ttype_tid_w2),
|
.q (spu_tid_w2),
|
.q (spu_tid_w2),
|
.clk (clk), .se(se), .so(), .si());
|
.clk (clk), .se(se), .so(), `SIMPLY_RISC_SCANIN);
|
|
|
assign spu_thr[0] = ~spu_tid_w2[1] & ~spu_tid_w2[0];
|
assign spu_thr[0] = ~spu_tid_w2[1] & ~spu_tid_w2[0];
|
assign spu_thr[1] = ~spu_tid_w2[1] & spu_tid_w2[0];
|
assign spu_thr[1] = ~spu_tid_w2[1] & spu_tid_w2[0];
|
assign spu_thr[2] = spu_tid_w2[1] & ~spu_tid_w2[0];
|
assign spu_thr[2] = spu_tid_w2[1] & ~spu_tid_w2[0];
|
assign spu_thr[3] = spu_tid_w2[1] & spu_tid_w2[0];
|
assign spu_thr[3] = spu_tid_w2[1] & spu_tid_w2[0];
|
| Line 2481... |
Line 2307... |
assign next_spuint0_i2 = {4{spu_ifu_ttype_vld_w2 & ~spu_ifu_ttype_w2}} &
|
assign next_spuint0_i2 = {4{spu_ifu_ttype_vld_w2 & ~spu_ifu_ttype_w2}} &
|
spu_thr & ~erb_fcl_spu_uetrap |
|
spu_thr & ~erb_fcl_spu_uetrap |
|
spuint0_i3 & ~({4{spuint0_w}} & thr_w);
|
spuint0_i3 & ~({4{spuint0_w}} & thr_w);
|
|
|
|
|
dffr #(4) rst_reg(.din (next_rst_i2),
|
dffr_s #(4) rst_reg(.din (next_rst_i2),
|
.q (rstint_i3),
|
.q (rstint_i3),
|
.clk (clk),
|
.clk (clk),
|
.rst (fcl_reset),
|
.rst (fcl_reset),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dffr #(4) resum_reg(.din (next_resum_i2),
|
dffr_s #(4) resum_reg(.din (next_resum_i2),
|
.q (resumint_i3),
|
.q (resumint_i3),
|
.clk (clk),
|
.clk (clk),
|
.rst (fcl_reset),
|
.rst (fcl_reset),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dffr #(4) nuke_reg(.din (next_nuke_i2),
|
dffr_s #(4) nuke_reg(.din (next_nuke_i2),
|
.q (nuke_thr_i3),
|
.q (nuke_thr_i3),
|
.rst (fcl_reset),
|
.rst (fcl_reset),
|
.clk (clk),
|
.clk (clk),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dffr #(4) sfti_reg(.din (next_sftint_i2),
|
dffr_s #(4) sfti_reg(.din (next_sftint_i2),
|
.q (sftint_i3),
|
.q (sftint_i3),
|
.rst (fcl_reset),
|
.rst (fcl_reset),
|
.clk (clk), .se (se), .si(), .so());
|
.clk (clk), .se (se), `SIMPLY_RISC_SCANIN, .so());
|
dffr #(4) hstki_reg(.din (next_hintp_i2),
|
dffr_s #(4) hstki_reg(.din (next_hintp_i2),
|
.q (hintp_i3),
|
.q (hintp_i3),
|
.rst (fcl_reset),
|
.rst (fcl_reset),
|
.clk (clk), .se (se), .si(), .so());
|
.clk (clk), .se (se), `SIMPLY_RISC_SCANIN, .so());
|
dffr #(4) reri_reg(.din (next_rerr_i2),
|
dffr_s #(4) reri_reg(.din (next_rerr_i2),
|
.q (rerr_i3),
|
.q (rerr_i3),
|
.rst (fcl_reset),
|
.rst (fcl_reset),
|
.clk (clk), .se (se), .si(), .so());
|
.clk (clk), .se (se), `SIMPLY_RISC_SCANIN, .so());
|
dffr #(4) hwi_reg(.din (next_hwint_i3),
|
dffr_s #(4) hwi_reg(.din (next_hwint_i3),
|
.q (hwint_i4),
|
.q (hwint_i4),
|
.rst (fcl_reset),
|
.rst (fcl_reset),
|
.clk (clk), .se (se), .si(), .so());
|
.clk (clk), .se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dffr #(4) spui0_reg(.din (next_spuint0_i2),
|
dffr_s #(4) spui0_reg(.din (next_spuint0_i2),
|
.q (spuint0_i3),
|
.q (spuint0_i3),
|
.rst (fcl_reset),
|
.rst (fcl_reset),
|
.clk (clk), .se (se), .si(), .so());
|
.clk (clk), .se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dffr #(4) spui1_reg(.din (next_spuint1_i2),
|
dffr_s #(4) spui1_reg(.din (next_spuint1_i2),
|
.q (spuint1_i3),
|
.q (spuint1_i3),
|
.rst (fcl_reset),
|
.rst (fcl_reset),
|
.clk (clk), .se (se), .si(), .so());
|
.clk (clk), .se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dffr #(4) cei_reg(.din (next_ceint_i2),
|
dffr_s #(4) cei_reg(.din (next_ceint_i2),
|
.q (ceint_i3),
|
.q (ceint_i3),
|
.rst (fcl_reset),
|
.rst (fcl_reset),
|
.clk (clk), .se (se), .si(), .so());
|
.clk (clk), .se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dffr #(4) uei_reg(.din (next_ueint_i2),
|
dffr_s #(4) uei_reg(.din (next_ueint_i2),
|
.q (ueint_i3),
|
.q (ueint_i3),
|
.rst (fcl_reset),
|
.rst (fcl_reset),
|
.clk (clk), .se (se), .si(), .so());
|
.clk (clk), .se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign supv_int_en = (~tlu_hpstate_priv | ~tlu_hpstate_enb) &
|
assign supv_int_en = (~tlu_hpstate_priv | ~tlu_hpstate_enb) &
|
tlu_ifu_pstate_ie & dtu_fcl_thr_active;
|
tlu_ifu_pstate_ie & dtu_fcl_thr_active;
|
assign hypv_int_en = ~tlu_hpstate_priv & tlu_hpstate_enb |
|
assign hypv_int_en = ~tlu_hpstate_priv & tlu_hpstate_enb |
|
tlu_ifu_pstate_ie & dtu_fcl_thr_active;
|
tlu_ifu_pstate_ie & dtu_fcl_thr_active;
|
|
|
dff #(4) spvie_ff(.din (supv_int_en),
|
dff_s #(4) spvie_ff(.din (supv_int_en),
|
.q (supv_int_en_d1),
|
.q (supv_int_en_d1),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff #(4) hpvie_ff(.din (hypv_int_en),
|
dff_s #(4) hpvie_ff(.din (hypv_int_en),
|
.q (hypv_int_en_d1),
|
.q (hypv_int_en_d1),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// force an interrupt by putting nop on pipe
|
// force an interrupt by putting nop on pipe
|
// use this signal instead of hw_int_s to help with crit path
|
// use this signal instead of hw_int_s to help with crit path
|
assign supv_masked_intr_s = (sftint_i3 |
|
assign supv_masked_intr_s = (sftint_i3 |
|
rerr_i3);
|
rerr_i3);
|
| Line 2567... |
Line 2393... |
// keep track of rolled back interrupts
|
// keep track of rolled back interrupts
|
assign intr_pending_nxt = (({4{intr_vld_e}} & rb_frome) |
|
assign intr_pending_nxt = (({4{intr_vld_e}} & rb_frome) |
|
({4{intr_vld_d}} & rb_fromd & ~rb_frome) |
|
({4{intr_vld_d}} & rb_fromd & ~rb_frome) |
|
intr_pending_s) & ~clear_s_d1;
|
intr_pending_s) & ~clear_s_d1;
|
|
|
dffr #(4) ipend_reg(.din (intr_pending_nxt),
|
dffr_s #(4) ipend_reg(.din (intr_pending_nxt),
|
.q (intr_pending_s),
|
.q (intr_pending_s),
|
.rst (fcl_reset),
|
.rst (fcl_reset),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign any_intr_vec_f = (supv_masked_intr_s & supv_int_en_d1 |
|
assign any_intr_vec_f = (supv_masked_intr_s & supv_int_en_d1 |
|
hypv_masked_intr_s & hypv_int_en_d1 |
|
hypv_masked_intr_s & hypv_int_en_d1 |
|
intr_pending_s |
|
intr_pending_s |
|
rstint_i3 |
|
rstint_i3 |
|
resumint_i3 |
|
resumint_i3 |
|
nuke_thr_i3);
|
nuke_thr_i3);
|
|
|
dff #(4) anyints_reg(.din (any_intr_vec_f),
|
dff_s #(4) anyints_reg(.din (any_intr_vec_f),
|
.q (any_intr_vec_s),
|
.q (any_intr_vec_s),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign force_intr_s = (thr_f_crit[0] & any_intr_vec_s[0] |
|
assign force_intr_s = (thr_f_crit[0] & any_intr_vec_s[0] |
|
thr_f_crit[1] & any_intr_vec_s[1] |
|
thr_f_crit[1] & any_intr_vec_s[1] |
|
thr_f_crit[2] & any_intr_vec_s[2] |
|
thr_f_crit[2] & any_intr_vec_s[2] |
|
thr_f_crit[3] & any_intr_vec_s[3]) &
|
thr_f_crit[3] & any_intr_vec_s[3]) &
|
| Line 2596... |
Line 2422... |
// - since the VA hole marker is lost once the intr is taken
|
// - since the VA hole marker is lost once the intr is taken
|
assign intr_vld_s = force_intr_s & (valid_s & ~pc_oor_s |
|
assign intr_vld_s = force_intr_s & (valid_s & ~pc_oor_s |
|
async_intr_vld_s);
|
async_intr_vld_s);
|
|
|
assign intr_vld_qual_s = intr_vld_s & ~iferrto_thisthr_d1;
|
assign intr_vld_qual_s = intr_vld_s & ~iferrto_thisthr_d1;
|
dff #(1) any_intrd_ff(.din (intr_vld_qual_s),
|
dff_s #(1) any_intrd_ff(.din (intr_vld_qual_s),
|
.q (intr_vld_d),
|
.q (intr_vld_d),
|
.clk (clk),
|
.clk (clk),
|
.se (se), .so(), .si());
|
.se (se), .so(), `SIMPLY_RISC_SCANIN);
|
assign fcl_dec_intr_vld_d = intr_vld_d;
|
assign fcl_dec_intr_vld_d = intr_vld_d;
|
assign intr_vld_qual_d = intr_vld_d & ~kill_intr_d & ~kill_thread_d &
|
assign intr_vld_qual_d = intr_vld_d & ~kill_intr_d & ~kill_thread_d &
|
~rb_stg_d;
|
~rb_stg_d;
|
|
|
dff #(1) intr_vlde_ff(.din (intr_vld_qual_d),
|
dff_s #(1) intr_vlde_ff(.din (intr_vld_qual_d),
|
.q (intr_vld_e),
|
.q (intr_vld_e),
|
.clk (clk), .se (se), .so(), .si());
|
.clk (clk), .se (se), .so(), `SIMPLY_RISC_SCANIN);
|
|
|
assign intr_vld_qual_e = intr_vld_e & ~kill_curr_e & ~rb_stg_e &
|
assign intr_vld_qual_e = intr_vld_e & ~kill_curr_e & ~rb_stg_e &
|
~kill_intr_e & ~dtu_inst_anull_e &
|
~kill_intr_e & ~dtu_inst_anull_e &
|
~(thr_match_em & ifu_tlu_flush_m);
|
~(thr_match_em & ifu_tlu_flush_m);
|
|
|
dff #(1) intr_vldm_ff(.din (intr_vld_qual_e),
|
dff_s #(1) intr_vldm_ff(.din (intr_vld_qual_e),
|
.q (intr_vld_m),
|
.q (intr_vld_m),
|
.clk (clk), .se (se), .so(), .si());
|
.clk (clk), .se (se), .so(), `SIMPLY_RISC_SCANIN);
|
|
|
assign intr_vld_qual_m = intr_vld_m & ~kill_thread_m & ~mark4rb_m;
|
assign intr_vld_qual_m = intr_vld_m & ~kill_thread_m & ~mark4rb_m;
|
|
|
dff #(1) intr_vldw_ff(.din (intr_vld_qual_m),
|
dff_s #(1) intr_vldw_ff(.din (intr_vld_qual_m),
|
.q (intr_vld_w),
|
.q (intr_vld_w),
|
.clk (clk), .se (se), .so(), .si());
|
.clk (clk), .se (se), .so(), `SIMPLY_RISC_SCANIN);
|
|
|
// Reset and Idle are prioritized in M. All others in E
|
// Reset and Idle are prioritized in M. All others in E
|
// reset interrupt
|
// reset interrupt
|
assign rstint_m = (rstint_i3[0] & thr_m[0] |
|
assign rstint_m = (rstint_i3[0] & thr_m[0] |
|
rstint_i3[1] & thr_m[1] |
|
rstint_i3[1] & thr_m[1] |
|
| Line 2632... |
Line 2458... |
rstint_i3[3] & thr_m[3]);
|
rstint_i3[3] & thr_m[3]);
|
|
|
assign ifu_tlu_rstint_m = rstint_m & intr_vld_m & ~kill_local_m &
|
assign ifu_tlu_rstint_m = rstint_m & intr_vld_m & ~kill_local_m &
|
~kill_curr_m;
|
~kill_curr_m;
|
// assign rstint_qual_m = rstint_m & ~ely_kill_thread_m & intr_vld_m;
|
// assign rstint_qual_m = rstint_m & ~ely_kill_thread_m & intr_vld_m;
|
dff #(1) rstw_ff(.din (rstint_m),
|
dff_s #(1) rstw_ff(.din (rstint_m),
|
.q (rst_thr_w),
|
.q (rst_thr_w),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
assign fcl_dtu_rst_thr_w = rst_thr_w & intr_vld_w;
|
assign fcl_dtu_rst_thr_w = rst_thr_w & intr_vld_w;
|
|
|
// resume interrupt
|
// resume interrupt
|
assign resumint_m = (resumint_i3[0] & thr_m[0] |
|
assign resumint_m = (resumint_i3[0] & thr_m[0] |
|
resumint_i3[1] & thr_m[1] |
|
resumint_i3[1] & thr_m[1] |
|
resumint_i3[2] & thr_m[2] |
|
resumint_i3[2] & thr_m[2] |
|
resumint_i3[3] & thr_m[3]);
|
resumint_i3[3] & thr_m[3]);
|
assign resumint_qual_m = resumint_m & ~rstint_m;
|
assign resumint_qual_m = resumint_m & ~rstint_m;
|
|
|
dff #(1) resumw_ff(.din (resumint_qual_m),
|
dff_s #(1) resumw_ff(.din (resumint_qual_m),
|
.q (resum_thr_w),
|
.q (resum_thr_w),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
assign fcl_dtu_resum_thr_w = resum_thr_w & intr_vld_w;
|
assign fcl_dtu_resum_thr_w = resum_thr_w & intr_vld_w;
|
|
|
// idle interrupt
|
// idle interrupt
|
assign nuke_thr_m = (nuke_thr_i3[0] & thr_m[0] |
|
assign nuke_thr_m = (nuke_thr_i3[0] & thr_m[0] |
|
nuke_thr_i3[1] & thr_m[1] |
|
nuke_thr_i3[1] & thr_m[1] |
|
nuke_thr_i3[2] & thr_m[2] |
|
nuke_thr_i3[2] & thr_m[2] |
|
nuke_thr_i3[3] & thr_m[3]);
|
nuke_thr_i3[3] & thr_m[3]);
|
|
|
assign nuke_thr_qual_m = nuke_thr_m & ~rstint_m & ~resumint_m;
|
assign nuke_thr_qual_m = nuke_thr_m & ~rstint_m & ~resumint_m;
|
|
|
dff #(1) nukw_ff(.din (nuke_thr_qual_m),
|
dff_s #(1) nukw_ff(.din (nuke_thr_qual_m),
|
.q (nuke_thr_w),
|
.q (nuke_thr_w),
|
.clk (clk),
|
.clk (clk),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
assign fcl_dtu_nuke_thr_w = nuke_thr_w & intr_vld_w;
|
assign fcl_dtu_nuke_thr_w = nuke_thr_w & intr_vld_w;
|
|
|
// uncorrected ecc
|
// uncorrected ecc
|
assign ueint_e = (ueint_i3[0] & thr_e[0] & hypv_int_en_d1[0] |
|
assign ueint_e = (ueint_i3[0] & thr_e[0] & hypv_int_en_d1[0] |
|
ueint_i3[1] & thr_e[1] & hypv_int_en_d1[1] |
|
ueint_i3[1] & thr_e[1] & hypv_int_en_d1[1] |
|
ueint_i3[2] & thr_e[2] & hypv_int_en_d1[2] |
|
ueint_i3[2] & thr_e[2] & hypv_int_en_d1[2] |
|
ueint_i3[3] & thr_e[3] & hypv_int_en_d1[3]);
|
ueint_i3[3] & thr_e[3] & hypv_int_en_d1[3]);
|
assign ueint_qual_e = ueint_e & intr_vld_e;
|
assign ueint_qual_e = ueint_e & intr_vld_e;
|
|
|
dff #(1) uem_ff (.din (ueint_qual_e),
|
dff_s #(1) uem_ff (.din (ueint_qual_e),
|
.q (ueint_m),
|
.q (ueint_m),
|
.clk (clk), .se (se), .si(), .so());
|
.clk (clk), .se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// assign ueint_m = (ueint_i3[0] & thr_m[0] |
|
// assign ueint_m = (ueint_i3[0] & thr_m[0] |
|
// ueint_i3[1] & thr_m[1] |
|
// ueint_i3[1] & thr_m[1] |
|
// ueint_i3[2] & thr_m[2] |
|
// ueint_i3[2] & thr_m[2] |
|
// ueint_i3[3] & thr_m[3]);
|
// ueint_i3[3] & thr_m[3]);
|
|
|
assign ueint_trap_m = ueint_m & intr_vld_m &
|
assign ueint_trap_m = ueint_m & intr_vld_m &
|
~(rstint_m | resumint_m | nuke_thr_m);
|
~(rstint_m | resumint_m | nuke_thr_m);
|
|
|
// assign ueint_qual_m = ueint_trap_m & ~ely_kill_thread_m;
|
// assign ueint_qual_m = ueint_trap_m & ~ely_kill_thread_m;
|
dff #(1) ueintw_ff(.din (ueint_trap_m),
|
dff_s #(1) ueintw_ff(.din (ueint_trap_m),
|
.q (ueint_trap_w),
|
.q (ueint_trap_w),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
assign ueint_qual_w = ueint_trap_w & intr_vld_w;
|
assign ueint_qual_w = ueint_trap_w & intr_vld_w;
|
|
|
// hstk match interrupt
|
// hstk match interrupt
|
assign hintp_e = (hintp_i3[0] & thr_e[0] & hypv_int_en_d1[0] |
|
assign hintp_e = (hintp_i3[0] & thr_e[0] & hypv_int_en_d1[0] |
|
hintp_i3[1] & thr_e[1] & hypv_int_en_d1[1] |
|
hintp_i3[1] & thr_e[1] & hypv_int_en_d1[1] |
|
hintp_i3[2] & thr_e[2] & hypv_int_en_d1[2] |
|
hintp_i3[2] & thr_e[2] & hypv_int_en_d1[2] |
|
hintp_i3[3] & thr_e[3] & hypv_int_en_d1[3]);
|
hintp_i3[3] & thr_e[3] & hypv_int_en_d1[3]);
|
assign hintp_qual_e = hintp_e & intr_vld_e & ~ueint_e;
|
assign hintp_qual_e = hintp_e & intr_vld_e & ~ueint_e;
|
|
|
dff #(1) hintpm_ff (.din (hintp_qual_e),
|
dff_s #(1) hintpm_ff (.din (hintp_qual_e),
|
.q (hintp_m),
|
.q (hintp_m),
|
.clk (clk), .se (se), .si(), .so());
|
.clk (clk), .se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// assign ifu_tlu_hintp_m = hintp_m & ~kill_local_m & intr_vld_m &
|
// assign ifu_tlu_hintp_m = hintp_m & ~kill_local_m & intr_vld_m &
|
// ~(rstint_m | nuke_thr_m | ueint_m);
|
// ~(rstint_m | nuke_thr_m | ueint_m);
|
|
|
// hw int
|
// hw int
|
assign hwint_e = (hwint_i4[0] & thr_e[0] & hypv_int_en_d1[0] |
|
assign hwint_e = (hwint_i4[0] & thr_e[0] & hypv_int_en_d1[0] |
|
hwint_i4[1] & thr_e[1] & hypv_int_en_d1[1] |
|
hwint_i4[1] & thr_e[1] & hypv_int_en_d1[1] |
|
hwint_i4[2] & thr_e[2] & hypv_int_en_d1[2] |
|
hwint_i4[2] & thr_e[2] & hypv_int_en_d1[2] |
|
hwint_i4[3] & thr_e[3] & hypv_int_en_d1[3]);
|
hwint_i4[3] & thr_e[3] & hypv_int_en_d1[3]);
|
dff #(1) hwe_ff(.din (hwint_e),
|
dff_s #(1) hwe_ff(.din (hwint_e),
|
.q (hwint_m),
|
.q (hwint_m),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign ifu_tlu_hwint_m = hwint_m & intr_vld_m & ~kill_local_m &
|
assign ifu_tlu_hwint_m = hwint_m & intr_vld_m & ~kill_local_m &
|
~kill_curr_m &
|
~kill_curr_m &
|
~(rstint_m | resumint_m | nuke_thr_m | ueint_m | hintp_m);
|
~(rstint_m | resumint_m | nuke_thr_m | ueint_m | hintp_m);
|
|
|
| Line 2728... |
Line 2554... |
// assign spuint1_m = (spuint1_i3[0] & thr_m[0] |
|
// assign spuint1_m = (spuint1_i3[0] & thr_m[0] |
|
// spuint1_i3[1] & thr_m[1] |
|
// spuint1_i3[1] & thr_m[1] |
|
// spuint1_i3[2] & thr_m[2] |
|
// spuint1_i3[2] & thr_m[2] |
|
// spuint1_i3[3] & thr_m[3]);
|
// spuint1_i3[3] & thr_m[3]);
|
|
|
dff #(1) spu1m_ff(.din (spuint1_qual_e),
|
dff_s #(1) spu1m_ff(.din (spuint1_qual_e),
|
.q (spuint1_m),
|
.q (spuint1_m),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign spuint1_trap_m = spuint1_m & intr_vld_m &
|
assign spuint1_trap_m = spuint1_m & intr_vld_m &
|
~(rstint_m | resumint_m | nuke_thr_m | hwint_m);
|
~(rstint_m | resumint_m | nuke_thr_m | hwint_m);
|
|
|
// assign spuint1_qual_m = spuint1_trap_m & ~ely_kill_thread_m;
|
// assign spuint1_qual_m = spuint1_trap_m & ~ely_kill_thread_m;
|
|
|
dff #(1) spiw1_ff(.din (spuint1_trap_m),
|
dff_s #(1) spiw1_ff(.din (spuint1_trap_m),
|
.q (spuint1_trap_w),
|
.q (spuint1_trap_w),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
assign spuint1_w = spuint1_trap_w & intr_vld_w;
|
assign spuint1_w = spuint1_trap_w & intr_vld_w;
|
|
|
assign spuint0_e = (spuint0_i3[0] & thr_e[0] & hypv_int_en_d1[0] |
|
assign spuint0_e = (spuint0_i3[0] & thr_e[0] & hypv_int_en_d1[0] |
|
spuint0_i3[1] & thr_e[1] & hypv_int_en_d1[1] |
|
spuint0_i3[1] & thr_e[1] & hypv_int_en_d1[1] |
|
spuint0_i3[2] & thr_e[2] & hypv_int_en_d1[2] |
|
spuint0_i3[2] & thr_e[2] & hypv_int_en_d1[2] |
|
| Line 2754... |
Line 2580... |
|
|
// assign spuint0_m = (spuint0_i3[0] & thr_m[0] |
|
// assign spuint0_m = (spuint0_i3[0] & thr_m[0] |
|
// spuint0_i3[1] & thr_m[1] |
|
// spuint0_i3[1] & thr_m[1] |
|
// spuint0_i3[2] & thr_m[2] |
|
// spuint0_i3[2] & thr_m[2] |
|
// spuint0_i3[3] & thr_m[3]);
|
// spuint0_i3[3] & thr_m[3]);
|
dff #(1) spu0m_ff(.din (spuint0_qual_e),
|
dff_s #(1) spu0m_ff(.din (spuint0_qual_e),
|
.q (spuint0_m),
|
.q (spuint0_m),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign spuint0_trap_m = spuint0_m & intr_vld_m &
|
assign spuint0_trap_m = spuint0_m & intr_vld_m &
|
~(rstint_m | nuke_thr_m | resumint_m |
|
~(rstint_m | nuke_thr_m | resumint_m |
|
hwint_m);
|
hwint_m);
|
|
|
// assign spuint0_qual_m = spuint0_trap_m & ~kill_thread_m;
|
// assign spuint0_qual_m = spuint0_trap_m & ~kill_thread_m;
|
|
|
dff #(1) spiw0_ff(.din (spuint0_trap_m),
|
dff_s #(1) spiw0_ff(.din (spuint0_trap_m),
|
.q (spuint0_trap_w),
|
.q (spuint0_trap_w),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
assign spuint0_w = spuint0_trap_w & intr_vld_w;
|
assign spuint0_w = spuint0_trap_w & intr_vld_w;
|
|
|
// assign ifu_spu_trap_ack = {spuint1_w, spuint0_w};
|
// assign ifu_spu_trap_ack = {spuint1_w, spuint0_w};
|
assign ifu_spu_trap_ack = spuint1_w;
|
assign ifu_spu_trap_ack = spuint1_w;
|
|
|
| Line 2782... |
Line 2608... |
sftint_i3[3] & thr_e[3] & supv_int_en_d1[3]);
|
sftint_i3[3] & thr_e[3] & supv_int_en_d1[3]);
|
|
|
assign sftint_qual_e = sftint_e & ~spuint0_e & intr_vld_e &
|
assign sftint_qual_e = sftint_e & ~spuint0_e & intr_vld_e &
|
~ueint_e & ~spuint1_e & ~hintp_e;
|
~ueint_e & ~spuint1_e & ~hintp_e;
|
|
|
dff #(1) swm_ff(.din (sftint_qual_e),
|
dff_s #(1) swm_ff(.din (sftint_qual_e),
|
.q (sftint_m),
|
.q (sftint_m),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// if nothing else, signal sftint!
|
// if nothing else, signal sftint!
|
// assign ifu_tlu_sftint_m = (sftint_m &
|
// assign ifu_tlu_sftint_m = (sftint_m &
|
// ~(rstint_m | nuke_thr_m | hintp_m | resumint_m |
|
// ~(rstint_m | nuke_thr_m | hintp_m | resumint_m |
|
// hwint_m | spuint1_m | spuint0_m | ueint_m) |
|
// hwint_m | spuint1_m | spuint0_m | ueint_m) |
|
| Line 2811... |
Line 2637... |
|
|
// assign ceint_m = (ceint_i3[0] & thr_m[0] |
|
// assign ceint_m = (ceint_i3[0] & thr_m[0] |
|
// ceint_i3[1] & thr_m[1] |
|
// ceint_i3[1] & thr_m[1] |
|
// ceint_i3[2] & thr_m[2] |
|
// ceint_i3[2] & thr_m[2] |
|
// ceint_i3[3] & thr_m[3]);
|
// ceint_i3[3] & thr_m[3]);
|
dff #(1) cem_ff(.din (ceint_qual_e),
|
dff_s #(1) cem_ff(.din (ceint_qual_e),
|
.q (ceint_m),
|
.q (ceint_m),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign ceint_trap_m = ceint_m & intr_vld_m &
|
assign ceint_trap_m = ceint_m & intr_vld_m &
|
~(rstint_m | nuke_thr_m | resumint_m |
|
~(rstint_m | nuke_thr_m | resumint_m |
|
sftint_m | hwint_m);
|
sftint_m | hwint_m);
|
|
|
// assign ceint_qual_m = ceint_trap_m & ~ely_kill_thread_m;
|
// assign ceint_qual_m = ceint_trap_m & ~ely_kill_thread_m;
|
dff #(1) ceintw_ff(.din (ceint_trap_m),
|
dff_s #(1) ceintw_ff(.din (ceint_trap_m),
|
.q (ceint_trap_w),
|
.q (ceint_trap_w),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
assign ceint_qual_w = ceint_trap_w & intr_vld_w;
|
assign ceint_qual_w = ceint_trap_w & intr_vld_w;
|
|
|
// resumable error interrupt
|
// resumable error interrupt
|
assign rerr_e = (rerr_i3[0] & thr_e[0] & supv_int_en_d1[0] |
|
assign rerr_e = (rerr_i3[0] & thr_e[0] & supv_int_en_d1[0] |
|
rerr_i3[1] & thr_e[1] & supv_int_en_d1[1] |
|
rerr_i3[1] & thr_e[1] & supv_int_en_d1[1] |
|
rerr_i3[2] & thr_e[2] & supv_int_en_d1[2] |
|
rerr_i3[2] & thr_e[2] & supv_int_en_d1[2] |
|
rerr_i3[3] & thr_e[3] & supv_int_en_d1[3]);
|
rerr_i3[3] & thr_e[3] & supv_int_en_d1[3]);
|
assign rerr_qual_e = rerr_e & intr_vld_e & ~ueint_e & ~ceint_e &
|
assign rerr_qual_e = rerr_e & intr_vld_e & ~ueint_e & ~ceint_e &
|
~spuint1_e & ~spuint0_e & ~hintp_e;
|
~spuint1_e & ~spuint0_e & ~hintp_e;
|
|
|
dff #(1) rem_ff(.din (rerr_qual_e),
|
dff_s #(1) rem_ff(.din (rerr_qual_e),
|
.q (rerr_m),
|
.q (rerr_m),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// assign rerr_m = (rerr_i3[0] & thr_m[0] |
|
// assign rerr_m = (rerr_i3[0] & thr_m[0] |
|
// rerr_i3[1] & thr_m[1] |
|
// rerr_i3[1] & thr_m[1] |
|
// rerr_i3[2] & thr_m[2] |
|
// rerr_i3[2] & thr_m[2] |
|
// rerr_i3[3] & thr_m[3]);
|
// rerr_i3[3] & thr_m[3]);
|
| Line 2856... |
Line 2682... |
hintp_m | rerr_m | sftint_m | hwint_m |
|
hintp_m | rerr_m | sftint_m | hwint_m |
|
rstint_m | nuke_thr_m | resumint_m);
|
rstint_m | nuke_thr_m | resumint_m);
|
|
|
// ..and rollback if that is the case
|
// ..and rollback if that is the case
|
assign rb_intr_m = ~any_intr_m & intr_vld_m;
|
assign rb_intr_m = ~any_intr_m & intr_vld_m;
|
dff #(1) rbint_ff(.din (rb_intr_m),
|
dff_s #(1) rbint_ff(.din (rb_intr_m),
|
.q (rb_intr_w),
|
.q (rb_intr_w),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// use synchronous interrupt signal to switch out thread in swl
|
// use synchronous interrupt signal to switch out thread in swl
|
// assign fcl_dtu_sync_intr_d = (intr_vld_d | immu_miss_crit_d) & ~rb_stg_d;
|
// assign fcl_dtu_sync_intr_d = (intr_vld_d | immu_miss_crit_d) & ~rb_stg_d;
|
assign fcl_dtu_sync_intr_d = (intr_vld_d) & ~rb_stg_d_crit;
|
assign fcl_dtu_sync_intr_d = (intr_vld_d) & ~rb_stg_d_crit;
|
|
|
| Line 2890... |
Line 2716... |
// & ~late_flush_w2;
|
// & ~late_flush_w2;
|
// Need to be a little pessimitic: can't clear the delay slot vec
|
// Need to be a little pessimitic: can't clear the delay slot vec
|
// after a utrap, since we may still be in the delay slot when we
|
// after a utrap, since we may still be in the delay slot when we
|
// re-execute
|
// re-execute
|
|
|
dffr #(4) ds_reg(.din (delay_slot_vec_nxt),
|
dffr_s #(4) ds_reg(.din (delay_slot_vec_nxt),
|
.q (delay_slot_vec),
|
.q (delay_slot_vec),
|
.rst (fcl_reset),
|
.rst (fcl_reset),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
assign fcl_dec_dslot_s = (delay_slot_vec[0] & thr_f[0] |
|
assign fcl_dec_dslot_s = (delay_slot_vec[0] & thr_f[0] |
|
delay_slot_vec[1] & thr_f[1] |
|
delay_slot_vec[1] & thr_f[1] |
|
delay_slot_vec[2] & thr_f[2] |
|
delay_slot_vec[2] & thr_f[2] |
|
delay_slot_vec[3] & thr_f[3]);
|
delay_slot_vec[3] & thr_f[3]);
|
|
|
|
|
//------------------------------
|
//------------------------------
|
// NIR control
|
// NIR control
|
//------------------------------
|
//------------------------------
|
// use nir if va[2] of previous fetch is a zero (i.e lower word)
|
// use nir if va[2] of previous fetch is a zero (i.e lower word)
|
dff #(1) va2_ff(.din (fdp_fcl_va2_bf),
|
dff_s #(1) va2_ff(.din (fdp_fcl_va2_bf),
|
.clk (clk),
|
.clk (clk),
|
.q (va2_f),
|
.q (va2_f),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign usep_bf = rdreq_f & ~va2_f & ~ntpc_thisthr & ~stall_f;
|
assign usep_bf = rdreq_f & ~va2_f & ~ntpc_thisthr & ~stall_f;
|
assign set_usen_bf = usep_bf & ~ely_stall_thisthr_f & dtu_fcl_running_s;
|
assign set_usen_bf = usep_bf & ~ely_stall_thisthr_f & dtu_fcl_running_s;
|
|
|
// need to kill usen if trap or interrupt or flush
|
// need to kill usen if trap or interrupt or flush
|
| Line 2923... |
Line 2749... |
(clear_s_d1) |
|
(clear_s_d1) |
|
(ntpc_vld) |
|
(ntpc_vld) |
|
(rb_w2 | rb_froms)); // reset usen (wins)
|
(rb_w2 | rb_froms)); // reset usen (wins)
|
// & ~dtu_fcl_flush_nir
|
// & ~dtu_fcl_flush_nir
|
|
|
dffr #(4) thr_usen_reg(.din (thr_usen_nxt),
|
dffr_s #(4) thr_usen_reg(.din (thr_usen_nxt),
|
.clk (clk),
|
.clk (clk),
|
.q (thr_usen_bf),
|
.q (thr_usen_bf),
|
.rst (fcl_reset),
|
.rst (fcl_reset),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
/*
|
/*
|
// Use hand instantiated mux
|
// Use hand instantiated mux
|
bw_u1_ao2222_4x UZsize_usn_mx(.z (usen_iso_bf)
|
bw_u1_ao2222_4x UZsize_usn_mx(.z (usen_iso_bf)
|
.a2 (thr_usen_bf[0]),
|
.a2 (thr_usen_bf[0]),
|
| Line 2987... |
Line 2813... |
assign fcl_swl_swout_f = stall_f; // sw out curr but don't sw in next
|
assign fcl_swl_swout_f = stall_f; // sw out curr but don't sw in next
|
// Note: need fcl_swl_swout_f and dtu_fcl_running_s to sync swl and
|
// Note: need fcl_swl_swout_f and dtu_fcl_running_s to sync swl and
|
// fcl at all times.
|
// fcl at all times.
|
|
|
assign switch_qual_bf = switch_bf & ~rst_stallreq;
|
assign switch_qual_bf = switch_bf & ~rst_stallreq;
|
dff #(1) sw_ff (.din (switch_qual_bf),
|
dff_s #(1) sw_ff (.din (switch_qual_bf),
|
.clk (clk),
|
.clk (clk),
|
.q (switch_s2),
|
.q (switch_s2),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff #(1) tmfn_ff (.din (switch_bf),
|
dff_s #(1) tmfn_ff (.din (switch_bf),
|
.clk (clk),
|
.clk (clk),
|
.q (tm_fd_l),
|
.q (tm_fd_l),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// need to qual with immu_fault to avoid X's
|
// need to qual with immu_fault to avoid X's
|
// assign fcl_dtu_swc_s = fdp_fcl_swc_s2 & inst_vld_s_crit &
|
// assign fcl_dtu_swc_s = fdp_fcl_swc_s2 & inst_vld_s_crit &
|
// ~immu_fault_f & ~part_stall_thisthr_f;
|
// ~immu_fault_f & ~part_stall_thisthr_f;
|
// assign fcl_dtu_swc_s = fdp_fcl_swc_s2 & inst_vld_s_crit &
|
// assign fcl_dtu_swc_s = fdp_fcl_swc_s2 & inst_vld_s_crit &
|
| Line 3073... |
Line 2899... |
bw_u1_nand2_4x UZsize_tmne30(.z (thr_match_ne),
|
bw_u1_nand2_4x UZsize_tmne30(.z (thr_match_ne),
|
.a (tmne_10),
|
.a (tmne_10),
|
.b (tmne_32));
|
.b (tmne_32));
|
|
|
|
|
dff #(4) thrf_reg(.din (thr_bf), // thr_f may be 4'b0000 but it has
|
dff_s #(4) thrf_reg(.din (thr_bf), // thr_f may be 4'b0000 but it has
|
.clk (clk), // to reset to 4'b0001
|
.clk (clk), // to reset to 4'b0001
|
.q (thr_f_flop),
|
.q (thr_f_flop),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
bw_u1_buf_10x UZsize_tfcrit0(.a (thr_f_flop[0]), .z(thr_f_crit[0]));
|
bw_u1_buf_10x UZsize_tfcrit0(.a (thr_f_flop[0]), .z(thr_f_crit[0]));
|
bw_u1_buf_10x UZsize_tfcrit1(.a (thr_f_flop[1]), .z(thr_f_crit[1]));
|
bw_u1_buf_10x UZsize_tfcrit1(.a (thr_f_flop[1]), .z(thr_f_crit[1]));
|
bw_u1_buf_10x UZsize_tfcrit2(.a (thr_f_flop[2]), .z(thr_f_crit[2]));
|
bw_u1_buf_10x UZsize_tfcrit2(.a (thr_f_flop[2]), .z(thr_f_crit[2]));
|
bw_u1_buf_10x UZsize_tfcrit3(.a (thr_f_flop[3]), .z(thr_f_crit[3]));
|
bw_u1_buf_10x UZsize_tfcrit3(.a (thr_f_flop[3]), .z(thr_f_crit[3]));
|
| Line 3103... |
Line 2929... |
|
|
//`ifdef VERPLEX
|
//`ifdef VERPLEX
|
// $constraint thr_s1_1h4 ($one_hot(thr_s1_next[3:0]));
|
// $constraint thr_s1_1h4 ($one_hot(thr_s1_next[3:0]));
|
//`endif
|
//`endif
|
|
|
dff #(4) thrs1_reg(.din (thr_s1_next),
|
dff_s #(4) thrs1_reg(.din (thr_s1_next),
|
.clk (clk),
|
.clk (clk),
|
.q (thr_s1),
|
.q (thr_s1),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff #(4) thrd_reg(.din (thr_s1_next),
|
dff_s #(4) thrd_reg(.din (thr_s1_next),
|
.clk (clk),
|
.clk (clk),
|
.q (thr_d),
|
.q (thr_d),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign fcl_ifq_thr_s1[0] = thr_s1[3] | thr_s1[1];
|
assign fcl_ifq_thr_s1[0] = thr_s1[3] | thr_s1[1];
|
assign fcl_ifq_thr_s1[1] = thr_s1[3] | thr_s1[2];
|
assign fcl_ifq_thr_s1[1] = thr_s1[3] | thr_s1[2];
|
|
|
assign ifu_tlu_thrid_d[1] = thr_d[3] | thr_d[2];
|
assign ifu_tlu_thrid_d[1] = thr_d[3] | thr_d[2];
|
| Line 3137... |
Line 2963... |
// assign thr_match_ft = (trap_thr[0] & thr_f[0] |
|
// assign thr_match_ft = (trap_thr[0] & thr_f[0] |
|
// trap_thr[1] & thr_f[1] |
|
// trap_thr[1] & thr_f[1] |
|
// trap_thr[2] & thr_f[2] |
|
// trap_thr[2] & thr_f[2] |
|
// trap_thr[3] & thr_f[3]);
|
// trap_thr[3] & thr_f[3]);
|
|
|
dffr #(4) thre_reg(.din (thr_d),
|
dffr_s #(4) thre_reg(.din (thr_d),
|
.clk (clk),
|
.clk (clk),
|
.rst (fcl_reset),
|
.rst (fcl_reset),
|
.q (thr_e),
|
.q (thr_e),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dffr #(4) thre2_reg(.din (thr_d),
|
dffr_s #(4) thre2_reg(.din (thr_d),
|
.clk (clk),
|
.clk (clk),
|
.rst (fcl_reset),
|
.rst (fcl_reset),
|
.q (thr_e_v2),
|
.q (thr_e_v2),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign ifu_tlu_thrid_e[1] = thr_e[3] | thr_e[2];
|
assign ifu_tlu_thrid_e[1] = thr_e[3] | thr_e[2];
|
assign ifu_tlu_thrid_e[0] = thr_e[3] | thr_e[1];
|
assign ifu_tlu_thrid_e[0] = thr_e[3] | thr_e[1];
|
|
|
assign thr_match_de = (thr_d[0] & thr_e[0] |
|
assign thr_match_de = (thr_d[0] & thr_e[0] |
|
| Line 3162... |
Line 2988... |
assign thr_match_dm = (thr_d[0] & thr_m[0] |
|
assign thr_match_dm = (thr_d[0] & thr_m[0] |
|
thr_d[1] & thr_m[1] |
|
thr_d[1] & thr_m[1] |
|
thr_d[2] & thr_m[2] |
|
thr_d[2] & thr_m[2] |
|
thr_d[3] & thr_m[3]);
|
thr_d[3] & thr_m[3]);
|
|
|
dff #(4) thrm_reg(.din (thr_e),
|
dff_s #(4) thrm_reg(.din (thr_e),
|
.clk (clk),
|
.clk (clk),
|
.q (thr_m),
|
.q (thr_m),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff #(4) thrw_reg(.din (thr_m),
|
dff_s #(4) thrw_reg(.din (thr_m),
|
.clk (clk),
|
.clk (clk),
|
.q (thr_w),
|
.q (thr_w),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign sas_thrid_w[1] = thr_w[3] | thr_w[2];
|
assign sas_thrid_w[1] = thr_w[3] | thr_w[2];
|
assign sas_thrid_w[0] = thr_w[3] | thr_w[1];
|
assign sas_thrid_w[0] = thr_w[3] | thr_w[1];
|
|
|
assign thr_match_fw = (thr_f[0] & thr_w[0] |
|
assign thr_match_fw = (thr_f[0] & thr_w[0] |
|
| Line 3205... |
Line 3031... |
assign thr_match_ew = (thr_e_v2[0] & thr_w[0] |
|
assign thr_match_ew = (thr_e_v2[0] & thr_w[0] |
|
thr_e_v2[1] & thr_w[1] |
|
thr_e_v2[1] & thr_w[1] |
|
thr_e_v2[2] & thr_w[2] |
|
thr_e_v2[2] & thr_w[2] |
|
thr_e_v2[3] & thr_w[3]);
|
thr_e_v2[3] & thr_w[3]);
|
|
|
dff #(1) stmw2_ff(.din (thr_match_ew),
|
dff_s #(1) stmw2_ff(.din (thr_match_ew),
|
.q (same_thr_mw2),
|
.q (same_thr_mw2),
|
.clk (clk), .se (se), .si(), .so());
|
.clk (clk), .se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign thr_match_ew2 = (thr_e[0] & thr_w2[0] |
|
assign thr_match_ew2 = (thr_e[0] & thr_w2[0] |
|
thr_e[1] & thr_w2[1] |
|
thr_e[1] & thr_w2[1] |
|
thr_e[2] & thr_w2[2] |
|
thr_e[2] & thr_w2[2] |
|
thr_e[3] & thr_w2[3]);
|
thr_e[3] & thr_w2[3]);
|
| Line 3219... |
Line 3045... |
assign thr_match_mw = (thr_m[0] & thr_w[0] |
|
assign thr_match_mw = (thr_m[0] & thr_w[0] |
|
thr_m[1] & thr_w[1] |
|
thr_m[1] & thr_w[1] |
|
thr_m[2] & thr_w[2] |
|
thr_m[2] & thr_w[2] |
|
thr_m[3] & thr_w[3]);
|
thr_m[3] & thr_w[3]);
|
|
|
dff #(4) thrw2_reg(.din (thr_w),
|
dff_s #(4) thrw2_reg(.din (thr_w),
|
.clk (clk),
|
.clk (clk),
|
.q (thr_w2),
|
.q (thr_w2),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
|
|
//-------------------------
|
//-------------------------
|
// Rollback
|
// Rollback
|
//-------------------------
|
//-------------------------
|
| Line 3267... |
Line 3093... |
|
|
assign retract_iferr_qual_d1 = retract_iferr_d1 & thr_match_de &
|
assign retract_iferr_qual_d1 = retract_iferr_d1 & thr_match_de &
|
fcl_dtu_inst_vld_d &
|
fcl_dtu_inst_vld_d &
|
~(dtu_fcl_rollback_g & thr_match_ew);
|
~(dtu_fcl_rollback_g & thr_match_ew);
|
|
|
dff rbe_ff(.din (rb2_inst_d),
|
dff_s rbe_ff(.din (rb2_inst_d),
|
.q (rb2_inst_e),
|
.q (rb2_inst_e),
|
.clk (clk),
|
.clk (clk),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff rte_ff(.din (retract_inst_d),
|
dff_s rte_ff(.din (retract_inst_d),
|
.q (rt2_inst_e),
|
.q (rt2_inst_e),
|
.clk (clk),
|
.clk (clk),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff rbd_ff(.din (rb1_inst_s),
|
dff_s rbd_ff(.din (rb1_inst_s),
|
.q (rb1_inst_d),
|
.q (rb1_inst_d),
|
.clk (clk),
|
.clk (clk),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff rtd_ff(.din (rt1_inst_s),
|
dff_s rtd_ff(.din (rt1_inst_s),
|
.q (rt1_inst_d),
|
.q (rt1_inst_d),
|
.clk (clk),
|
.clk (clk),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff rbs_ff(.din (rb0_inst_bf),
|
dff_s rbs_ff(.din (rb0_inst_bf),
|
.q (rb0_inst_s),
|
.q (rb0_inst_s),
|
.clk (clk),
|
.clk (clk),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// TBD: is this necessary?
|
// TBD: is this necessary?
|
dff rts_ff(.din (rt0_inst_bf),
|
dff_s rts_ff(.din (rt0_inst_bf),
|
.q (rt0_inst_s),
|
.q (rt0_inst_s),
|
.clk (clk),
|
.clk (clk),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff rtiferr_ff(.din (retract_iferr_qual_d1),
|
dff_s rtiferr_ff(.din (retract_iferr_qual_d1),
|
.q (retract_iferr_e),
|
.q (retract_iferr_e),
|
.clk (clk),
|
.clk (clk),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign rb_stg_s = (rb0_inst_s | rt0_inst_s) & tm_fd_l |
|
assign rb_stg_s = (rb0_inst_s | rt0_inst_s) & tm_fd_l |
|
(rb1_inst_d | rt1_inst_d) & ~tm_fd_l;
|
(rb1_inst_d | rt1_inst_d) & ~tm_fd_l;
|
assign rb_stg_d_crit = rb1_inst_d | rt1_inst_d;
|
assign rb_stg_d_crit = rb1_inst_d | rt1_inst_d;
|
assign rb_stg_e = rb2_inst_e | rt2_inst_e;
|
assign rb_stg_e = rb2_inst_e | rt2_inst_e;
|
| Line 3353... |
Line 3179... |
.z (brto_nxtthr_bf_l));
|
.z (brto_nxtthr_bf_l));
|
|
|
// bw_u1_inv_8x UZsize_btkn_bf(.a (brto_nxtthr_bf_l),
|
// bw_u1_inv_8x UZsize_btkn_bf(.a (brto_nxtthr_bf_l),
|
// .z (brto_nxtthr_bf));
|
// .z (brto_nxtthr_bf));
|
|
|
dff #(1) br_ff(.din (brtaken_buf_e),
|
dff_s #(1) br_ff(.din (brtaken_buf_e),
|
.q (brtaken_m),
|
.q (brtaken_m),
|
.clk (clk),
|
.clk (clk),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
|
|
//----------------------------------------------------------------------
|
//----------------------------------------------------------------------
|
// PC related control
|
// PC related control
|
//----------------------------------------------------------------------
|
//----------------------------------------------------------------------
|
| Line 3495... |
Line 3321... |
bw_u1_inv_8x UZsize_ntfin_buf3(.z (nextthr_final_bf[3]),
|
bw_u1_inv_8x UZsize_ntfin_buf3(.z (nextthr_final_bf[3]),
|
.a (nextthr_final_bf_l[3]));
|
.a (nextthr_final_bf_l[3]));
|
|
|
|
|
// decode trap thread
|
// decode trap thread
|
dff #(2) ld_trp_reg(.din ({tlu_ifu_trappc_vld_w1,
|
dff_s #(2) ld_trp_reg(.din ({tlu_ifu_trappc_vld_w1,
|
tlu_ifu_trapnpc_vld_w1}),
|
tlu_ifu_trapnpc_vld_w1}),
|
.q ({trappc_vld_w2,
|
.q ({trappc_vld_w2,
|
trapnpc_vld_w2}),
|
trapnpc_vld_w2}),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff #(2) trp_tid_reg(.din (tlu_ifu_trap_tid_w1[1:0]),
|
dff_s #(2) trp_tid_reg(.din (tlu_ifu_trap_tid_w1[1:0]),
|
.q (trap_tid_w2[1:0]),
|
.q (trap_tid_w2[1:0]),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign trap_thr[0] = ~trap_tid_w2[1] & ~trap_tid_w2[0];
|
assign trap_thr[0] = ~trap_tid_w2[1] & ~trap_tid_w2[0];
|
assign trap_thr[1] = ~trap_tid_w2[1] & trap_tid_w2[0];
|
assign trap_thr[1] = ~trap_tid_w2[1] & trap_tid_w2[0];
|
assign trap_thr[2] = trap_tid_w2[1] & ~trap_tid_w2[0];
|
assign trap_thr[2] = trap_tid_w2[1] & ~trap_tid_w2[0];
|
assign trap_thr[3] = trap_tid_w2[1] & trap_tid_w2[0];
|
assign trap_thr[3] = trap_tid_w2[1] & trap_tid_w2[0];
|
| Line 3541... |
Line 3367... |
fcl_fdp_tpcbf_sel_trap_bf_l = ~load_tpc;
|
fcl_fdp_tpcbf_sel_trap_bf_l = ~load_tpc;
|
end // always @ (...
|
end // always @ (...
|
|
|
// Track correctible errors
|
// Track correctible errors
|
assign irf_ce_m = exu_ifu_ecc_ce_m & ~trap_m & inst_vld_m & ~kill_curr_m;
|
assign irf_ce_m = exu_ifu_ecc_ce_m & ~trap_m & inst_vld_m & ~kill_curr_m;
|
dff #(1) irfcew_ff(.din (irf_ce_m),
|
dff_s #(1) irfcew_ff(.din (irf_ce_m),
|
.q (irf_ce_w),
|
.q (irf_ce_w),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// track if ldhit was actually a miss
|
// track if ldhit was actually a miss
|
// D and S stage are rolled back through the normal D stage retract
|
// D and S stage are rolled back through the normal D stage retract
|
// process.
|
// process.
|
assign mark4rb_d = lsu_ifu_dc_parity_error_w2 & thr_match_dw2 &
|
assign mark4rb_d = lsu_ifu_dc_parity_error_w2 & thr_match_dw2 &
|
| Line 3557... |
Line 3383... |
|
|
assign mark4rb_e = lsu_ifu_dc_parity_error_w2 & thr_match_ew2 &
|
assign mark4rb_e = lsu_ifu_dc_parity_error_w2 & thr_match_ew2 &
|
(inst_vld_e | intr_vld_e) &
|
(inst_vld_e | intr_vld_e) &
|
~dtu_inst_anull_e & ~kill_curr_e;
|
~dtu_inst_anull_e & ~kill_curr_e;
|
|
|
dff #(2) markrb_reg(.din ({mark4rb_m,
|
dff_s #(2) markrb_reg(.din ({mark4rb_m,
|
mark4rb_e}),
|
mark4rb_e}),
|
.q ({mark4rb_w,
|
.q ({mark4rb_w,
|
mark4rb_m}),
|
mark4rb_m}),
|
.clk (clk),
|
.clk (clk),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// Rollback from W on irf/frf ce and on a dcache parity error
|
// Rollback from W on irf/frf ce and on a dcache parity error
|
assign rb_stg_w = irf_ce_w & inst_vld_w & no_iftrap_w |
|
assign rb_stg_w = irf_ce_w & inst_vld_w & no_iftrap_w |
|
ffu_ifu_fst_ce_w & inst_vld_w & no_iftrap_w |
|
ffu_ifu_fst_ce_w & inst_vld_w & no_iftrap_w |
|
rb_intr_w & intr_vld_w |
|
rb_intr_w & intr_vld_w |
|
| Line 3582... |
Line 3408... |
(resumint_m | nuke_thr_m) &
|
(resumint_m | nuke_thr_m) &
|
intr_vld_m & ~rstint_m |
|
intr_vld_m & ~rstint_m |
|
rb_intr_m |
|
rb_intr_m |
|
mark4rb_m);
|
mark4rb_m);
|
assign utrap_flush_m = ifu_tlu_flush_m & ~kill_local_m;
|
assign utrap_flush_m = ifu_tlu_flush_m & ~kill_local_m;
|
dff #(1) flw_ff(.din (utrap_flush_m),
|
dff_s #(1) flw_ff(.din (utrap_flush_m),
|
.q (utrap_flush_w),
|
.q (utrap_flush_w),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
assign ifu_tlu_flush_w = utrap_flush_w;
|
assign ifu_tlu_flush_w = utrap_flush_w;
|
assign fcl_swl_flush_w = (irf_ce_w & inst_vld_w & no_iftrap_w |
|
assign fcl_swl_flush_w = (irf_ce_w & inst_vld_w & no_iftrap_w |
|
rb_intr_w & intr_vld_w |
|
rb_intr_w & intr_vld_w |
|
mark4rb_w |
|
mark4rb_w |
|
fcl_dtu_resum_thr_w |
|
fcl_dtu_resum_thr_w |
|
| Line 3606... |
Line 3432... |
assign ce_cnt0_nxt = (({4{any_ce_w & inst_vld_w}} & thr_w) ^
|
assign ce_cnt0_nxt = (({4{any_ce_w & inst_vld_w}} & thr_w) ^
|
ce_cnt0) & ~ce_cnt_rst;
|
ce_cnt0) & ~ce_cnt_rst;
|
|
|
assign ce_cnt_rst = thr_w & {4{inst_vld_w & ~any_ce_w}} | {4{fcl_reset}};
|
assign ce_cnt_rst = thr_w & {4{inst_vld_w & ~any_ce_w}} | {4{fcl_reset}};
|
|
|
dff #(8) cecnt_reg(.din ({ce_cnt1_nxt, ce_cnt0_nxt}),
|
dff_s #(8) cecnt_reg(.din ({ce_cnt1_nxt, ce_cnt0_nxt}),
|
.q ({ce_cnt1, ce_cnt0}),
|
.q ({ce_cnt1, ce_cnt0}),
|
.clk (clk),
|
.clk (clk),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// find the count for the current d stage thread
|
// find the count for the current d stage thread
|
assign ce_val1_d = (thr_d[0] & ce_cnt1[0] |
|
assign ce_val1_d = (thr_d[0] & ce_cnt1[0] |
|
thr_d[1] & ce_cnt1[1] |
|
thr_d[1] & ce_cnt1[1] |
|
thr_d[2] & ce_cnt1[2] |
|
thr_d[2] & ce_cnt1[2] |
|
| Line 3625... |
Line 3451... |
thr_d[3] & ce_cnt0[3]);
|
thr_d[3] & ce_cnt0[3]);
|
|
|
// if count hits 3 disable ce's
|
// if count hits 3 disable ce's
|
assign disable_ce_d = ce_val1_d & ce_val0_d;
|
assign disable_ce_d = ce_val1_d & ce_val0_d;
|
|
|
dff #(1) disce_ff(.din (disable_ce_d),
|
dff_s #(1) disce_ff(.din (disable_ce_d),
|
.q (disable_ce_e),
|
.q (disable_ce_e),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
assign ifu_exu_disable_ce_e = disable_ce_e;
|
assign ifu_exu_disable_ce_e = disable_ce_e;
|
|
|
// select error/trap/utrap rollback PC
|
// select error/trap/utrap rollback PC
|
assign fcl_fdp_trrbpc_sel_trap_bf_l =
|
assign fcl_fdp_trrbpc_sel_trap_bf_l =
|
~({4{trappc_vld_w2}} & trap_thr);
|
~({4{trappc_vld_w2}} & trap_thr);
|
| Line 3700... |
Line 3526... |
iferrto_thisthr_d1) &
|
iferrto_thisthr_d1) &
|
~arst_vld_f &
|
~arst_vld_f &
|
~async_intr_vld_s}} | ~thr_f) &
|
~async_intr_vld_s}} | ~thr_f) &
|
~({4{trappc_vld_w2}} & trap_thr);
|
~({4{trappc_vld_w2}} & trap_thr);
|
|
|
dffr #(4) ntpcv_reg(.din (ntpc_vld_nxt),
|
dffr_s #(4) ntpcv_reg(.din (ntpc_vld_nxt),
|
.clk (clk),
|
.clk (clk),
|
.q (ntpc_vld),
|
.q (ntpc_vld),
|
.rst (fcl_reset),
|
.rst (fcl_reset),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign ntpc_thisthr = (thr_f[0] & ntpc_vld[0] |
|
assign ntpc_thisthr = (thr_f[0] & ntpc_vld[0] |
|
thr_f[1] & ntpc_vld[1] |
|
thr_f[1] & ntpc_vld[1] |
|
thr_f[2] & ntpc_vld[2] |
|
thr_f[2] & ntpc_vld[2] |
|
thr_f[3] & ntpc_vld[3]);
|
thr_f[3] & ntpc_vld[3]);
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| Line 3847... |
Line 3673... |
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//--------------------
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//--------------------
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// rdsr data to exu
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// rdsr data to exu
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//--------------------
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//--------------------
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dff #(1) pcrsr_ff(.din (dec_fcl_rdsr_sel_pc_d),
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dff_s #(1) pcrsr_ff(.din (dec_fcl_rdsr_sel_pc_d),
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.clk (clk),
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.clk (clk),
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.q (rdsr_sel_pc_e),
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.q (rdsr_sel_pc_e),
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.se (se), .si(), .so());
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.se (se), `SIMPLY_RISC_SCANIN, .so());
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dff #(1) thrrsr_ff(.din (dec_fcl_rdsr_sel_thr_d),
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dff_s #(1) thrrsr_ff(.din (dec_fcl_rdsr_sel_thr_d),
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.clk (clk),
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.clk (clk),
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.q (rdsr_sel_thr_e),
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.q (rdsr_sel_thr_e),
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.se (se), .si(), .so());
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.se (se), `SIMPLY_RISC_SCANIN, .so());
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// make sure they are exclusive
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// make sure they are exclusive
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assign fcl_fdp_rdsr_sel_pc_e_l = ~rdsr_sel_pc_e;
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assign fcl_fdp_rdsr_sel_pc_e_l = ~rdsr_sel_pc_e;
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assign fcl_fdp_rdsr_sel_thr_e_l = ~(~rdsr_sel_pc_e & rdsr_sel_thr_e);
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assign fcl_fdp_rdsr_sel_thr_e_l = ~(~rdsr_sel_pc_e & rdsr_sel_thr_e);
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assign fcl_fdp_rdsr_sel_ver_e_l = ~(~rdsr_sel_pc_e & ~rdsr_sel_thr_e);
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assign fcl_fdp_rdsr_sel_ver_e_l = ~(~rdsr_sel_pc_e & ~rdsr_sel_thr_e);
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| Line 3892... |
Line 3718... |
assign fcl_fdp_oddwin_s = (exu_ifu_oddwin_s[0] & thr_f[0] |
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assign fcl_fdp_oddwin_s = (exu_ifu_oddwin_s[0] & thr_f[0] |
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exu_ifu_oddwin_s[1] & thr_f[1] |
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exu_ifu_oddwin_s[1] & thr_f[1] |
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exu_ifu_oddwin_s[2] & thr_f[2] |
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exu_ifu_oddwin_s[2] & thr_f[2] |
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exu_ifu_oddwin_s[3] & thr_f[3]);
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exu_ifu_oddwin_s[3] & thr_f[3]);
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dff #(1) oddwin_ff(.din (fcl_fdp_oddwin_s),
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dff_s #(1) oddwin_ff(.din (fcl_fdp_oddwin_s),
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.clk (clk),
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.clk (clk),
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.q (fcl_imd_oddwin_d),
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.q (fcl_imd_oddwin_d),
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.se (se), .si(), .so());
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.se (se), `SIMPLY_RISC_SCANIN, .so());
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sink #(2) s0(.in (sas_thrid_w));
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sink #(2) s0(.in (sas_thrid_w));
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endmodule // sparc_ifu_fcl
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endmodule // sparc_ifu_fcl
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No newline at end of file
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No newline at end of file
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