| Line 16... |
Line 16... |
// You should have received a copy of the GNU General Public
|
// You should have received a copy of the GNU General Public
|
// License along with this work; if not, write to the Free Software
|
// License along with this work; if not, write to the Free Software
|
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
|
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
|
//
|
//
|
// ========== Copyright Header End ============================================
|
// ========== Copyright Header End ============================================
|
|
`ifdef SIMPLY_RISC_TWEAKS
|
|
`define SIMPLY_RISC_SCANIN .si(0)
|
|
`else
|
|
`define SIMPLY_RISC_SCANIN .si()
|
|
`endif
|
////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////
|
/*
|
/*
|
// Module Name: sparc_ifu_fdp
|
// Module Name: sparc_ifu_fdp
|
// Description:
|
// Description:
|
// The fdp contains the pc's for all four threads and the PC and
|
// The fdp contains the pc's for all four threads and the PC and
|
| Line 30... |
Line 35... |
// double instruction bundle which is fetched from the icache.
|
// double instruction bundle which is fetched from the icache.
|
*/
|
*/
|
////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////
|
// Local header file includes / local defines
|
// Local header file includes / local defines
|
////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////
|
/*
|
`include "ifu.h"
|
/* ========== Copyright Header Begin ==========================================
|
|
*
|
|
* OpenSPARC T1 Processor File: ifu.h
|
|
* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
|
|
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
|
|
*
|
|
* The above named program is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU General Public
|
|
* License version 2 as published by the Free Software Foundation.
|
|
*
|
|
* The above named program is distributed in the hope that it will be
|
|
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
|
* General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public
|
|
* License along with this work; if not, write to the Free Software
|
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
|
|
*
|
|
* ========== Copyright Header End ============================================
|
|
*/
|
|
////////////////////////////////////////////////////////////////////////
|
|
/*
|
|
//
|
|
// Module Name: ifu.h
|
|
// Description:
|
|
// All ifu defines
|
|
*/
|
|
|
|
//--------------------------------------------
|
|
// Icache Values in IFU::ICD/ICV/ICT/FDP/IFQDP
|
|
//--------------------------------------------
|
|
// Set Values
|
|
|
|
// IC_IDX_HI = log(icache_size/4ways) - 1
|
|
|
|
|
|
// !!IMPORTANT!! a change to IC_LINE_SZ will mean a change to the code as
|
|
// well. Unfortunately this has not been properly parametrized.
|
|
// Changing the IC_LINE_SZ param alone is *not* enough.
|
|
|
|
|
|
// !!IMPORTANT!! a change to IC_TAG_HI will mean a change to the code as
|
|
// well. Changing the IC_TAG_HI param alone is *not* enough to
|
|
// change the PA range.
|
|
// highest bit of PA
|
|
|
|
|
|
|
|
// Derived Values
|
|
// 4095
|
|
|
|
|
|
// number of entries - 1 = 511
|
|
|
|
|
|
// 12
|
|
|
|
|
|
// 28
|
|
|
|
|
|
// 7
|
|
|
|
|
|
// tags for all 4 ways + parity
|
|
// 116
|
|
|
|
|
|
// 115
|
|
|
|
|
|
|
|
//----------------------------------------------------------------------
|
|
// For thread scheduler in IFU::DTU::SWL
|
|
//----------------------------------------------------------------------
|
|
// thread states: (thr_state[4:0])
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// thread configuration register bit fields
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
//----------------------------------------------------------------------
|
|
// For MIL fsm in IFU::IFQ
|
|
//----------------------------------------------------------------------
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
//---------------------------------------------------
|
|
// Interrupt Block
|
|
//---------------------------------------------------
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
//-------------------------------------
|
|
// IFQ
|
|
//-------------------------------------
|
|
// valid bit plus ifill
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
//`ifdef SPARC_L2_64B
|
|
|
|
|
|
//`else
|
|
//`define BANK_ID_HI 8
|
|
//`define BANK_ID_LO 7
|
|
//`endif
|
|
|
|
//`define CPX_INV_PA_HI 116
|
|
//`define CPX_INV_PA_LO 112
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
//----------------------------------------
|
|
// IFU Traps
|
|
//----------------------------------------
|
|
// precise
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// disrupting
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
`define NOP 32'h01000000
|
|
`define PO_RESET_PC 48'hfffff0000020
|
|
`define VER_MANUF 16'h003e
|
|
`define VER_IMPL 16'h0023
|
|
`define VER_MAXGL 8'h03
|
|
`define VER_MAXWIN 8'h07
|
|
`define VER_MAXTL 8'h06
|
|
|
//`define VER_MAXTL {5'b0, fcl_fdp_hprivmode_e, 2'b10}
|
//`define VER_MAXTL {5'b0, fcl_fdp_hprivmode_e, 2'b10}
|
//`define VER_IMPL_MASK 24'h002301
|
//`define VER_IMPL_MASK 24'h002301
|
|
|
//`define VERSION_REG_HPV {`VER_MANUF, `VER_IMPL_MASK, `VER_MAXGL, 5'b0, fcl_fdp_hprivmode_e, 2'b10, `VER_MAXWIN}
|
//`define VERSION_REG_HPV {`VER_MANUF, `VER_IMPL_MASK, `VER_MAXGL, 5'b0, fcl_fdp_hprivmode_e, 2'b10, `VER_MAXWIN}
|
|
|
//`define VERSION_REG {`VER_MANUF, `VER_IMPL_MASK, `VER_MAXGL, 8'h06, `VER_MAXWIN}
|
//`define VERSION_REG {`VER_MANUF, `VER_IMPL_MASK, `VER_MAXGL, 8'h06, `VER_MAXWIN}
|
|
|
//FPGA_SYN enables all FPGA related modifications
|
//FPGA_SYN enables all FPGA related modifications
|
|
`ifdef FPGA_SYN
|
|
`define FPGA_SYN_CLK_EN
|
|
`define FPGA_SYN_CLK_DFF
|
|
`endif
|
|
|
module sparc_ifu_fdp(/*AUTOARG*/
|
module sparc_ifu_fdp(/*AUTOARG*/
|
// Outputs
|
// Outputs
|
so, fdp_itlb_ctxt_bf, fdp_icd_vaddr_bf, fdp_icv_index_bf,
|
so, fdp_itlb_ctxt_bf, fdp_icd_vaddr_bf, fdp_icv_index_bf,
|
fdp_erb_pc_f, fdp_dtu_inst_s, ifu_exu_pc_d, ifu_exu_rs1_s,
|
fdp_erb_pc_f, fdp_dtu_inst_s, ifu_exu_pc_d, ifu_exu_rs1_s,
|
| Line 498... |
Line 324... |
//----------------------------------------------------------------------
|
//----------------------------------------------------------------------
|
// Context Reg
|
// Context Reg
|
//----------------------------------------------------------------------
|
//----------------------------------------------------------------------
|
assign t0_ctxt_bf = lsu_t0_pctxt_state & {13{fcl_fdp_tctxt_sel_prim[0]}};
|
assign t0_ctxt_bf = lsu_t0_pctxt_state & {13{fcl_fdp_tctxt_sel_prim[0]}};
|
|
|
|
`ifdef FPGA_SYN_1THREAD
|
|
|
|
assign sw_ctxt = t0_ctxt_bf;
|
|
assign curr_ctxt = t0_ctxt_bf;
|
|
assign dmp_ctxt_unq = lsu_t0_pctxt_state;
|
|
|
|
`else
|
|
|
|
|
|
|
|
|
|
|
assign t1_ctxt_bf = lsu_t1_pctxt_state & {13{fcl_fdp_tctxt_sel_prim[1]}};
|
assign t1_ctxt_bf = lsu_t1_pctxt_state & {13{fcl_fdp_tctxt_sel_prim[1]}};
|
assign t2_ctxt_bf = lsu_t2_pctxt_state & {13{fcl_fdp_tctxt_sel_prim[2]}};
|
assign t2_ctxt_bf = lsu_t2_pctxt_state & {13{fcl_fdp_tctxt_sel_prim[2]}};
|
assign t3_ctxt_bf = lsu_t3_pctxt_state & {13{fcl_fdp_tctxt_sel_prim[3]}};
|
assign t3_ctxt_bf = lsu_t3_pctxt_state & {13{fcl_fdp_tctxt_sel_prim[3]}};
|
|
|
| Line 539... |
Line 365... |
.in3 (lsu_t3_pctxt_state),
|
.in3 (lsu_t3_pctxt_state),
|
.sel0_l (fcl_fdp_dmpthr_l[0]),
|
.sel0_l (fcl_fdp_dmpthr_l[0]),
|
.sel1_l (fcl_fdp_dmpthr_l[1]),
|
.sel1_l (fcl_fdp_dmpthr_l[1]),
|
.sel2_l (fcl_fdp_dmpthr_l[2]),
|
.sel2_l (fcl_fdp_dmpthr_l[2]),
|
.sel3_l (fcl_fdp_dmpthr_l[3]));
|
.sel3_l (fcl_fdp_dmpthr_l[3]));
|
// !`ifdef FPGA_SYN_1THREAD
|
`endif // !`ifdef FPGA_SYN_1THREAD
|
|
|
assign dmp_ctxt1 = dmp_ctxt_unq & {13{~(tlu_itlb_dmp_nctxt_g |
|
assign dmp_ctxt1 = dmp_ctxt_unq & {13{~(tlu_itlb_dmp_nctxt_g |
|
tlu_itlb_dmp_actxt_g)}};
|
tlu_itlb_dmp_actxt_g)}};
|
//`ifdef SPARC_HPV_EN
|
//`ifdef SPARC_HPV_EN
|
assign dmp_ctxt2 = {tlu_itlb_tte_tag_w2[12:7],tlu_itlb_tte_tag_w2[6:0]} &
|
assign dmp_ctxt2 = {tlu_itlb_tte_tag_w2[12:7],tlu_itlb_tte_tag_w2[6:0]} &
|
| Line 570... |
Line 396... |
|
|
// pc/thr to exu for rdsr instruction
|
// pc/thr to exu for rdsr instruction
|
// this is the only 64 bit cell in the IFU
|
// this is the only 64 bit cell in the IFU
|
dp_mux3ds #(64) ver_mux(.dout (ifu_exu_pcver_e[63:0]),
|
dp_mux3ds #(64) ver_mux(.dout (ifu_exu_pcver_e[63:0]),
|
.in0 ({{16{pc_e[47]}}, pc_e[47:0]}),
|
.in0 ({{16{pc_e[47]}}, pc_e[47:0]}),
|
.in1 ({16'h003e,
|
.in1 ({`VER_MANUF,
|
16'h0023,
|
`VER_IMPL,
|
const_maskid[7:0],
|
const_maskid[7:0],
|
8'h03,
|
`VER_MAXGL,
|
8'h06,
|
`VER_MAXTL,
|
8'h07}),
|
`VER_MAXWIN}),
|
.in2 ({12'b0,
|
.in2 ({12'b0,
|
dtu_fdp_thrconf_e[40:29],
|
dtu_fdp_thrconf_e[40:29],
|
4'b0,
|
4'b0,
|
dtu_fdp_thrconf_e[28:9],
|
dtu_fdp_thrconf_e[28:9],
|
2'b0,
|
2'b0,
|
| Line 599... |
Line 425... |
.sel0_l (fcl_fdp_tpcbf_sel_old_bf_l[0]),
|
.sel0_l (fcl_fdp_tpcbf_sel_old_bf_l[0]),
|
.sel1_l (fcl_fdp_tpcbf_sel_pcp4_bf_l[0]),
|
.sel1_l (fcl_fdp_tpcbf_sel_pcp4_bf_l[0]),
|
.sel2_l (fcl_fdp_tpcbf_sel_trap_bf_l[0]),
|
.sel2_l (fcl_fdp_tpcbf_sel_trap_bf_l[0]),
|
.sel3_l (fcl_fdp_tpcbf_sel_brpc_bf_l[0]));
|
.sel3_l (fcl_fdp_tpcbf_sel_brpc_bf_l[0]));
|
|
|
|
`ifdef FPGA_SYN_1THREAD
|
|
`else
|
dp_mux4ds #(49) t1_pcbf_mux(.dout (t1npc_bf),
|
dp_mux4ds #(49) t1_pcbf_mux(.dout (t1npc_bf),
|
.in0 ({fcl_fdp_pcoor_vec_f[1], t1pc_f[47:0]}),
|
.in0 ({fcl_fdp_pcoor_vec_f[1], t1pc_f[47:0]}),
|
.in1 (nextpc_nosw_bf),
|
.in1 (nextpc_nosw_bf),
|
.in2 (t1_trap_rb_pc_bf),
|
.in2 (t1_trap_rb_pc_bf),
|
.in3 ({1'b0, exu_ifu_brpc_e}),
|
.in3 ({1'b0, exu_ifu_brpc_e}),
|
| Line 630... |
Line 456... |
.in3 ({1'b0, exu_ifu_brpc_e}),
|
.in3 ({1'b0, exu_ifu_brpc_e}),
|
.sel0_l (fcl_fdp_tpcbf_sel_old_bf_l[3]),
|
.sel0_l (fcl_fdp_tpcbf_sel_old_bf_l[3]),
|
.sel1_l (fcl_fdp_tpcbf_sel_pcp4_bf_l[3]),
|
.sel1_l (fcl_fdp_tpcbf_sel_pcp4_bf_l[3]),
|
.sel2_l (fcl_fdp_tpcbf_sel_trap_bf_l[3]),
|
.sel2_l (fcl_fdp_tpcbf_sel_trap_bf_l[3]),
|
.sel3_l (fcl_fdp_tpcbf_sel_brpc_bf_l[3]));
|
.sel3_l (fcl_fdp_tpcbf_sel_brpc_bf_l[3]));
|
|
`endif
|
|
|
// F stage thread PC regs; use low power thr flop
|
// F stage thread PC regs; use low power thr flop
|
dff #(49) t0_pcf_reg(.din (t0npc_bf),
|
dff_s #(49) t0_pcf_reg(.din (t0npc_bf),
|
.clk (clk),
|
.clk (clk),
|
.q (t0pc_f),
|
.q (t0pc_f),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
`ifdef FPGA_SYN_1THREAD
|
|
assign fdp_fcl_pc_oor_vec_f = {3'b0, t0pc_f[48]};
|
|
assign swpc_bf = t0pc_f[47:0];
|
|
`else
|
dff #(49) t1_pcf_reg(.din (t1npc_bf),
|
dff_s #(49) t1_pcf_reg(.din (t1npc_bf),
|
.clk (clk),
|
.clk (clk),
|
.q (t1pc_f),
|
.q (t1pc_f),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
dff #(49) t2_pcf_reg(.din (t2npc_bf),
|
dff_s #(49) t2_pcf_reg(.din (t2npc_bf),
|
.clk (clk),
|
.clk (clk),
|
.q (t2pc_f),
|
.q (t2pc_f),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
dff #(49) t3_pcf_reg(.din (t3npc_bf),
|
dff_s #(49) t3_pcf_reg(.din (t3npc_bf),
|
.clk (clk),
|
.clk (clk),
|
.q (t3pc_f),
|
.q (t3pc_f),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign fdp_fcl_pc_oor_vec_f = {t3pc_f[48], t2pc_f[48],
|
assign fdp_fcl_pc_oor_vec_f = {t3pc_f[48], t2pc_f[48],
|
t1pc_f[48], t0pc_f[48]};
|
t1pc_f[48], t0pc_f[48]};
|
|
|
|
|
| Line 668... |
Line 494... |
.in3 (t3pc_f[47:0]),
|
.in3 (t3pc_f[47:0]),
|
.sel0_l (fcl_fdp_next_thr_bf_l[0]),
|
.sel0_l (fcl_fdp_next_thr_bf_l[0]),
|
.sel1_l (fcl_fdp_next_thr_bf_l[1]),
|
.sel1_l (fcl_fdp_next_thr_bf_l[1]),
|
.sel2_l (fcl_fdp_next_thr_bf_l[2]),
|
.sel2_l (fcl_fdp_next_thr_bf_l[2]),
|
.sel3_l (fcl_fdp_next_thr_bf_l[3]));
|
.sel3_l (fcl_fdp_next_thr_bf_l[3]));
|
|
`endif
|
|
|
// choose between I$ write address and read address
|
// choose between I$ write address and read address
|
// need mux only for lower 11 bits (2+3 + ICINDEX_SIZE)
|
// need mux only for lower 11 bits (2+3 + ICINDEX_SIZE)
|
// dp_mux2es #(48) ifqfdp_mux(.dout (icaddr_nosw_bf[47:0]),
|
// dp_mux2es #(48) ifqfdp_mux(.dout (icaddr_nosw_bf[47:0]),
|
// .in0 (nextpc_nosw_bf[47:0]),
|
// .in0 (nextpc_nosw_bf[47:0]),
|
| Line 708... |
Line 534... |
.in2 (exu_ifu_brpc_e[47:0]),
|
.in2 (exu_ifu_brpc_e[47:0]),
|
.sel0_l (fcl_fdp_pcbf_sel_swpc_bf_l),
|
.sel0_l (fcl_fdp_pcbf_sel_swpc_bf_l),
|
.sel1_l (fcl_fdp_pcbf_sel_nosw_bf_l),
|
.sel1_l (fcl_fdp_pcbf_sel_nosw_bf_l),
|
.sel2_l (fcl_fdp_pcbf_sel_br_bf_l));
|
.sel2_l (fcl_fdp_pcbf_sel_br_bf_l));
|
|
|
dff #(48) pcf_reg(.din (pc_bf),
|
dff_s #(48) pcf_reg(.din (pc_bf),
|
.clk (clk),
|
.clk (clk),
|
.q (pc_f),
|
.q (pc_f),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign fdp_erb_pc_f = pc_f[47:0];
|
assign fdp_erb_pc_f = pc_f[47:0];
|
|
|
// trappc mux (choose trap pc vs rollback/uTrap pc)
|
// trappc mux (choose trap pc vs rollback/uTrap pc)
|
dp_mux4ds #(49) trap_pc0_mux(.dout (t0_trap_rb_pc_bf),
|
dp_mux4ds #(49) trap_pc0_mux(.dout (t0_trap_rb_pc_bf),
|
| Line 726... |
Line 552... |
.sel0_l (fcl_fdp_trrbpc_sel_trap_bf_l[0]),
|
.sel0_l (fcl_fdp_trrbpc_sel_trap_bf_l[0]),
|
.sel1_l (fcl_fdp_trrbpc_sel_rb_bf_l[0]),
|
.sel1_l (fcl_fdp_trrbpc_sel_rb_bf_l[0]),
|
.sel2_l (fcl_fdp_trrbpc_sel_pcs_bf_l[0]),
|
.sel2_l (fcl_fdp_trrbpc_sel_pcs_bf_l[0]),
|
.sel3_l (fcl_fdp_trrbpc_sel_err_bf_l[0]));
|
.sel3_l (fcl_fdp_trrbpc_sel_err_bf_l[0]));
|
|
|
|
`ifdef FPGA_SYN_1THREAD
|
|
`else
|
dp_mux4ds #(49) trap_pc1_mux(.dout (t1_trap_rb_pc_bf),
|
dp_mux4ds #(49) trap_pc1_mux(.dout (t1_trap_rb_pc_bf),
|
.in0 (tlu_ifu_trappc_w2),
|
.in0 (tlu_ifu_trappc_w2),
|
.in1 (pc_d_adj),
|
.in1 (pc_d_adj),
|
.in2 (t1pc_s),
|
.in2 (t1pc_s),
|
.in3 (pc_w),
|
.in3 (pc_w),
|
| Line 757... |
Line 583... |
.in3 (pc_w),
|
.in3 (pc_w),
|
.sel0_l (fcl_fdp_trrbpc_sel_trap_bf_l[3]),
|
.sel0_l (fcl_fdp_trrbpc_sel_trap_bf_l[3]),
|
.sel1_l (fcl_fdp_trrbpc_sel_rb_bf_l[3]),
|
.sel1_l (fcl_fdp_trrbpc_sel_rb_bf_l[3]),
|
.sel2_l (fcl_fdp_trrbpc_sel_pcs_bf_l[3]),
|
.sel2_l (fcl_fdp_trrbpc_sel_pcs_bf_l[3]),
|
.sel3_l (fcl_fdp_trrbpc_sel_err_bf_l[3]));
|
.sel3_l (fcl_fdp_trrbpc_sel_err_bf_l[3]));
|
|
`endif
|
|
|
|
|
// can reduce this to a 2:1 mux since reset pc is not used any more and
|
// can reduce this to a 2:1 mux since reset pc is not used any more and
|
// pc_f is not needed.
|
// pc_f is not needed.
|
dp_mux3ds #(49) pcp4_mux(.dout (nextpc_nosw_bf),
|
dp_mux3ds #(49) pcp4_mux(.dout (nextpc_nosw_bf),
|
| Line 784... |
Line 610... |
.sel0_l (fcl_fdp_nextpcs_sel_pcs_f_l[0]),
|
.sel0_l (fcl_fdp_nextpcs_sel_pcs_f_l[0]),
|
.sel1_l (fcl_fdp_nextpcs_sel_pcf_f_l[0]),
|
.sel1_l (fcl_fdp_nextpcs_sel_pcf_f_l[0]),
|
.sel2_l (fcl_fdp_nextpcs_sel_pcd_f_l[0]),
|
.sel2_l (fcl_fdp_nextpcs_sel_pcd_f_l[0]),
|
.sel3_l (fcl_fdp_nextpcs_sel_pce_f_l[0]));
|
.sel3_l (fcl_fdp_nextpcs_sel_pce_f_l[0]));
|
|
|
|
`ifdef FPGA_SYN_1THREAD
|
|
`else
|
dp_mux4ds #(49) t1pcf_mux(.dout (t1_next_pcs_f),
|
dp_mux4ds #(49) t1pcf_mux(.dout (t1_next_pcs_f),
|
.in0 (t1pc_s),
|
.in0 (t1pc_s),
|
.in1 ({fcl_fdp_pcoor_vec_f[1], t1pc_f[47:0]}),
|
.in1 ({fcl_fdp_pcoor_vec_f[1], t1pc_f[47:0]}),
|
.in2 (pc_d_adj),
|
.in2 (pc_d_adj),
|
.in3 (pc_e),
|
.in3 (pc_e),
|
| Line 817... |
Line 643... |
.in3 (pc_e),
|
.in3 (pc_e),
|
.sel0_l (fcl_fdp_nextpcs_sel_pcs_f_l[3]),
|
.sel0_l (fcl_fdp_nextpcs_sel_pcs_f_l[3]),
|
.sel1_l (fcl_fdp_nextpcs_sel_pcf_f_l[3]),
|
.sel1_l (fcl_fdp_nextpcs_sel_pcf_f_l[3]),
|
.sel2_l (fcl_fdp_nextpcs_sel_pcd_f_l[3]),
|
.sel2_l (fcl_fdp_nextpcs_sel_pcd_f_l[3]),
|
.sel3_l (fcl_fdp_nextpcs_sel_pce_f_l[3]));
|
.sel3_l (fcl_fdp_nextpcs_sel_pce_f_l[3]));
|
|
`endif
|
|
|
|
|
// S stage thread PC regs; use low power thr flop
|
// S stage thread PC regs; use low power thr flop
|
dff #(49) t0pcs_reg(.din (t0_next_pcs_f),
|
dff_s #(49) t0pcs_reg(.din (t0_next_pcs_f),
|
.q (t0pc_s),
|
.q (t0pc_s),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
`ifdef FPGA_SYN_1THREAD
|
|
assign pc_s = t0pc_s;
|
|
assign npc_s = t0_next_pcs_f;
|
|
`else
|
dff #(49) t1pcs_reg(.din (t1_next_pcs_f),
|
dff_s #(49) t1pcs_reg(.din (t1_next_pcs_f),
|
.q (t1pc_s),
|
.q (t1pc_s),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff #(49) t2pcs_reg(.din (t2_next_pcs_f),
|
dff_s #(49) t2pcs_reg(.din (t2_next_pcs_f),
|
.q (t2pc_s),
|
.q (t2pc_s),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff #(49) t3pcs_reg(.din (t3_next_pcs_f),
|
dff_s #(49) t3pcs_reg(.din (t3_next_pcs_f),
|
.q (t3pc_s),
|
.q (t3pc_s),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// S stage PC mux -- need to protect
|
// S stage PC mux -- need to protect
|
dp_mux4ds #(49) pcs_mux(.dout (pc_s),
|
dp_mux4ds #(49) pcs_mux(.dout (pc_s),
|
.in0 (t0pc_s),
|
.in0 (t0pc_s),
|
.in1 (t1pc_s),
|
.in1 (t1pc_s),
|
| Line 859... |
Line 685... |
.in3 (t3_next_pcs_f),
|
.in3 (t3_next_pcs_f),
|
.sel0_l (fcl_fdp_thr_s2_l[0]),
|
.sel0_l (fcl_fdp_thr_s2_l[0]),
|
.sel1_l (fcl_fdp_thr_s2_l[1]),
|
.sel1_l (fcl_fdp_thr_s2_l[1]),
|
.sel2_l (fcl_fdp_thr_s2_l[2]),
|
.sel2_l (fcl_fdp_thr_s2_l[2]),
|
.sel3_l (fcl_fdp_thr_s2_l[3]));
|
.sel3_l (fcl_fdp_thr_s2_l[3]));
|
|
`endif
|
|
|
// D stage PC and nPC
|
// D stage PC and nPC
|
dff #(49) pcd_reg(.din (pc_s),
|
dff_s #(49) pcd_reg(.din (pc_s),
|
.q (pc_d),
|
.q (pc_d),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff #(49) npcd_reg(.din (npc_s),
|
dff_s #(49) npcd_reg(.din (npc_s),
|
.q (npc_d),
|
.q (npc_d),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign am_mask = {{17{~fcl_fdp_addr_mask_d}}, 32'hffffffff};
|
assign am_mask = {{17{~fcl_fdp_addr_mask_d}}, 32'hffffffff};
|
|
|
// nand2
|
// nand2
|
assign pc_d_adj = pc_d & am_mask;
|
assign pc_d_adj = pc_d & am_mask;
|
assign npc_d_adj = npc_d & am_mask;
|
assign npc_d_adj = npc_d & am_mask;
|
|
|
assign ifu_exu_pc_d = pc_d_adj[47:0];
|
assign ifu_exu_pc_d = pc_d_adj[47:0];
|
|
|
// E stage PC and nPC
|
// E stage PC and nPC
|
dff #(49) pce_reg(.din (pc_d_adj),
|
dff_s #(49) pce_reg(.din (pc_d_adj),
|
.q (pc_e),
|
.q (pc_e),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff #(49) npce_reg(.din (npc_d_adj),
|
dff_s #(49) npce_reg(.din (npc_d_adj),
|
.q (npc_e),
|
.q (npc_e),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign fdp_fcl_pc_oor_e = pc_e[48];
|
assign fdp_fcl_pc_oor_e = pc_e[48];
|
assign ifu_tlu_pc_oor_e = pc_e[48];
|
assign ifu_tlu_pc_oor_e = pc_e[48];
|
|
|
// M stage PC and nPC
|
// M stage PC and nPC
|
dff #(49) pcm_reg(.din (pc_e),
|
dff_s #(49) pcm_reg(.din (pc_e),
|
.q (pc_m),
|
.q (pc_m),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff #(49) npcm_reg(.din (npc_e),
|
dff_s #(49) npcm_reg(.din (npc_e),
|
.q (npc_m),
|
.q (npc_m),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
assign ifu_tlu_pc_m = pc_m[48:0];
|
assign ifu_tlu_pc_m = pc_m[48:0];
|
assign ifu_tlu_npc_m = npc_m[48:0];
|
assign ifu_tlu_npc_m = npc_m[48:0];
|
|
|
// W stage PC and nPC
|
// W stage PC and nPC
|
dff #(49) pcw_reg(.din (pc_m),
|
dff_s #(49) pcw_reg(.din (pc_m),
|
.q (pc_w),
|
.q (pc_w),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff #(49) npcw_reg(.din (npc_m),
|
dff_s #(49) npcw_reg(.din (npc_m),
|
.q (npc_w),
|
.q (npc_w),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// assign ifu_tlu_pc_w = pc_w;
|
// assign ifu_tlu_pc_w = pc_w;
|
// assign ifu_tlu_npc_w = npc_w;
|
// assign ifu_tlu_npc_w = npc_w;
|
|
|
// PC incrementer
|
// PC incrementer
|
| Line 931... |
Line 757... |
.sel0_l (fcl_fdp_thrtnpc_sel_tnpc_l[0]),
|
.sel0_l (fcl_fdp_thrtnpc_sel_tnpc_l[0]),
|
.sel1_l (fcl_fdp_thrtnpc_sel_npcw_l[0]),
|
.sel1_l (fcl_fdp_thrtnpc_sel_npcw_l[0]),
|
.sel2_l (fcl_fdp_thrtnpc_sel_pcf_l[0]),
|
.sel2_l (fcl_fdp_thrtnpc_sel_pcf_l[0]),
|
.sel3_l (fcl_fdp_thrtnpc_sel_old_l[0]));
|
.sel3_l (fcl_fdp_thrtnpc_sel_old_l[0]));
|
|
|
|
`ifdef FPGA_SYN_1THREAD
|
|
`else
|
dp_mux4ds #(49) t1tnpc_mux(.dout (trapnpc1_bf),
|
dp_mux4ds #(49) t1tnpc_mux(.dout (trapnpc1_bf),
|
.in0 (tlu_ifu_trapnpc_w2),
|
.in0 (tlu_ifu_trapnpc_w2),
|
.in1 (npc_w),
|
.in1 (npc_w),
|
.in2 (t1pc_f),
|
.in2 (t1pc_f),
|
.in3 (t1_trapnpc_f),
|
.in3 (t1_trapnpc_f),
|
| Line 962... |
Line 788... |
.in3 (t3_trapnpc_f),
|
.in3 (t3_trapnpc_f),
|
.sel0_l (fcl_fdp_thrtnpc_sel_tnpc_l[3]),
|
.sel0_l (fcl_fdp_thrtnpc_sel_tnpc_l[3]),
|
.sel1_l (fcl_fdp_thrtnpc_sel_npcw_l[3]),
|
.sel1_l (fcl_fdp_thrtnpc_sel_npcw_l[3]),
|
.sel2_l (fcl_fdp_thrtnpc_sel_pcf_l[3]),
|
.sel2_l (fcl_fdp_thrtnpc_sel_pcf_l[3]),
|
.sel3_l (fcl_fdp_thrtnpc_sel_old_l[3]));
|
.sel3_l (fcl_fdp_thrtnpc_sel_old_l[3]));
|
|
`endif
|
|
|
// thread next trap pc reg
|
// thread next trap pc reg
|
dff #(49) t0tnpcf_reg(.din (trapnpc0_bf),
|
dff_s #(49) t0tnpcf_reg(.din (trapnpc0_bf),
|
.q (t0_trapnpc_f),
|
.q (t0_trapnpc_f),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
`ifdef FPGA_SYN_1THREAD
|
|
assign thr_trappc_bf = t0_trapnpc_f;
|
|
`else
|
dff #(49) t1tnpcf_reg(.din (trapnpc1_bf),
|
dff_s #(49) t1tnpcf_reg(.din (trapnpc1_bf),
|
.q (t1_trapnpc_f),
|
.q (t1_trapnpc_f),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff #(49) t2tnpcf_reg(.din (trapnpc2_bf),
|
dff_s #(49) t2tnpcf_reg(.din (trapnpc2_bf),
|
.q (t2_trapnpc_f),
|
.q (t2_trapnpc_f),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff #(49) t3tnpcf_reg(.din (trapnpc3_bf),
|
dff_s #(49) t3tnpcf_reg(.din (trapnpc3_bf),
|
.q (t3_trapnpc_f),
|
.q (t3_trapnpc_f),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dp_mux4ds #(49) nxttpc_mux(.dout (thr_trappc_bf),
|
dp_mux4ds #(49) nxttpc_mux(.dout (thr_trappc_bf),
|
.in0 (t0_trapnpc_f),
|
.in0 (t0_trapnpc_f),
|
.in1 (t1_trapnpc_f),
|
.in1 (t1_trapnpc_f),
|
.in2 (t2_trapnpc_f),
|
.in2 (t2_trapnpc_f),
|
.in3 (t3_trapnpc_f),
|
.in3 (t3_trapnpc_f),
|
.sel0_l (fcl_fdp_thr_s2_l[0]), // thr_s2 = thr_f
|
.sel0_l (fcl_fdp_thr_s2_l[0]), // thr_s2 = thr_f
|
.sel1_l (fcl_fdp_thr_s2_l[1]),
|
.sel1_l (fcl_fdp_thr_s2_l[1]),
|
.sel2_l (fcl_fdp_thr_s2_l[2]),
|
.sel2_l (fcl_fdp_thr_s2_l[2]),
|
.sel3_l (fcl_fdp_thr_s2_l[3]));
|
.sel3_l (fcl_fdp_thr_s2_l[3]));
|
|
`endif
|
|
|
// During rst nextpc_nosw_bf = PO_RESET_PC. All thread PC_f registers,
|
// During rst nextpc_nosw_bf = PO_RESET_PC. All thread PC_f registers,
|
// the icaddr_f register and the nextpc register should be loaded
|
// the icaddr_f register and the nextpc register should be loaded
|
// with nextpc_nosw_bf during reset.
|
// with nextpc_nosw_bf during reset.
|
// Eventually, we will load the reset_pc from the trap logic unit,
|
// Eventually, we will load the reset_pc from the trap logic unit,
|
| Line 1027... |
Line 853... |
// Instruction Output Mux
|
// Instruction Output Mux
|
// CHANGE: now 4:1
|
// CHANGE: now 4:1
|
dp_mux4ds #(33) instout_mux(.dout (fdp_inst_s),
|
dp_mux4ds #(33) instout_mux(.dout (fdp_inst_s),
|
.in0 (icd_fdp_fetdata_s1[32:0]),
|
.in0 (icd_fdp_fetdata_s1[32:0]),
|
.in1 (inst_s2),
|
.in1 (inst_s2),
|
.in2 ({32'h01000000, 1'b0}),
|
.in2 ({`NOP, 1'b0}),
|
.in3 (nirdata_s1[32:0]),
|
.in3 (nirdata_s1[32:0]),
|
.sel0_l (fcl_fdp_inst_sel_curr_s_l),
|
.sel0_l (fcl_fdp_inst_sel_curr_s_l),
|
.sel1_l (fcl_fdp_inst_sel_switch_s_l),
|
.sel1_l (fcl_fdp_inst_sel_switch_s_l),
|
.sel2_l (fcl_fdp_inst_sel_nop_s_l),
|
.sel2_l (fcl_fdp_inst_sel_nop_s_l),
|
.sel3_l (fcl_fdp_inst_sel_nir_s_l));
|
.sel3_l (fcl_fdp_inst_sel_nir_s_l));
|
| Line 1072... |
Line 898... |
.sel0_l (fcl_fdp_tinst_sel_ifq_s_l[0]),
|
.sel0_l (fcl_fdp_tinst_sel_ifq_s_l[0]),
|
.sel1_l (fcl_fdp_tinst_sel_curr_s_l[0]),
|
.sel1_l (fcl_fdp_tinst_sel_curr_s_l[0]),
|
.sel2_l (fcl_fdp_tinst_sel_old_s_l[0]),
|
.sel2_l (fcl_fdp_tinst_sel_old_s_l[0]),
|
.sel3_l (fcl_fdp_tinst_sel_rb_s_l[0]));
|
.sel3_l (fcl_fdp_tinst_sel_rb_s_l[0]));
|
|
|
|
`ifdef FPGA_SYN_1THREAD
|
|
`else
|
dp_mux4ds #(33) t1inst_mux(.dout (t1inst_s1),
|
dp_mux4ds #(33) t1inst_mux(.dout (t1inst_s1),
|
.in0 (ifq_fdp_fill_inst),
|
.in0 (ifq_fdp_fill_inst),
|
.in1 (inst_s1_bf1),
|
.in1 (inst_s1_bf1),
|
.in2 (t1inst_s2),
|
.in2 (t1inst_s2),
|
.in3 (rb_inst1_s),
|
.in3 (rb_inst1_s),
|
| Line 1103... |
Line 929... |
.in3 (rb_inst3_s),
|
.in3 (rb_inst3_s),
|
.sel0_l (fcl_fdp_tinst_sel_ifq_s_l[3]),
|
.sel0_l (fcl_fdp_tinst_sel_ifq_s_l[3]),
|
.sel1_l (fcl_fdp_tinst_sel_curr_s_l[3]),
|
.sel1_l (fcl_fdp_tinst_sel_curr_s_l[3]),
|
.sel2_l (fcl_fdp_tinst_sel_old_s_l[3]),
|
.sel2_l (fcl_fdp_tinst_sel_old_s_l[3]),
|
.sel3_l (fcl_fdp_tinst_sel_rb_s_l[3]));
|
.sel3_l (fcl_fdp_tinst_sel_rb_s_l[3]));
|
|
`endif
|
|
|
// Thread Instruction Register
|
// Thread Instruction Register
|
dff #(33) t0_inst_reg(.din (t0inst_s1),
|
dff_s #(33) t0_inst_reg(.din (t0inst_s1),
|
.q (t0inst_s2),
|
.q (t0inst_s2),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
`ifdef FPGA_SYN_1THREAD
|
|
assign inst_s2 = t0inst_s2;
|
|
`else
|
dff #(33) t1_inst_reg(.din (t1inst_s1),
|
dff_s #(33) t1_inst_reg(.din (t1inst_s1),
|
.q (t1inst_s2),
|
.q (t1inst_s2),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff #(33) t2_inst_reg(.din (t2inst_s1),
|
dff_s #(33) t2_inst_reg(.din (t2inst_s1),
|
.q (t2inst_s2),
|
.q (t2inst_s2),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff #(33) t3_inst_reg(.din (t3inst_s1),
|
dff_s #(33) t3_inst_reg(.din (t3inst_s1),
|
.q (t3inst_s2),
|
.q (t3inst_s2),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// switch instruction mux -- choose the instruction to switch to
|
// switch instruction mux -- choose the instruction to switch to
|
// fcl keep track of which t*inst_s2 is valid
|
// fcl keep track of which t*inst_s2 is valid
|
dp_mux4ds #(33) swinst_mux(.dout (inst_s2),
|
dp_mux4ds #(33) swinst_mux(.dout (inst_s2),
|
.in0 (t0inst_s2),
|
.in0 (t0inst_s2),
|
| Line 1133... |
Line 959... |
.in3 (t3inst_s2),
|
.in3 (t3inst_s2),
|
.sel0_l (fcl_fdp_thr_s2_l[0]),
|
.sel0_l (fcl_fdp_thr_s2_l[0]),
|
.sel1_l (fcl_fdp_thr_s2_l[1]),
|
.sel1_l (fcl_fdp_thr_s2_l[1]),
|
.sel2_l (fcl_fdp_thr_s2_l[2]),
|
.sel2_l (fcl_fdp_thr_s2_l[2]),
|
.sel3_l (fcl_fdp_thr_s2_l[3]));
|
.sel3_l (fcl_fdp_thr_s2_l[3]));
|
|
`endif
|
|
|
// Rollback instruction
|
// Rollback instruction
|
dff #(33) rbinst_d_reg(.din (fdp_inst_s[32:0]),
|
dff_s #(33) rbinst_d_reg(.din (fdp_inst_s[32:0]),
|
.q (inst_d),
|
.q (inst_d),
|
.clk (clk),
|
.clk (clk),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff #(33) rbinst_e_reg(.din (inst_d),
|
dff_s #(33) rbinst_e_reg(.din (inst_d),
|
.q (inst_e),
|
.q (inst_e),
|
.clk (clk),
|
.clk (clk),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dp_mux2es #(33) rbinst0_mux(.dout (rb_inst0_s),
|
dp_mux2es #(33) rbinst0_mux(.dout (rb_inst0_s),
|
.in0 (inst_d),
|
.in0 (inst_d),
|
.in1 (inst_e),
|
.in1 (inst_e),
|
.sel (fcl_fdp_rbinst_sel_inste_s[0]));
|
.sel (fcl_fdp_rbinst_sel_inste_s[0]));
|
|
|
|
`ifdef FPGA_SYN_1THREAD
|
|
`else
|
dp_mux2es #(33) rbinst1_mux(.dout (rb_inst1_s),
|
dp_mux2es #(33) rbinst1_mux(.dout (rb_inst1_s),
|
.in0 (inst_d),
|
.in0 (inst_d),
|
.in1 (inst_e),
|
.in1 (inst_e),
|
.sel (fcl_fdp_rbinst_sel_inste_s[1]));
|
.sel (fcl_fdp_rbinst_sel_inste_s[1]));
|
|
|
| Line 1167... |
Line 993... |
|
|
dp_mux2es #(33) rbinst3_mux(.dout (rb_inst3_s),
|
dp_mux2es #(33) rbinst3_mux(.dout (rb_inst3_s),
|
.in0 (inst_d),
|
.in0 (inst_d),
|
.in1 (inst_e),
|
.in1 (inst_e),
|
.sel (fcl_fdp_rbinst_sel_inste_s[3]));
|
.sel (fcl_fdp_rbinst_sel_inste_s[3]));
|
|
`endif
|
|
|
//----------------------------------------------------------------------
|
//----------------------------------------------------------------------
|
// Next Instruction Datapath
|
// Next Instruction Datapath
|
//----------------------------------------------------------------------
|
//----------------------------------------------------------------------
|
|
|
| Line 1193... |
Line 1019... |
// .in1 (t3nir),
|
// .in1 (t3nir),
|
// .sel (fcl_fdp_thr_s1_l[3]));
|
// .sel (fcl_fdp_thr_s1_l[3]));
|
|
|
// Thread Next Instruction Register
|
// Thread Next Instruction Register
|
wire clk_nir0;
|
wire clk_nir0;
|
|
`ifdef FPGA_SYN_CLK_EN
|
|
`else
|
|
|
|
bw_u1_ckenbuf_6x ckennir0(.rclk (rclk),
|
|
.clk (clk_nir0),
|
|
.en_l (fcl_fdp_thr_s1_l[0]),
|
|
.tm_l (~se));
|
|
`endif
|
|
`ifdef FPGA_SYN_CLK_DFF
|
|
dffe_s #(33) t0nir_reg(.din (icd_fdp_topdata_s1[32:0]),
|
|
|
dffe #(33) t0nir_reg(.din (icd_fdp_topdata_s1[32:0]),
|
|
.q (t0nir),
|
.q (t0nir),
|
.en (~(fcl_fdp_thr_s1_l[0])), .clk(rclk), .se(se), .si(), .so());
|
.en (~(fcl_fdp_thr_s1_l[0])), .clk(rclk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
`else
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
dff_s #(33) t0nir_reg(.din (icd_fdp_topdata_s1[32:0]),
|
|
.q (t0nir),
|
|
.clk (clk_nir0), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
`endif
|
|
|
|
`ifdef FPGA_SYN_1THREAD
|
|
assign nirdata_s1 = t0nir;
|
|
`else
|
wire clk_nir1;
|
wire clk_nir1;
|
|
`ifdef FPGA_SYN_CLK_EN
|
|
`else
|
|
|
|
bw_u1_ckenbuf_6x ckennir1(.rclk (rclk),
|
|
.clk (clk_nir1),
|
|
.en_l (fcl_fdp_thr_s1_l[1]),
|
|
.tm_l (~se));
|
|
`endif
|
|
`ifdef FPGA_SYN_CLK_DFF
|
|
dffe_s #(33) t1nir_reg(.din (icd_fdp_topdata_s1[32:0]),
|
|
|
dffe #(33) t1nir_reg(.din (icd_fdp_topdata_s1[32:0]),
|
|
.q (t1nir),
|
.q (t1nir),
|
.en (~(fcl_fdp_thr_s1_l[1])), .clk (rclk), .se(se), .si(), .so());
|
.en (~(fcl_fdp_thr_s1_l[1])), .clk (rclk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
`else
|
|
dff_s #(33) t1nir_reg(.din (icd_fdp_topdata_s1[32:0]),
|
|
.q (t1nir),
|
|
.clk (clk_nir1), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
`endif
|
|
|
wire clk_nir2;
|
wire clk_nir2;
|
|
`ifdef FPGA_SYN_CLK_EN
|
|
`else
|
|
|
|
bw_u1_ckenbuf_6x ckennir2(.rclk (rclk),
|
|
.clk (clk_nir2),
|
|
.en_l (fcl_fdp_thr_s1_l[2]),
|
|
.tm_l (~se));
|
|
`endif
|
|
`ifdef FPGA_SYN_CLK_DFF
|
|
dffe_s #(33) t2nir_reg(.din (icd_fdp_topdata_s1[32:0]),
|
|
|
dffe #(33) t2nir_reg(.din (icd_fdp_topdata_s1[32:0]),
|
|
.q (t2nir),
|
.q (t2nir),
|
.en (~(fcl_fdp_thr_s1_l[2])), .clk (rclk), .se(se), .si(), .so());
|
.en (~(fcl_fdp_thr_s1_l[2])), .clk (rclk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
`else
|
|
dff_s #(33) t2nir_reg(.din (icd_fdp_topdata_s1[32:0]),
|
|
.q (t2nir),
|
|
.clk (clk_nir2), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
`endif
|
wire clk_nir3;
|
wire clk_nir3;
|
|
`ifdef FPGA_SYN_CLK_EN
|
|
`else
|
|
|
|
bw_u1_ckenbuf_6x ckennir3(.rclk (rclk),
|
|
.clk (clk_nir3),
|
|
.en_l (fcl_fdp_thr_s1_l[3]),
|
|
.tm_l (~se));
|
|
`endif
|
|
`ifdef FPGA_SYN_CLK_DFF
|
|
dffe_s #(33) t3nir_reg(.din (icd_fdp_topdata_s1[32:0]),
|
|
|
dffe #(33) t3nir_reg(.din (icd_fdp_topdata_s1[32:0]),
|
|
.q (t3nir),
|
.q (t3nir),
|
.en (~(fcl_fdp_thr_s1_l[3])), .clk (rclk), .se(se), .si(), .so());
|
.en (~(fcl_fdp_thr_s1_l[3])), .clk (rclk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
`else
|
|
|
|
|
|
|
|
|
|
|
|
dff_s #(33) t3nir_reg(.din (icd_fdp_topdata_s1[32:0]),
|
|
.q (t3nir),
|
|
.clk (clk_nir3), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
`endif
|
|
|
// Next thread NIR mux (nir output mux)
|
// Next thread NIR mux (nir output mux)
|
dp_mux4ds #(33) nextnir_mux(.dout (nirdata_s1),
|
dp_mux4ds #(33) nextnir_mux(.dout (nirdata_s1),
|
.in0 (t0nir),
|
.in0 (t0nir),
|
.in1 (t1nir),
|
.in1 (t1nir),
|
| Line 1282... |
Line 1108... |
.in3 (t3nir),
|
.in3 (t3nir),
|
.sel0_l (fcl_fdp_nirthr_s1_l[0]),
|
.sel0_l (fcl_fdp_nirthr_s1_l[0]),
|
.sel1_l (fcl_fdp_nirthr_s1_l[1]),
|
.sel1_l (fcl_fdp_nirthr_s1_l[1]),
|
.sel2_l (fcl_fdp_nirthr_s1_l[2]),
|
.sel2_l (fcl_fdp_nirthr_s1_l[2]),
|
.sel3_l (fcl_fdp_nirthr_s1_l[3]));
|
.sel3_l (fcl_fdp_nirthr_s1_l[3]));
|
|
`endif
|
|
|
// TBD in fetched instruction DP:
|
// TBD in fetched instruction DP:
|
// 1. Rollback -- DONE
|
// 1. Rollback -- DONE
|
// 2. Icache parity check (increase fet data and top data to 34 bits)
|
// 2. Icache parity check (increase fet data and top data to 34 bits)
|
|
|
