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Line 16... |
// You should have received a copy of the GNU General Public
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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//
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// ========== Copyright Header End ============================================
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// ========== Copyright Header End ============================================
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`ifdef SIMPLY_RISC_TWEAKS
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`define SIMPLY_RISC_SCANIN .si(0)
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`else
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`define SIMPLY_RISC_SCANIN .si()
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`endif
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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/*
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/*
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// Module Name: sparc_ifu_imd
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// Module Name: sparc_ifu_imd
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// Description:
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// Description:
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// Contains the immediate operand datapath. Has two outputs: The
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// Contains the immediate operand datapath. Has two outputs: The
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| Line 138... |
Line 143... |
//--------
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//--------
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// D stage
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// D stage
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// Contains the immediate data and branch offset muxes
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// Contains the immediate data and branch offset muxes
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//--------
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//--------
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dff #(32) inst_d_reg(.din (fdp_dtu_inst_s),
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dff_s #(32) inst_d_reg(.din (fdp_dtu_inst_s),
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.clk (clk),
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.clk (clk),
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.q (dtu_inst_d),
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.q (dtu_inst_d),
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.se (se), .si(), .so());
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.se (se), `SIMPLY_RISC_SCANIN, .so());
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dff #(1) ifu_lsu_imm_asi_inst(.din (fdp_dtu_inst_s[13]),
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dff_s #(1) ifu_lsu_imm_asi_inst(.din (fdp_dtu_inst_s[13]),
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.clk (clk),
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.clk (clk),
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.q (ifu_lsu_imm_asi_vld_f),
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.q (ifu_lsu_imm_asi_vld_f),
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.se (se), .si(), .so());
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.se (se), `SIMPLY_RISC_SCANIN, .so());
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assign imd_dcl_abit_d = dtu_inst_d[29];
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assign imd_dcl_abit_d = dtu_inst_d[29];
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// imm data select
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// imm data select
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// sext12:0 -- add/sub/and/or/xor/taggedOP/jmpl/ld/store/atomic/div/mul/popc
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// sext12:0 -- add/sub/and/or/xor/taggedOP/jmpl/ld/store/atomic/div/mul/popc
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Line 211... |
// if call instruction set rd = 0f (15)
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// if call instruction set rd = 0f (15)
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assign ifu_exu_rd_d[3:0] = dtu_inst_d[28:25] | {4{dcl_imd_call_inst_d}};
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assign ifu_exu_rd_d[3:0] = dtu_inst_d[28:25] | {4{dcl_imd_call_inst_d}};
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assign ifu_exu_rd_d[4] = (dtu_inst_d[29] & ~dcl_imd_call_inst_d) ^
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assign ifu_exu_rd_d[4] = (dtu_inst_d[29] & ~dcl_imd_call_inst_d) ^
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(ifu_exu_rd_d[3] & fcl_imd_oddwin_d);
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(ifu_exu_rd_d[3] & fcl_imd_oddwin_d);
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dff #(5) rde_ff(.din (ifu_exu_rd_d[4:0]),
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dff_s #(5) rde_ff(.din (ifu_exu_rd_d[4:0]),
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.clk (clk),
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.clk (clk),
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.q (ifu_lsu_rd_e[4:0]),
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.q (ifu_lsu_rd_e[4:0]),
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.se (se), .si(), .so());
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.se (se), `SIMPLY_RISC_SCANIN, .so());
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// read/write pr and read/write sr
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// read/write pr and read/write sr
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dp_mux2es #(5) sraddr_mux(.dout (sraddr5[4:0]),
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dp_mux2es #(5) sraddr_mux(.dout (sraddr5[4:0]),
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.in0 (dtu_inst_d[18:14]), // rs1 for rdpr
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.in0 (dtu_inst_d[18:14]), // rs1 for rdpr
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.in1 (dtu_inst_d[29:25]), // rd for wrpr
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.in1 (dtu_inst_d[29:25]), // rd for wrpr
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