| Line 16... |
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// You should have received a copy of the GNU General Public
|
// You should have received a copy of the GNU General Public
|
// License along with this work; if not, write to the Free Software
|
// License along with this work; if not, write to the Free Software
|
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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//
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// ========== Copyright Header End ============================================
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// ========== Copyright Header End ============================================
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`ifdef SIMPLY_RISC_TWEAKS
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`define SIMPLY_RISC_SCANIN .si(0)
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`else
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`define SIMPLY_RISC_SCANIN .si()
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`endif
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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/*
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/*
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// Module Name: sparc_ifu_swlthrfsm
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// Module Name: sparc_ifu_swlthrfsm
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// Description:
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// Description:
|
// The switch logithrfsm contains the thread state machine.
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// The switch logithrfsm contains the thread state machine.
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*/
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*/
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/*
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`include "ifu.h"
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/* ========== Copyright Header Begin ==========================================
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*
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* OpenSPARC T1 Processor File: ifu.h
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* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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*
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* The above named program is free software; you can redistribute it and/or
|
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* modify it under the terms of the GNU General Public
|
|
* License version 2 as published by the Free Software Foundation.
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*
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* The above named program is distributed in the hope that it will be
|
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* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public
|
|
* License along with this work; if not, write to the Free Software
|
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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*
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* ========== Copyright Header End ============================================
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*/
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////////////////////////////////////////////////////////////////////////
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/*
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//
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// Module Name: ifu.h
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// Description:
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// All ifu defines
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*/
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//--------------------------------------------
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// Icache Values in IFU::ICD/ICV/ICT/FDP/IFQDP
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//--------------------------------------------
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// Set Values
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// IC_IDX_HI = log(icache_size/4ways) - 1
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// !!IMPORTANT!! a change to IC_LINE_SZ will mean a change to the code as
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// well. Unfortunately this has not been properly parametrized.
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// Changing the IC_LINE_SZ param alone is *not* enough.
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// !!IMPORTANT!! a change to IC_TAG_HI will mean a change to the code as
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// well. Changing the IC_TAG_HI param alone is *not* enough to
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// change the PA range.
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// highest bit of PA
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// Derived Values
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// 4095
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// number of entries - 1 = 511
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// 12
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// 28
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// 7
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// tags for all 4 ways + parity
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// 116
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// 115
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//----------------------------------------------------------------------
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// For thread scheduler in IFU::DTU::SWL
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//----------------------------------------------------------------------
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// thread states: (thr_state[4:0])
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// thread configuration register bit fields
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//----------------------------------------------------------------------
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// For MIL fsm in IFU::IFQ
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//----------------------------------------------------------------------
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//---------------------------------------------------
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// Interrupt Block
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//---------------------------------------------------
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//-------------------------------------
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// IFQ
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//-------------------------------------
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// valid bit plus ifill
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//`ifdef SPARC_L2_64B
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//`else
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//`define BANK_ID_HI 8
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//`define BANK_ID_LO 7
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//`endif
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//`define CPX_INV_PA_HI 116
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//`define CPX_INV_PA_LO 112
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//----------------------------------------
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// IFU Traps
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//----------------------------------------
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// precise
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// disrupting
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module sparc_ifu_thrfsm(/*AUTOARG*/
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module sparc_ifu_thrfsm(/*AUTOARG*/
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// Outputs
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// Outputs
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so, thr_state,
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so, thr_state,
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// Inputs
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// Inputs
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| Line 252... |
Line 78... |
or rst_thread or schedule or spec_ld or stall
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or rst_thread or schedule or spec_ld or stall
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or start_thread or sw_cond or switch_out or thaw_thread
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or start_thread or sw_cond or switch_out or thaw_thread
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or thr_state)
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or thr_state)
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begin
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begin
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case (thr_state[4:0])
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case (thr_state[4:0])
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5'b00000: // 5'b00000
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`THRFSM_IDLE: // 5'b00000
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begin
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begin
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if (rst_thread | thaw_thread)
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if (rst_thread | thaw_thread)
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next_state = 5'b00001;
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next_state = `THRFSM_WAIT;
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else if (start_thread)
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else if (start_thread)
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next_state = 5'b11001;
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next_state = `THRFSM_RDY;
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else // all other interrupts ignored
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else // all other interrupts ignored
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next_state = thr_state[4:0];
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next_state = thr_state[4:0];
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end
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end
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5'b00010: // 5'b00010
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`THRFSM_HALT: // 5'b00010
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begin
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begin
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if (nuke_thread)
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if (nuke_thread)
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next_state = 5'b00000;
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next_state = `THRFSM_IDLE;
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else if (rst_thread | thaw_thread)
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else if (rst_thread | thaw_thread)
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next_state = 5'b00001;
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next_state = `THRFSM_WAIT;
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else if (int_activate | start_thread)
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else if (int_activate | start_thread)
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next_state = 5'b11001;
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next_state = `THRFSM_RDY;
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else
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else
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next_state = thr_state[4:0];
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next_state = thr_state[4:0];
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end
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end
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5'b11001: // 5'b11001
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`THRFSM_RDY: // 5'b11001
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begin
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begin
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if (stall)
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if (stall)
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// trap also kills inst_s2 and nir
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// trap also kills inst_s2 and nir
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// Ldmiss should not happen in this state
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// Ldmiss should not happen in this state
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next_state = 5'b00001;
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next_state = `THRFSM_WAIT;
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else if (schedule)
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else if (schedule)
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next_state = 5'b00101;
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next_state = `THRFSM_RUN;
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else
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else
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next_state = thr_state[4:0];
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next_state = thr_state[4:0];
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end // case: `THRFSM_RDY
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end // case: `THRFSM_RDY
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5'b00101: // 5'b00101
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`THRFSM_RUN: // 5'b00101
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begin
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begin
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if (stall | sw_cond)
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if (stall | sw_cond)
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// trap also kills inst_s2 and nir
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// trap also kills inst_s2 and nir
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// ldmiss should not happen in this state
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// ldmiss should not happen in this state
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next_state = 5'b00001;
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next_state = `THRFSM_WAIT;
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else if (switch_out)
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else if (switch_out)
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// on an interrupt or thread stall, the fcl has to
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// on an interrupt or thread stall, the fcl has to
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// switch out the thread and inform the fsm
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// switch out the thread and inform the fsm
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next_state = 5'b11001;
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next_state = `THRFSM_RDY;
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else
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else
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next_state = thr_state[4:0];
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next_state = thr_state[4:0];
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end // case: `THRFSM_RUN
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end // case: `THRFSM_RUN
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5'b00001: // 5'b00001
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`THRFSM_WAIT: // 5'b00001
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begin
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begin
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if (nuke_thread)
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if (nuke_thread)
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next_state = 5'b00000;
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next_state = `THRFSM_IDLE;
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else if (halt_thread) // exclusive with above
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else if (halt_thread) // exclusive with above
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next_state = 5'b00010;
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next_state = `THRFSM_HALT;
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else if (stall) // excl. with above
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else if (stall) // excl. with above
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next_state = 5'b00001;
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next_state = `THRFSM_WAIT;
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else if (spec_ld) // exclusive with above
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else if (spec_ld) // exclusive with above
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next_state = 5'b10011;
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next_state = `THRFSM_SPEC_RDY;
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else if (completion & ~halt_thread)
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else if (completion & ~halt_thread)
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next_state = 5'b11001;
|
next_state = `THRFSM_RDY;
|
else
|
else
|
next_state = thr_state[4:0];
|
next_state = thr_state[4:0];
|
end // case: `THRFSM_WAIT
|
end // case: `THRFSM_WAIT
|
|
|
5'b10011: // 5'b10011
|
`THRFSM_SPEC_RDY: // 5'b10011
|
begin
|
begin
|
if (stall)
|
if (stall)
|
next_state = 5'b00001;
|
next_state = `THRFSM_WAIT;
|
else if (schedule & ~ldhit) // exclusive
|
else if (schedule & ~ldhit) // exclusive
|
next_state = 5'b00111;
|
next_state = `THRFSM_SPEC_RUN;
|
else if (schedule & ldhit) // exclusive
|
else if (schedule & ldhit) // exclusive
|
next_state = 5'b00101;
|
next_state = `THRFSM_RUN;
|
else if (ldhit)
|
else if (ldhit)
|
next_state = 5'b11001;
|
next_state = `THRFSM_RDY;
|
else
|
else
|
next_state = thr_state[4:0];
|
next_state = thr_state[4:0];
|
end // case: `THRFSM_SPEC_RDY
|
end // case: `THRFSM_SPEC_RDY
|
|
|
5'b00111: // 5'b00111
|
`THRFSM_SPEC_RUN: // 5'b00111
|
begin
|
begin
|
if (stall | sw_cond)
|
if (stall | sw_cond)
|
next_state = 5'b00001;
|
next_state = `THRFSM_WAIT;
|
else if ((ldhit) & switch_out)
|
else if ((ldhit) & switch_out)
|
next_state = 5'b11001;
|
next_state = `THRFSM_RDY;
|
else if ((ldhit) & ~switch_out)
|
else if ((ldhit) & ~switch_out)
|
next_state = 5'b00101;
|
next_state = `THRFSM_RUN;
|
else if (~(ldhit) & switch_out)
|
else if (~(ldhit) & switch_out)
|
next_state = 5'b10011;
|
next_state = `THRFSM_SPEC_RDY;
|
// on an interrupt or thread stall, the fcl has to
|
// on an interrupt or thread stall, the fcl has to
|
// switch out the thread and inform the fsm
|
// switch out the thread and inform the fsm
|
else
|
else
|
next_state = thr_state[4:0];
|
next_state = thr_state[4:0];
|
end // case: `THRFSM_SPEC_RUN
|
end // case: `THRFSM_SPEC_RUN
|
| Line 351... |
Line 177... |
//VCS coverage off
|
//VCS coverage off
|
default:
|
default:
|
begin
|
begin
|
// synopsys translate_off
|
// synopsys translate_off
|
// 0in <fire -message "thrfsm.v: Error! Invalid State"
|
// 0in <fire -message "thrfsm.v: Error! Invalid State"
|
|
`ifdef DEFINE_0IN
|
|
`else
|
|
`ifdef MODELSIM
|
|
$display("ILLEGAL_THR_STATE", "thrfsm.v: Error! Invalid State %b\n", thr_state);
|
|
`else
|
//$display("ILLEGAL_THR_STATE", "thrfsm.v: Error! Invalid State %b\n", thr_state);
|
$error("ILLEGAL_THR_STATE", "thrfsm.v: Error! Invalid State %b\n", thr_state);
|
|
`endif
|
|
`endif
|
// synopsys translate_on
|
// synopsys translate_on
|
if (rst_thread)
|
if (rst_thread)
|
next_state = 5'b00001;
|
next_state = `THRFSM_WAIT;
|
else if (nuke_thread)
|
else if (nuke_thread)
|
next_state = 5'b00000;
|
next_state = `THRFSM_IDLE;
|
else
|
else
|
next_state = thr_state[4:0];
|
next_state = thr_state[4:0];
|
end
|
end
|
//VCS coverage on
|
//VCS coverage on
|
endcase // casex({thr_state[4:0]})
|
endcase // casex({thr_state[4:0]})
|
end // always @ (...
|
end // always @ (...
|
|
|
// thread config register (tcr)
|
// thread config register (tcr)
|
dffr #(5) tcr(.din (next_state),
|
dffr_s #(5) tcr(.din (next_state),
|
.clk (clk),
|
.clk (clk),
|
.q (thr_state),
|
.q (thr_state),
|
.rst (reset),
|
.rst (reset),
|
.se (se), .so(), .si());
|
.se (se), .so(), `SIMPLY_RISC_SCANIN);
|
|
|
|
|
endmodule
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
