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[/] [s1_core/] [trunk/] [hdl/] [rtl/] [sparc_core/] [sparc_tlu_intctl.v] - Diff between revs 105 and 113

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Rev 105 Rev 113
Line 16... Line 16... 
// You should have received a copy of the GNU General Public
 
// You should have received a copy of the GNU General Public
 
// License along with this work; if not, write to the Free Software
 
// License along with this work; if not, write to the Free Software
 
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
 
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
 
// 
// 
// ========== Copyright Header End ============================================
 
// ========== Copyright Header End ============================================
 
 
 
`ifdef SIMPLY_RISC_TWEAKS
 
 
 
`define SIMPLY_RISC_SCANIN .si(0)
 
 
 
`else
 
 
 
`define SIMPLY_RISC_SCANIN .si()
 
 
 
`endif
 
////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////
 
/*
 
/*
 
//  Module Name: sparc_tlu_intctl
 
//  Module Name: sparc_tlu_intctl
 
//  Description:
 
//  Description:
 
//    Contains the code for receiving interrupts from the crossbar,
 
//    Contains the code for receiving interrupts from the crossbar,
Line 30... Line 35... 
//    block.  This block also initiates thread reset/wake up when a
 
//    block.  This block also initiates thread reset/wake up when a
 
//    reset packet is received.
 
//    reset packet is received.
 
//
 
//
 
*/
 
*/
 
 
 
 
 
/*
 
`include "iop.h"
 
/* ========== Copyright Header Begin ==========================================
 
 
 
*
 
 
 
* OpenSPARC T1 Processor File: iop.h
 
 
 
* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
 
 
 
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
 
 
 
*
 
 
 
* The above named program is free software; you can redistribute it and/or
 
 
 
* modify it under the terms of the GNU General Public
 
 
 
* License version 2 as published by the Free Software Foundation.
 
 
 
*
 
 
 
* The above named program is distributed in the hope that it will be
 
 
 
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
 
 
 
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 
 
 
* General Public License for more details.
 
 
 
*
 
 
 
* You should have received a copy of the GNU General Public
 
 
 
* License along with this work; if not, write to the Free Software
 
 
 
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
 
 
 
*
 
 
 
* ========== Copyright Header End ============================================
 
 
 
*/
 
 
 
//-*- verilog -*-
 
 
 
////////////////////////////////////////////////////////////////////////
 
 
 
/*
 
 
 
//
 
 
 
//  Description:        Global header file that contain definitions that
 
 
 
//                      are common/shared at the IOP chip level
 
 
 
*/
 
 
 
////////////////////////////////////////////////////////////////////////
 
 
 
 
 
 
 
 
 
 
 
// Address Map Defines
 
 
 
// ===================
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// CMP space
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// IOP space
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
                               //`define ENET_ING_CSR     8'h84
 
 
 
                               //`define ENET_EGR_CMD_CSR 8'h85
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// L2 space
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// More IOP space
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//Cache Crossbar Width and Field Defines
 
 
 
//======================================
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//bits 133:128 are shared by different fields
 
 
 
//for different packet types.
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//End cache crossbar defines
 
 
 
 
 
 
 
 
 
 
 
// Number of COS supported by EECU 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// 
 
 
// BSC bus sizes
 
 
 
// =============
 
 
 
//
 
 
 
 
 
 
 
// General
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// CTags
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// reinstated temporarily
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// CoS
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// L2$ Bank
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// L2$ Req
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// L2$ Ack
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Enet Egress Command Unit
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Enet Egress Packet Unit
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// This is cleaved in between Egress Datapath Ack's
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Enet Egress Datapath
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// In-Order / Ordered Queue: EEPU
 
 
 
// Tag is: TLEN, SOF, EOF, QID = 15
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Nack + Tag Info + CTag
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// ENET Ingress Queue Management Req
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// ENET Ingress Queue Management Ack
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Enet Ingress Packet Unit
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// ENET Ingress Packet Unit Ack
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// In-Order / Ordered Queue: PCI
 
 
 
// Tag is: CTAG
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// PCI-X Request
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// PCI_X Acknowledge
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// BSC array sizes
 
 
 
//================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// ECC syndrome bits per memory element
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// BSC Port Definitions
 
 
 
// ====================
 
 
 
//
 
 
 
// Bits 7 to 4 of curr_port_id
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Number of ports of each type
 
 
 
 
 
 
 
 
 
 
 
// Bits needed to represent above
 
 
 
 
 
 
 
 
 
 
 
// How wide the linked list pointers are
 
 
 
// 60b for no payload (2CoS)
 
 
 
// 80b for payload (2CoS)
 
 
 
 
 
 
 
//`define BSC_OBJ_PTR   80
 
 
 
//`define BSC_HD1_HI    69
 
 
 
//`define BSC_HD1_LO    60
 
 
 
//`define BSC_TL1_HI    59
 
 
 
//`define BSC_TL1_LO    50
 
 
 
//`define BSC_CT1_HI    49
 
 
 
//`define BSC_CT1_LO    40
 
 
 
//`define BSC_HD0_HI    29
 
 
 
//`define BSC_HD0_LO    20
 
 
 
//`define BSC_TL0_HI    19
 
 
 
//`define BSC_TL0_LO    10
 
 
 
//`define BSC_CT0_HI     9
 
 
 
//`define BSC_CT0_LO     0
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// I2C STATES in DRAMctl
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// IOB defines
 
 
 
// ===========
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//`define IOB_INT_STAT_WIDTH   32
 
 
 
//`define IOB_INT_STAT_HI      31
 
 
 
//`define IOB_INT_STAT_LO       0
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// fixme - double check address mapping
 
 
 
// CREG in `IOB_INT_CSR space
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// CREG in `IOB_MAN_CSR space
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Address map for TAP access of SPARC ASI
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// CIOP UCB Bus Width
 
 
 
// ==================
 
 
 
//
 
 
 
//`define IOB_EECU_WIDTH       16  // ethernet egress command
 
 
 
//`define EECU_IOB_WIDTH       16
 
 
 
 
 
 
 
//`define IOB_NRAM_WIDTH       16  // NRAM (RLDRAM previously)
 
 
 
//`define NRAM_IOB_WIDTH        4
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//`define IOB_ENET_ING_WIDTH   32  // ethernet ingress
 
 
 
//`define ENET_ING_IOB_WIDTH    8
 
 
 
 
 
 
 
//`define IOB_ENET_EGR_WIDTH    4  // ethernet egress
 
 
 
//`define ENET_EGR_IOB_WIDTH    4
 
 
 
 
 
 
 
//`define IOB_ENET_MAC_WIDTH    4  // ethernet MAC
 
 
 
//`define ENET_MAC_IOB_WIDTH    4
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//`define IOB_BSC_WIDTH         4  // BSC
 
 
 
//`define BSC_IOB_WIDTH         4
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//`define IOB_CLSP_WIDTH        4  // clk spine unit
 
 
 
//`define CLSP_IOB_WIDTH        4
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// CIOP UCB Buf ID Type
 
 
 
// ====================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// Interrupt Device ID
 
 
 
// ===================
 
 
 
//
 
 
 
// Caution: DUMMY_DEV_ID has to be 9 bit wide
 
 
 
//          for fields to line up properly in the IOB.
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// Soft Error related definitions 
 
 
// ==============================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// CMP clock
 
 
 
// =========
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// NRAM/IO Interface
 
 
 
// =================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// NRAM/ENET Interface
 
 
 
// ===================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// IO/FCRAM Interface
 
 
 
// ==================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// PCI Interface
 
 
 
// ==================
 
 
 
// Load/store size encodings
 
 
 
// -------------------------
 
 
 
// Size encoding
 
 
 
// 000 - byte
 
 
 
// 001 - half-word
 
 
 
// 010 - word
 
 
 
// 011 - double-word
 
 
 
// 100 - quad
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// JBI<->SCTAG Interface
 
 
 
// =======================
 
 
 
// Outbound Header Format
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Inbound Header Format
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// JBI->IOB Mondo Header Format
 
 
 
// ============================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// JBI->IOB Mondo Bus Width/Cycle
 
 
 
// ==============================
 
 
 
// Cycle  1 Header[15:8]
 
 
 
// Cycle  2 Header[ 7:0]
 
 
 
// Cycle  3 J_AD[127:120]
 
 
 
// Cycle  4 J_AD[119:112]
 
 
 
// .....
 
 
 
// Cycle 18 J_AD[  7:  0]
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// from intdp.v for now
 
 
 
 
 
 
 
 
 
 
 
////////////////////////////////////////////////////////////////////////
 
 
 
// Local header file includes / local defines
 
 
 
////////////////////////////////////////////////////////////////////////
 
 
 
/*
 
 
 
/* ========== Copyright Header Begin ==========================================
 
 
 
*
 
 
 
* OpenSPARC T1 Processor File: tlu.h
 
 
 
* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
 
 
 
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
 
 
 
*
 
 
 
* The above named program is free software; you can redistribute it and/or
 
 
 
* modify it under the terms of the GNU General Public
 
 
 
* License version 2 as published by the Free Software Foundation.
 
 
 
*
 
 
 
* The above named program is distributed in the hope that it will be
 
 
 
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
 
 
 
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 
 
 
* General Public License for more details.
 
 
 
*
 
 
 
* You should have received a copy of the GNU General Public
 
 
 
* License along with this work; if not, write to the Free Software
 
 
 
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
 
 
 
*
 
 
 
* ========== Copyright Header End ============================================
 
 
 
*/
 
 
 
// ifu trap types
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// modified for hypervisor support
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
// modified due to bug 2588
 
 
 
// `define      TSA_PSTATE_VRANGE2_LO 16 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
// from intdp.v for now
 
// added due to Niagara SRAMs methodology
 
`define INT_THR_HI  12
 
// The following defines have been replaced due
 
 
 
// the memory macro replacement from:
 
 
 
// bw_r_rf32x144 -> 2x bw_r_rf32x80
 
 
 
/*
 
 
 
`define TSA_MEM_WIDTH     144
 
 
 
`define TSA_HTSTATE_HI    142 //  3 bits
 
 
 
`define TSA_HTSTATE_LO    140
 
 
 
`define TSA_TPC_HI        138 // 47 bits
 
 
 
`define TSA_TPC_LO         92
 
 
 
`define TSA_TNPC_HI        90 // 47 bits
 
 
 
`define TSA_TNPC_LO        44
 
 
 
`define TSA_TSTATE_HI      40 // 29 bits
 
 
 
`define TSA_TSTATE_LO      12
 
 
 
`define TSA_TTYPE_HI        8 //  9 bits
 
 
 
`define TSA_TTYPE_LO        0
 
 
 
`define TSA_MEM_CWP_LO     12
 
 
 
`define TSA_MEM_CWP_HI     14
 
 
 
`define TSA_MEM_PSTATE_LO  15
 
 
 
`define TSA_MEM_PSTATE_HI  22
 
 
 
`define TSA_MEM_ASI_LO     23
 
 
 
`define TSA_MEM_ASI_HI     30
 
 
 
`define TSA_MEM_CCR_LO     31
 
 
 
`define TSA_MEM_CCR_HI     38
 
 
 
`define TSA_MEM_GL_LO      39
 
 
 
`define TSA_MEM_GL_HI      40
 
 
 
*/
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// HPSTATE position definitions within wsr
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// TSTATE postition definitions within wsr
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// modified due to bug 2588
 
 
 
 
 
 
 
 
 
 
 
// added for bug 2584 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// tick_cmp and stick_cmp definitions
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// PIB WRAP
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// HPSTATE postition definitions
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// HTBA definitions
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// TBA definitions
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// added for the hypervisor support
 
 
 
 
 
 
 
 
 
 
 
// modified due to bug 2588
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// compressed PSTATE WSR definitions
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// ASI_QUEUE for hypervisor
 
 
 
// Queues are: CPU_MONODO
 
 
 
//             DEV_MONODO
 
 
 
//             RESUMABLE_ERROR
 
 
 
//             NON_RESUMABLE_ERROR
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// for address range checking
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// Niagara scratch-pads
 
 
 
// VA address of 0x20 and 0x28 are exclusive to hypervisor
 
 
 
// 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// range checking 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// PIB related definitions
 
 
 
// Bit definition for events
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// 
 
 
// PIB related definitions
 
 
 
// PCR and PIC address definitions
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// 
 
 
// PCR bit definitions
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// PIC definitions
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// PIC  mask bit position definitions
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// added define from sparc_tlu_int.v 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// shadow scan related definitions 
 
 
 
 
 
 
// modified due to logic redistribution
 
 
 
// `define TCL_SSCAN_WIDTH 12 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// `define TCL_SSCAN_LO 51 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// 
 
 
// position definitions - TDP
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// 
 
 
// position definitions - TCL
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// 
 
 
// To speedup POR for verification purposes
 
 
 
 
 
 
 
 
 
////////////////////////////////////////////////////////////////////////
 
 
 
// Local header file includes / local defines
 
 
 
////////////////////////////////////////////////////////////////////////
 
 
 
`include "tlu.h"
 
 
 
 
 
module sparc_tlu_intctl(/*AUTOARG*/
 
module sparc_tlu_intctl(/*AUTOARG*/
 
   // Outputs
 
   // Outputs
 
   so, int_rst_l, tlu_ifu_hwint_i3, tlu_ifu_rstthr_i2, tlu_ifu_rstint_i2,
 
   so, int_rst_l, tlu_ifu_hwint_i3, tlu_ifu_rstthr_i2, tlu_ifu_rstint_i2,
 
   tlu_ifu_nukeint_i2, tlu_ifu_resumint_i2, tlu_ifu_pstate_ie,
 
   tlu_ifu_nukeint_i2, tlu_ifu_resumint_i2, tlu_ifu_pstate_ie,
Line 1441... Line 210... 
       .din  (grst_l),
 
       .din  (grst_l),
 
       .clk  (clk),
 
       .clk  (clk),
 
       .rst_l(arst_l),
 
       .rst_l(arst_l),
 
       .q    (local_rst_l),
 
       .q    (local_rst_l),
 
       .se   (se),
 
       .se   (se),
 
       .si   (),
 
       `SIMPLY_RISC_SCANIN,
 
       .so   ()
 
       .so   ()
 
   );
 
   );
 
   assign local_rst = ~local_rst_l;
 
   assign local_rst = ~local_rst_l;
 
   assign int_rst_l = local_rst_l;
 
   assign int_rst_l = local_rst_l;
 
 
 
 
Line 1463... Line 232... 
   // int = 00
 
   // int = 00
 
   // the flush bit from cpx packet is now included in the
 
   // the flush bit from cpx packet is now included in the
 
   // lsu_tlu_cpx_vld qualification
 
   // lsu_tlu_cpx_vld qualification
 
   assign  hw_int_i1 = (lsu_tlu_cpx_vld &
 
   assign  hw_int_i1 = (lsu_tlu_cpx_vld &
 
                        // (lsu_tlu_cpx_req == `INT_RET) & ~lsu_tlu_cpx_nc &
 
                        // (lsu_tlu_cpx_req == `INT_RET) & ~lsu_tlu_cpx_nc &
 
                        (lsu_tlu_cpx_req == 4'b0111) &
 
                        (lsu_tlu_cpx_req == `INT_RET) &
 
                        (ind_inc_thrid_i1[4:2] == const_cpuid[2:0])) ?
 
                        (ind_inc_thrid_i1[4:2] == const_cpuid[2:0])) ?
 
                         ~ind_inc_type_i1[1] & ~ind_inc_type_i1[0] :
 
                         ~ind_inc_type_i1[1] & ~ind_inc_type_i1[0] :
 
                         1'b0;
 
                         1'b0;
 
   //reset = 01
 
   //reset = 01
 
   // the flush bit from cpx packet is now included in the
 
   // the flush bit from cpx packet is now included in the
 
   // lsu_tlu_cpx_vld qualification
 
   // lsu_tlu_cpx_vld qualification
 
   assign  rst_int_i1 = (lsu_tlu_cpx_vld &
 
   assign  rst_int_i1 = (lsu_tlu_cpx_vld &
 
                         // (lsu_tlu_cpx_req == `INT_RET) && ~lsu_tlu_cpx_nc &
 
                         // (lsu_tlu_cpx_req == `INT_RET) && ~lsu_tlu_cpx_nc &
 
                         (lsu_tlu_cpx_req == 4'b0111) &
 
                         (lsu_tlu_cpx_req == `INT_RET) &
 
                         (ind_inc_thrid_i1[4:2] == const_cpuid[2:0])) ?
 
                         (ind_inc_thrid_i1[4:2] == const_cpuid[2:0])) ?
 
                          ~ind_inc_type_i1[1] & ind_inc_type_i1[0] :
 
                          ~ind_inc_type_i1[1] & ind_inc_type_i1[0] :
 
                          1'b0;
 
                          1'b0;
 
   // idle/nuke = 10
 
   // idle/nuke = 10
 
   // the flush bit from cpx packet is now included in the
 
   // the flush bit from cpx packet is now included in the
 
   // lsu_tlu_cpx_vld qualification
 
   // lsu_tlu_cpx_vld qualification
 
   assign  nuke_int_i1 = (lsu_tlu_cpx_vld &
 
   assign  nuke_int_i1 = (lsu_tlu_cpx_vld &
 
                           // (lsu_tlu_cpx_req == `INT_RET) & ~lsu_tlu_cpx_nc &
 
                           // (lsu_tlu_cpx_req == `INT_RET) & ~lsu_tlu_cpx_nc &
 
                           (lsu_tlu_cpx_req == 4'b0111) &
 
                           (lsu_tlu_cpx_req == `INT_RET) &
 
                           (ind_inc_thrid_i1[4:2] == const_cpuid[2:0])) ?
 
                           (ind_inc_thrid_i1[4:2] == const_cpuid[2:0])) ?
 
                            ind_inc_type_i1[1] & ~ind_inc_type_i1[0] :
 
                            ind_inc_type_i1[1] & ~ind_inc_type_i1[0] :
 
                            1'b0;
 
                            1'b0;
 
   // resume = 11
 
   // resume = 11
 
   // the flush bit from cpx packet is now included in the
 
   // the flush bit from cpx packet is now included in the
 
   // lsu_tlu_cpx_vld qualification
 
   // lsu_tlu_cpx_vld qualification
 
   assign  resum_int_i1 = (lsu_tlu_cpx_vld &
 
   assign  resum_int_i1 = (lsu_tlu_cpx_vld &
 
                           // (lsu_tlu_cpx_req == `INT_RET) & ~lsu_tlu_cpx_nc &
 
                           // (lsu_tlu_cpx_req == `INT_RET) & ~lsu_tlu_cpx_nc &
 
                           (lsu_tlu_cpx_req == 4'b0111) &
 
                           (lsu_tlu_cpx_req == `INT_RET) &
 
                           (ind_inc_thrid_i1[4:2] == const_cpuid[2:0])) ?
 
                           (ind_inc_thrid_i1[4:2] == const_cpuid[2:0])) ?
 
                            ind_inc_type_i1[1] & ind_inc_type_i1[0] :
 
                            ind_inc_type_i1[1] & ind_inc_type_i1[0] :
 
                            1'b0;
 
                            1'b0;
 
 
 
 
 
   dffr #1  rstint_ff(.din  (rst_int_i1),
 
   dffr_s #1  rstint_ff(.din  (rst_int_i1),
 
                      .q    (tlu_ifu_rstint_i2),
 
                      .q    (tlu_ifu_rstint_i2),
 
                      .clk  (clk),
 
                      .clk  (clk),
 
//
 
//
 
// modified to abide to the Niagara reset methodology 
// modified to abide to the Niagara reset methodology 
//                    .rst  (reset),
 
//                    .rst  (reset),
 
                      .rst  (local_rst),
 
                      .rst  (local_rst),
 
                      .se   (se), .si(), .so());
 
                      .se   (se), `SIMPLY_RISC_SCANIN, .so());
 
 
 
 
 
   dffr #1  nukint_ff(.din  (nuke_int_i1),
 
   dffr_s #1  nukint_ff(.din  (nuke_int_i1),
 
                      .q    (tlu_ifu_nukeint_i2),
 
                      .q    (tlu_ifu_nukeint_i2),
 
                      .clk  (clk),
 
                      .clk  (clk),
 
//
 
//
 
// modified to abide to the Niagara reset methodology 
// modified to abide to the Niagara reset methodology 
//                    .rst  (reset),
 
//                    .rst  (reset),
 
                      .rst  (local_rst),
 
                      .rst  (local_rst),
 
                      .se   (se), .si(), .so());
 
                      .se   (se), `SIMPLY_RISC_SCANIN, .so());
 
 
 
 
 
   dffr #1  resint_ff(.din  (resum_int_i1),
 
   dffr_s #1  resint_ff(.din  (resum_int_i1),
 
                      .q    (tlu_ifu_resumint_i2),
 
                      .q    (tlu_ifu_resumint_i2),
 
                      .clk  (clk),
 
                      .clk  (clk),
 
//
 
//
 
// modified to abide to the Niagara reset methodology 
// modified to abide to the Niagara reset methodology 
//                    .rst  (reset),
 
//                    .rst  (reset),
 
                      .rst  (local_rst),
 
                      .rst  (local_rst),
 
                      .se   (se), .si(), .so());
 
                      .se   (se), `SIMPLY_RISC_SCANIN, .so());
 
 
 
 
 
   // decode int thread id
 
   // decode int thread id
 
   assign  int_thr_i1[0] = ~ind_inc_thrid_i1[1] & ~ind_inc_thrid_i1[0];
 
   assign  int_thr_i1[0] = ~ind_inc_thrid_i1[1] & ~ind_inc_thrid_i1[0];
 
   assign  int_thr_i1[1] = ~ind_inc_thrid_i1[1] &  ind_inc_thrid_i1[0];
 
   assign  int_thr_i1[1] = ~ind_inc_thrid_i1[1] &  ind_inc_thrid_i1[0];
 
   assign  int_thr_i1[2] =  ind_inc_thrid_i1[1] & ~ind_inc_thrid_i1[0];
 
   assign  int_thr_i1[2] =  ind_inc_thrid_i1[1] & ~ind_inc_thrid_i1[0];
Line 1560... Line 329... 
 
 
 
 
   // removed IFU will derive the siganl locally
 
   // removed IFU will derive the siganl locally
 
   /*
 
   /*
 
   assign  int_activate_i2 = ~int_pending_i2_l | tlu_int_sftint_pend;
 
   assign  int_activate_i2 = ~int_pending_i2_l | tlu_int_sftint_pend;
 
   // send message to SWL to wake up thread if it is halted
 
   // send message to SWL to wake up thread if it is halted
 
   dff #4 act_signal_reg(.din (int_activate_i2[3:0]),
 
   dff_s #4 act_signal_reg(.din (int_activate_i2[3:0]),
 
                         .q   (tlu_ifu_int_activate_i3[3:0]),
 
                         .q   (tlu_ifu_int_activate_i3[3:0]),
 
                         .clk (clk),
 
                         .clk (clk),
 
                         .se  (se), .si(), .so());
 
                         .se  (se), `SIMPLY_RISC_SCANIN, .so());
 
   */
 
   */
 
 
 
 
 
   // ask IFU to schedule interrupt
 
   // ask IFU to schedule interrupt
 
   dff #4 int_signal_reg(.din (int_pending_i2[3:0]),
 
   dff_s #4 int_signal_reg(.din (int_pending_i2[3:0]),
 
                         .q   (tlu_ifu_hwint_i3[3:0]),
 
                         .q   (tlu_ifu_hwint_i3[3:0]),
 
                         .clk (clk),
 
                         .clk (clk),
 
                         .se  (se), .si(), .so());
 
                         .se  (se), `SIMPLY_RISC_SCANIN, .so());
 
 
 
 
 
   dff #4 rst_signal_reg(.din (rstthr_i1[3:0]),
 
   dff_s #4 rst_signal_reg(.din (rstthr_i1[3:0]),
 
                         .q   (tlu_ifu_rstthr_i2[3:0]),
 
                         .q   (tlu_ifu_rstthr_i2[3:0]),
 
                         .clk (clk),
 
                         .clk (clk),
 
                         .se  (se), .si(), .so());
 
                         .se  (se), `SIMPLY_RISC_SCANIN, .so());
 
 
 
 
 
 
 
 
 
   //----------------------------------
 
   //----------------------------------
 
   // ASI Registers
 
   // ASI Registers
 
   //----------------------------------
 
   //----------------------------------
Line 1662... Line 431... 
   // 
   // 
   assign int_tlu_asi_data_vld_g =
 
   assign int_tlu_asi_data_vld_g =
 
          ((asi_invr | inc_ind_asi_inrr) & asi_read) | tlu_ld_data_vld_g;
 
          ((asi_invr | inc_ind_asi_inrr) & asi_read) | tlu_ld_data_vld_g;
 
 
 
 
 
 
 
 
 
   dffr dffr_int_tlu_asi_data_vld_w2 (
 
   dffr_s dffr_int_tlu_asi_data_vld_w2 (
 
    .din (int_tlu_asi_data_vld_g),
 
    .din (int_tlu_asi_data_vld_g),
 
    .q   (int_tlu_asi_data_vld_w2),
 
    .q   (int_tlu_asi_data_vld_w2),
 
    .clk (clk),
 
    .clk (clk),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .se  (1'b0),
 
    .se  (1'b0),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
// modified for timing
 
// modified for timing
 
// assign tlu_lsu_int_ldxa_vld_w2 = 
// assign tlu_lsu_int_ldxa_vld_w2 =
Line 1688... Line 457... 
          ((asi_invr | inc_ind_asi_inrr) & asi_read &
 
          ((asi_invr | inc_ind_asi_inrr) & asi_read &
 
            ~tlu_va_all_zero_g) | tlu_va_ill_g;
 
            ~tlu_va_all_zero_g) | tlu_va_ill_g;
 
   */
 
   */
 
   assign int_ld_ill_va_g = tlu_va_ill_g;
 
   assign int_ld_ill_va_g = tlu_va_ill_g;
 
 
 
 
 
   dffr dffr_tlu_lsu_int_ld_ill_va_w2 (
 
   dffr_s dffr_tlu_lsu_int_ld_ill_va_w2 (
 
    .din (int_ld_ill_va_g),
 
    .din (int_ld_ill_va_g),
 
    // .q   (tlu_lsu_int_ld_ill_va_w2),
 
    // .q   (tlu_lsu_int_ld_ill_va_w2),
 
    .q   (int_ld_ill_va_w2),
 
    .q   (int_ld_ill_va_w2),
 
    .clk (clk),
 
    .clk (clk),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .se  (1'b0),
 
    .se  (1'b0),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
assign tlu_lsu_int_ld_ill_va_w2 = int_ld_ill_va_w2;
 
assign tlu_lsu_int_ld_ill_va_w2 = int_ld_ill_va_w2;
 
   // Write to INDR
 
   // Write to INDR
Line 1750... Line 519... 
 
 
 
 
   assign indr_vld_next[0] =
 
   assign indr_vld_next[0] =
 
              (asi_indr & asi_write & asi_thr[0]) |
 
              (asi_indr & asi_write & asi_thr[0]) |
 
              (indr_vld[0] & ~indr_rst[0]);
 
              (indr_vld[0] & ~indr_rst[0]);
 
 
 
 
 
   dff #4 indr_vld_reg(.din (indr_vld_next[3:0]),
 
   dff_s #4 indr_vld_reg(.din (indr_vld_next[3:0]),
 
                       .q   (indr_vld[3:0]),
 
                       .q   (indr_vld[3:0]),
 
                       .clk (clk),
 
                       .clk (clk),
 
                       .se  (se), .si(), .so());
 
                       .se  (se), `SIMPLY_RISC_SCANIN, .so());
 
   // 
   // 
   // modified for bug 3945
 
   // modified for bug 3945
 
   dffr dffr_indr_req_valid_disable(
 
   dffr_s dffr_indr_req_valid_disable(
 
       .din (|indr_vld[3:0]),
 
       .din (|indr_vld[3:0]),
 
           .q   (indr_req_valid_disable),
 
           .q   (indr_req_valid_disable),
 
           .clk (clk),
 
           .clk (clk),
 
           .rst  (local_rst | lsu_tlu_pcxpkt_ack),
 
           .rst  (local_rst | lsu_tlu_pcxpkt_ack),
 
           .se  (se),
 
           .se  (se),
 
       .si(),
 
       `SIMPLY_RISC_SCANIN,
 
       .so());
 
       .so());
 
 
 
 
 
   dffe #(4) dffe_indr_req_vec(
 
   dffe_s #(4) dffe_indr_req_vec(
 
       .din (indr_vld_next[3:0]),
 
       .din (indr_vld_next[3:0]),
 
           .q   (indr_req_vec[3:0]),
 
           .q   (indr_req_vec[3:0]),
 
       .en  (~indr_req_valid_disable),
 
       .en  (~indr_req_valid_disable),
 
           .clk (clk),
 
           .clk (clk),
 
           .se  (se),
 
           .se  (se),
 
       .si(),
 
       `SIMPLY_RISC_SCANIN,
 
       .so());
 
       .so());
 
 
 
 
 
   // Round robin scheduler for indr request to pcx
 
   // Round robin scheduler for indr request to pcx
 
   sparc_ifu_rndrob  indr_sched(
 
   sparc_ifu_rndrob  indr_sched(
 
       // .req_vec (indr_vld[3:0]),
 
       // .req_vec (indr_vld[3:0]),
Line 1803... Line 572... 
   assign  indr_rst[3:0] =
 
   assign  indr_rst[3:0] =
 
               {4{local_rst}} | (indr_grant[3:0] & {4{lsu_tlu_pcxpkt_ack}});
 
               {4{local_rst}} | (indr_grant[3:0] & {4{lsu_tlu_pcxpkt_ack}});
 
   assign  intd_done[3:0] =
 
   assign  intd_done[3:0] =
 
               (indr_grant[3:0] & indr_vld[3:0] & {4{lsu_tlu_pcxpkt_ack}});
 
               (indr_grant[3:0] & indr_vld[3:0] & {4{lsu_tlu_pcxpkt_ack}});
 
 
 
 
 
   dffr #(4) intd_reg(
 
   dffr_s #(4) intd_reg(
 
       .din (intd_done[3:0]),
 
       .din (intd_done[3:0]),
 
           .q   (int_tlu_longop_done[3:0]),
 
           .q   (int_tlu_longop_done[3:0]),
 
           .clk (clk),
 
           .clk (clk),
 
           .rst  (local_rst),
 
           .rst  (local_rst),
 
           .se  (se),
 
           .se  (se),
 
       .si(),
 
       `SIMPLY_RISC_SCANIN,
 
       .so());
 
       .so());
 
 
 
 
 
   // INDR pcx request control signals
 
   // INDR pcx request control signals
 
   // modified for bug 3945
 
   // modified for bug 3945
 
   // assign  inc_indr_req_valid = (|indr_vld[3:0]) & ~lsu_tlu_pcxpkt_ack;
 
   // assign  inc_indr_req_valid = (|indr_vld[3:0]) & ~lsu_tlu_pcxpkt_ack;

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