| Line 23... |
Line 23... |
//
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//
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// Module Name: swrvr_clib.v
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// Module Name: swrvr_clib.v
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// Description: Design control behavioural library
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// Description: Design control behavioural library
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*/
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*/
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`ifdef FPGA_SYN
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`define NO_SCAN
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`endif
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// POSITVE-EDGE TRIGGERED FLOP with SCAN
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// POSITVE-EDGE TRIGGERED FLOP with SCAN
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module dff (din, clk, q, se, si, so);
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module dff_s (din, clk, q, se, si, so);
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// synopsys template
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// synopsys template
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parameter SIZE = 1;
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parameter SIZE = 1;
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input [SIZE-1:0] din ; // data in
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input [SIZE-1:0] din ; // data in
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| Line 44... |
Line 44... |
input [SIZE-1:0] si ; // scan-input
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input [SIZE-1:0] si ; // scan-input
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output [SIZE-1:0] so ; // scan-output
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output [SIZE-1:0] so ; // scan-output
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reg [SIZE-1:0] q ;
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reg [SIZE-1:0] q ;
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`ifdef NO_SCAN
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always @ (posedge clk)
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always @ (posedge clk)
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q[SIZE-1:0] <= din[SIZE-1:0] ;
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q[SIZE-1:0] <= din[SIZE-1:0] ;
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`else
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always @ (posedge clk)
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q[SIZE-1:0] <= (se) ? si[SIZE-1:0] : din[SIZE-1:0] ;
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assign so[SIZE-1:0] = q[SIZE-1:0] ;
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`endif
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endmodule // dff_s
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`ifndef SIMPLY_RISC_TWEAKS
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endmodule // dff
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// POSITVE-EDGE TRIGGERED FLOP with SCAN for Shadow-scan
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// POSITVE-EDGE TRIGGERED FLOP with SCAN for Shadow-scan
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module dff_sscan (din, clk, q, se, si, so);
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module dff_sscan (din, clk, q, se, si, so);
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// synopsys template
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// synopsys template
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parameter SIZE = 1;
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parameter SIZE = 1;
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| Line 76... |
Line 77... |
input [SIZE-1:0] si ; // scan-input
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input [SIZE-1:0] si ; // scan-input
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output [SIZE-1:0] so ; // scan-output
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output [SIZE-1:0] so ; // scan-output
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reg [SIZE-1:0] q ;
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reg [SIZE-1:0] q ;
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`ifdef CONNECT_SHADOW_SCAN
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always @ (posedge clk)
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q[SIZE-1:0] <= (se) ? si[SIZE-1:0] : din[SIZE-1:0] ;
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assign so[SIZE-1:0] = q[SIZE-1:0] ;
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`else
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always @ (posedge clk)
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always @ (posedge clk)
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q[SIZE-1:0] <= din[SIZE-1:0] ;
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q[SIZE-1:0] <= din[SIZE-1:0] ;
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assign so={SIZE{1'b0}};
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assign so={SIZE{1'b0}};
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`endif
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endmodule // dff_sscan
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endmodule // dff
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`endif
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// POSITVE-EDGE TRIGGERED FLOP without SCAN
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// POSITVE-EDGE TRIGGERED FLOP without SCAN
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module dff_ns (din, clk, q);
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module dff_ns (din, clk, q);
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// synopsys template
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// synopsys template
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| Line 113... |
Line 115... |
q[SIZE-1:0] <= din[SIZE-1:0] ;
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q[SIZE-1:0] <= din[SIZE-1:0] ;
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endmodule // dff_ns
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endmodule // dff_ns
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// POSITIVE-EDGE TRIGGERED FLOP with SCAN, RESET
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// POSITIVE-EDGE TRIGGERED FLOP with SCAN, RESET
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module dffr (din, clk, rst, q, se, si, so);
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module dffr_s (din, clk, rst, q, se, si, so);
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// synopsys template
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// synopsys template
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parameter SIZE = 1;
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parameter SIZE = 1;
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input [SIZE-1:0] din ; // data in
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input [SIZE-1:0] din ; // data in
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| Line 130... |
Line 132... |
input [SIZE-1:0] si ; // scan-input
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input [SIZE-1:0] si ; // scan-input
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output [SIZE-1:0] so ; // scan-output
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output [SIZE-1:0] so ; // scan-output
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reg [SIZE-1:0] q ;
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reg [SIZE-1:0] q ;
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`ifdef NO_SCAN
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always @ (posedge clk)
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always @ (posedge clk)
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q[SIZE-1:0] <= ((rst) ? {SIZE{1'b0}} : din[SIZE-1:0] );
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q[SIZE-1:0] <= ((rst) ? {SIZE{1'b0}} : din[SIZE-1:0] );
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`else
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// Scan-Enable dominates
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always @ (posedge clk)
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q[SIZE-1:0] <= se ? si[SIZE-1:0] : ((rst) ? {SIZE{1'b0}} : din[SIZE-1:0] );
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assign so[SIZE-1:0] = q[SIZE-1:0] ;
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`endif
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endmodule // dffr_s
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`ifndef SIMPLY_RISC_TWEAKS
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endmodule // dffr
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// POSITIVE-EDGE TRIGGERED FLOP with SCAN, RESET_L
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// POSITIVE-EDGE TRIGGERED FLOP with SCAN, RESET_L
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module dffrl (din, clk, rst_l, q, se, si, so);
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module dffrl_s (din, clk, rst_l, q, se, si, so);
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// synopsys template
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// synopsys template
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parameter SIZE = 1;
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parameter SIZE = 1;
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input [SIZE-1:0] din ; // data in
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input [SIZE-1:0] din ; // data in
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| Line 163... |
Line 166... |
input [SIZE-1:0] si ; // scan-input
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input [SIZE-1:0] si ; // scan-input
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output [SIZE-1:0] so ; // scan-output
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output [SIZE-1:0] so ; // scan-output
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reg [SIZE-1:0] q ;
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reg [SIZE-1:0] q ;
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`ifdef NO_SCAN
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always @ (posedge clk)
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always @ (posedge clk)
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q[SIZE-1:0] <= rst_l ? din[SIZE-1:0] : {SIZE{1'b0}};
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q[SIZE-1:0] <= rst_l ? din[SIZE-1:0] : {SIZE{1'b0}};
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`else
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// Reset dominates
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always @ (posedge clk)
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q[SIZE-1:0] <= rst_l ? ((se) ? si[SIZE-1:0] : din[SIZE-1:0] ) : {SIZE{1'b0}};
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assign so[SIZE-1:0] = q[SIZE-1:0] ;
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`endif
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endmodule // dffrl_s
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endmodule // dffr_l
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// POSITIVE-EDGE TRIGGERED FLOP with RESET, without SCAN
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// POSITIVE-EDGE TRIGGERED FLOP with RESET, without SCAN
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module dffr_ns (din, clk, rst, q);
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module dffr_ns (din, clk, rst, q);
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// synopsys template
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// synopsys template
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parameter SIZE = 1;
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parameter SIZE = 1;
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| Line 197... |
Line 201... |
// synopsys sync_set_reset "rst"
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// synopsys sync_set_reset "rst"
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always @ (posedge clk)
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always @ (posedge clk)
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q[SIZE-1:0] <= rst ? {SIZE{1'b0}} : din[SIZE-1:0];
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q[SIZE-1:0] <= rst ? {SIZE{1'b0}} : din[SIZE-1:0];
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endmodule // dffr_ns
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endmodule // dffr_ns
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`endif
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// POSITIVE-EDGE TRIGGERED FLOP with RESET_L, without SCAN
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// POSITIVE-EDGE TRIGGERED FLOP with RESET_L, without SCAN
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module dffrl_ns (din, clk, rst_l, q);
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module dffrl_ns (din, clk, rst_l, q);
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// synopsys template
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// synopsys template
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| Line 219... |
Line 224... |
q[SIZE-1:0] <= rst_l ? din[SIZE-1:0] : {SIZE{1'b0}};
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q[SIZE-1:0] <= rst_l ? din[SIZE-1:0] : {SIZE{1'b0}};
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endmodule // dffrl_ns
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endmodule // dffrl_ns
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// POSITIVE-EDGE TRIGGERED FLOP with SCAN and FUNCTIONAL ENABLE
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// POSITIVE-EDGE TRIGGERED FLOP with SCAN and FUNCTIONAL ENABLE
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module dffe (din, en, clk, q, se, si, so);
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module dffe_s (din, en, clk, q, se, si, so);
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// synopsys template
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// synopsys template
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parameter SIZE = 1;
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parameter SIZE = 1;
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input [SIZE-1:0] din ; // data in
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input [SIZE-1:0] din ; // data in
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| Line 245... |
Line 250... |
// x 1 sin ; scan dominates
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// x 1 sin ; scan dominates
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// 1 0 din
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// 1 0 din
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// 0 0 q
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// 0 0 q
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//
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//
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`ifdef NO_SCAN
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always @ (posedge clk)
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always @ (posedge clk)
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q[SIZE-1:0] <= ((en) ? din[SIZE-1:0] : q[SIZE-1:0]) ;
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q[SIZE-1:0] <= ((en) ? din[SIZE-1:0] : q[SIZE-1:0]) ;
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`else
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always @ (posedge clk)
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q[SIZE-1:0] <= (se) ? si[SIZE-1:0] : ((en) ? din[SIZE-1:0] : q[SIZE-1:0]) ;
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assign so[SIZE-1:0] = q[SIZE-1:0] ;
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`endif
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endmodule // dffe_s
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`ifndef SIMPLY_RISC_TWEAKS
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endmodule // dffe
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// POSITIVE-EDGE TRIGGERED FLOP with enable, without SCAN
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// POSITIVE-EDGE TRIGGERED FLOP with enable, without SCAN
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module dffe_ns (din, en, clk, q);
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module dffe_ns (din, en, clk, q);
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// synopsys template
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// synopsys template
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parameter SIZE = 1;
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parameter SIZE = 1;
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| Line 277... |
Line 283... |
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always @ (posedge clk)
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always @ (posedge clk)
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q[SIZE-1:0] <= en ? din[SIZE-1:0] : q[SIZE-1:0];
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q[SIZE-1:0] <= en ? din[SIZE-1:0] : q[SIZE-1:0];
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endmodule // dffe_ns
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endmodule // dffe_ns
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`endif
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// POSITIVE-EDGE TRIGGERED FLOP with RESET, FUNCTIONAL ENABLE, SCAN.
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// POSITIVE-EDGE TRIGGERED FLOP with RESET, FUNCTIONAL ENABLE, SCAN.
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module dffre (din, rst, en, clk, q, se, si, so);
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module dffre_s (din, rst, en, clk, q, se, si, so);
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// synopsys template
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// synopsys template
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parameter SIZE = 1;
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parameter SIZE = 1;
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input [SIZE-1:0] din ; // data in
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input [SIZE-1:0] din ; // data in
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| Line 307... |
Line 314... |
// 0 x 1 sin ; scan dominates
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// 0 x 1 sin ; scan dominates
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// 0 1 0 din
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// 0 1 0 din
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// 0 0 0 q
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// 0 0 0 q
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//
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//
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`ifdef NO_SCAN
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always @ (posedge clk)
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always @ (posedge clk)
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q[SIZE-1:0] <= (rst ? {SIZE{1'b0}} : ((en) ? din[SIZE-1:0] : q[SIZE-1:0])) ;
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q[SIZE-1:0] <= (rst ? {SIZE{1'b0}} : ((en) ? din[SIZE-1:0] : q[SIZE-1:0])) ;
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`else
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always @ (posedge clk)
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// q[SIZE-1:0] <= rst ? {SIZE{1'b0}} : ((se) ? si[SIZE-1:0] : ((en) ? din[SIZE-1:0] : q[SIZE-1:0])) ;
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q[SIZE-1:0] <= se ? si[SIZE-1:0] : (rst ? {SIZE{1'b0}} : ((en) ? din[SIZE-1:0] : q[SIZE-1:0])) ;
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assign so[SIZE-1:0] = q[SIZE-1:0] ;
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`endif
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endmodule // dffre_s
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endmodule // dffre
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// POSITIVE-EDGE TRIGGERED FLOP with RESET_L, FUNCTIONAL ENABLE, SCAN.
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// POSITIVE-EDGE TRIGGERED FLOP with RESET_L, FUNCTIONAL ENABLE, SCAN.
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module dffrle (din, rst_l, en, clk, q, se, si, so);
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module dffrle_s (din, rst_l, en, clk, q, se, si, so);
|
// synopsys template
|
// synopsys template
|
|
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parameter SIZE = 1;
|
parameter SIZE = 1;
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|
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input [SIZE-1:0] din ; // data in
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input [SIZE-1:0] din ; // data in
|
| Line 352... |
Line 359... |
// 1 x 1 sin ; scan dominates
|
// 1 x 1 sin ; scan dominates
|
// 1 1 0 din
|
// 1 1 0 din
|
// 1 0 0 q
|
// 1 0 0 q
|
//
|
//
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|
|
|
`ifdef NO_SCAN
|
always @ (posedge clk)
|
always @ (posedge clk)
|
q[SIZE-1:0] <= (rst_l ? ((en) ? din[SIZE-1:0] : q[SIZE-1:0]) : {SIZE{1'b0}}) ;
|
q[SIZE-1:0] <= (rst_l ? ((en) ? din[SIZE-1:0] : q[SIZE-1:0]) : {SIZE{1'b0}}) ;
|
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`else
|
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|
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always @ (posedge clk)
|
|
|
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// q[SIZE-1:0] <= rst_l ? ((se) ? si[SIZE-1:0] : ((en) ? din[SIZE-1:0] : q[SIZE-1:0])) : {SIZE{1'b0}} ;
|
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q[SIZE-1:0] <= se ? si[SIZE-1:0] : (rst_l ? ((en) ? din[SIZE-1:0] : q[SIZE-1:0]) : {SIZE{1'b0}}) ;
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assign so[SIZE-1:0] = q[SIZE-1:0] ;
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`endif
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endmodule // dffrle_s
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`ifndef SIMPLY_RISC_TWEAKS
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endmodule // dffrle
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// POSITIVE-EDGE TRIGGERED FLOP with RESET, ENABLE, without SCAN.
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// POSITIVE-EDGE TRIGGERED FLOP with RESET, ENABLE, without SCAN.
|
module dffre_ns (din, rst, en, clk, q);
|
module dffre_ns (din, rst, en, clk, q);
|
// synopsys template
|
// synopsys template
|
|
|
parameter SIZE = 1;
|
parameter SIZE = 1;
|
| Line 396... |
Line 404... |
// synopsys sync_set_reset "rst"
|
// synopsys sync_set_reset "rst"
|
always @ (posedge clk)
|
always @ (posedge clk)
|
q[SIZE-1:0] <= rst ? {SIZE{1'b0}} : ((en) ? din[SIZE-1:0] : q[SIZE-1:0]);
|
q[SIZE-1:0] <= rst ? {SIZE{1'b0}} : ((en) ? din[SIZE-1:0] : q[SIZE-1:0]);
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endmodule // dffre_ns
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endmodule // dffre_ns
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`endif
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// POSITIVE-EDGE TRIGGERED FLOP with RESET_L, ENABLE, without SCAN.
|
// POSITIVE-EDGE TRIGGERED FLOP with RESET_L, ENABLE, without SCAN.
|
module dffrle_ns (din, rst_l, en, clk, q);
|
module dffrle_ns (din, rst_l, en, clk, q);
|
// synopsys template
|
// synopsys template
|
|
|
| Line 427... |
Line 436... |
always @ (posedge clk)
|
always @ (posedge clk)
|
q[SIZE-1:0] <= rst_l ? ((en) ? din[SIZE-1:0] : q[SIZE-1:0]) : {SIZE{1'b0}} ;
|
q[SIZE-1:0] <= rst_l ? ((en) ? din[SIZE-1:0] : q[SIZE-1:0]) : {SIZE{1'b0}} ;
|
|
|
endmodule // dffrle_ns
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endmodule // dffrle_ns
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|
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`ifndef SIMPLY_RISC_TWEAKS
|
// POSITIVE-EDGE TRIGGERED FLOP with SCAN, and ASYNC RESET
|
// POSITIVE-EDGE TRIGGERED FLOP with SCAN, and ASYNC RESET
|
module dffr_async (din, clk, rst, q, se, si, so);
|
module dffr_async (din, clk, rst, q, se, si, so);
|
// synopsys template
|
// synopsys template
|
|
|
parameter SIZE = 1;
|
parameter SIZE = 1;
|
| Line 445... |
Line 455... |
input [SIZE-1:0] si ; // scan-input
|
input [SIZE-1:0] si ; // scan-input
|
output [SIZE-1:0] so ; // scan-output
|
output [SIZE-1:0] so ; // scan-output
|
|
|
reg [SIZE-1:0] q ;
|
reg [SIZE-1:0] q ;
|
|
|
|
`ifdef NO_SCAN
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
q[SIZE-1:0] <= rst ? {SIZE{1'b0}} : din[SIZE-1:0];
|
q[SIZE-1:0] <= rst ? {SIZE{1'b0}} : din[SIZE-1:0];
|
|
`else
|
|
|
|
// Reset dominates
|
|
always @ (posedge clk or posedge rst)
|
|
q[SIZE-1:0] <= rst ? {SIZE{1'b0}} : ((se) ? si[SIZE-1:0] : din[SIZE-1:0] );
|
|
|
|
assign so[SIZE-1:0] = q[SIZE-1:0] ;
|
|
|
|
`endif
|
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|
|
endmodule // dffr_async
|
endmodule // dffr_async
|
|
`endif
|
|
|
// POSITIVE-EDGE TRIGGERED FLOP with SCAN, and ASYNC RESET_L
|
// POSITIVE-EDGE TRIGGERED FLOP with SCAN, and ASYNC RESET_L
|
module dffrl_async (din, clk, rst_l, q, se, si, so);
|
module dffrl_async (din, clk, rst_l, q, se, si, so);
|
// synopsys template
|
// synopsys template
|
|
|
| Line 478... |
Line 489... |
input [SIZE-1:0] si ; // scan-input
|
input [SIZE-1:0] si ; // scan-input
|
output [SIZE-1:0] so ; // scan-output
|
output [SIZE-1:0] so ; // scan-output
|
|
|
reg [SIZE-1:0] q ;
|
reg [SIZE-1:0] q ;
|
|
|
|
`ifdef NO_SCAN
|
always @ (posedge clk or negedge rst_l)
|
always @ (posedge clk or negedge rst_l)
|
q[SIZE-1:0] <= (!rst_l) ? {SIZE{1'b0}} : din[SIZE-1:0];
|
q[SIZE-1:0] <= (!rst_l) ? {SIZE{1'b0}} : din[SIZE-1:0];
|
|
`else
|
|
|
|
// Reset dominates
|
|
always @ (posedge clk or negedge rst_l)
|
|
q[SIZE-1:0] <= (!rst_l) ? {SIZE{1'b0}} : ((se) ? si[SIZE-1:0] : din[SIZE-1:0] );
|
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|
|
assign so[SIZE-1:0] = q[SIZE-1:0] ;
|
|
|
|
`endif
|
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|
|
|
|
|
|
endmodule // dffrl_async
|
endmodule // dffrl_async
|
|
|
// POSITIVE-EDGE TRIGGERED FLOP with ASYNC RESET, without SCAN
|
// POSITIVE-EDGE TRIGGERED FLOP with ASYNC RESET, without SCAN
|
//module dffr_async_ns (din, clk, rst, q);
|
//module dffr_async_ns (din, clk, rst, q);
|
| Line 509... |
Line 520... |
//always @ (posedge clk or posedge rst)
|
//always @ (posedge clk or posedge rst)
|
// if(rst) q[SIZE-1:0] <= {SIZE{1'b0}};
|
// if(rst) q[SIZE-1:0] <= {SIZE{1'b0}};
|
// else if(clk) q[SIZE-1:0] <= din[SIZE-1:0];
|
// else if(clk) q[SIZE-1:0] <= din[SIZE-1:0];
|
//endmodule // dffr_async_ns
|
//endmodule // dffr_async_ns
|
|
|
|
`ifndef SIMPLY_RISC_TWEAKS
|
// POSITIVE-EDGE TRIGGERED FLOP with ASYNC RESET_L, without SCAN
|
// POSITIVE-EDGE TRIGGERED FLOP with ASYNC RESET_L, without SCAN
|
module dffrl_async_ns (din, clk, rst_l, q);
|
module dffrl_async_ns (din, clk, rst_l, q);
|
// synopsys template
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// synopsys template
|
|
|
parameter SIZE = 1;
|
parameter SIZE = 1;
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| Line 545... |
Line 557... |
// qs <= clk ? qm_l : qs_f;
|
// qs <= clk ? qm_l : qs_f;
|
//
|
//
|
// assign q = ~qs;
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// assign q = ~qs;
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|
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endmodule // dffrl_async_ns
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endmodule // dffrl_async_ns
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`endif
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// 2:1 MUX WITH DECODED SELECTS
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// 2:1 MUX WITH DECODED SELECTS
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module mux2ds (dout, in0, in1, sel0, sel1) ;
|
module mux2ds (dout, in0, in1, sel0, sel1) ;
|
// synopsys template
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// synopsys template
|
|
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| Line 564... |
Line 577... |
// across cycles. Used to construct case statement and
|
// across cycles. Used to construct case statement and
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// always updated by inputs every cycle.
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// always updated by inputs every cycle.
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reg [SIZE-1:0] dout ;
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reg [SIZE-1:0] dout ;
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|
|
// priority encoding takes care of mutex'ing selects.
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// priority encoding takes care of mutex'ing selects.
|
|
`ifdef VERPLEX
|
|
$constraint cl_1h_chk2 ($one_hot ({sel1,sel0}));
|
|
`endif
|
|
|
wire [1:0] sel = {sel1, sel0}; // 0in one_hot
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wire [1:0] sel = {sel1, sel0}; // 0in one_hot
|
|
|
always @ (sel0 or sel1 or in0 or in1)
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always @ (sel0 or sel1 or in0 or in1)
|
|
|
| Line 584... |
Line 597... |
// `ifdef FOUR_STATE
|
// `ifdef FOUR_STATE
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// dout = {SIZE{1'bx}};
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// dout = {SIZE{1'bx}};
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// `else
|
// `else
|
// begin
|
// begin
|
// dout = {SIZE{1'b0}};
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// dout = {SIZE{1'b0}};
|
// $display();
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// $error();
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// end
|
// end
|
// `endif
|
// `endif
|
// end
|
// end
|
default : dout = {SIZE{1'bx}};
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default : dout = {SIZE{1'bx}};
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endcase
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endcase
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| Line 612... |
Line 625... |
// reg declaration does not imply state being maintained
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// reg declaration does not imply state being maintained
|
// across cycles. Used to construct case statement and
|
// across cycles. Used to construct case statement and
|
// always updated by inputs every cycle.
|
// always updated by inputs every cycle.
|
reg [SIZE-1:0] dout ;
|
reg [SIZE-1:0] dout ;
|
|
|
|
`ifdef VERPLEX
|
|
$constraint cl_1h_chk3 ($one_hot ({sel2,sel1,sel0}));
|
|
`endif
|
|
|
wire [2:0] sel = {sel2,sel1,sel0}; // 0in one_hot
|
wire [2:0] sel = {sel2,sel1,sel0}; // 0in one_hot
|
|
|
// priority encoding takes care of mutex'ing selects.
|
// priority encoding takes care of mutex'ing selects.
|
always @ (sel0 or sel1 or sel2 or in0 or in1 or in2)
|
always @ (sel0 or sel1 or sel2 or in0 or in1 or in2)
|
| Line 657... |
Line 670... |
// reg declaration does not imply state being maintained
|
// reg declaration does not imply state being maintained
|
// across cycles. Used to construct case statement and
|
// across cycles. Used to construct case statement and
|
// always updated by inputs every cycle.
|
// always updated by inputs every cycle.
|
reg [SIZE-1:0] dout ;
|
reg [SIZE-1:0] dout ;
|
|
|
|
`ifdef VERPLEX
|
|
$constraint cl_1h_chk4 ($one_hot ({sel3,sel2,sel1,sel0}));
|
|
`endif
|
|
|
wire [3:0] sel = {sel3,sel2,sel1,sel0}; // 0in one_hot
|
wire [3:0] sel = {sel3,sel2,sel1,sel0}; // 0in one_hot
|
|
|
// priority encoding takes care of mutex'ing selects.
|
// priority encoding takes care of mutex'ing selects.
|
always @ (sel0 or sel1 or sel2 or sel3 or in0 or in1 or in2 or in3)
|
always @ (sel0 or sel1 or sel2 or sel3 or in0 or in1 or in2 or in3)
|
| Line 697... |
Line 710... |
|
|
parameter SIZE = 1;
|
parameter SIZE = 1;
|
|
|
input [SIZE-1:0] in;
|
input [SIZE-1:0] in;
|
|
|
|
`ifdef FPGA_SYN
|
// As of version 8.2 XST does not remove this module without the
|
// As of version 8.2 XST does not remove this module without the
|
// following additional dead code
|
// following additional dead code
|
|
|
wire a;
|
wire a;
|
|
|
assign a = | in;
|
assign a = | in;
|
|
|
|
`endif
|
|
|
endmodule //sink
|
endmodule //sink
|
|
|
|
`ifndef SIMPLY_RISC_TWEAKS
|
// SOURCE FOR UNDRIVEN OUTPUT PORTS
|
// SOURCE FOR UNDRIVEN OUTPUT PORTS
|
module source (out) ;
|
module source (out) ;
|
// synopsys template
|
// synopsys template
|
|
|
parameter SIZE = 1;
|
parameter SIZE = 1;
|
| Line 727... |
Line 741... |
//`else
|
//`else
|
assign out = {SIZE{1'b0}};
|
assign out = {SIZE{1'b0}};
|
//`endif
|
//`endif
|
|
|
endmodule //source
|
endmodule //source
|
|
`endif
|
|
|
// 2:1 MUX WITH PRIORITY ENCODED SELECTS
|
// 2:1 MUX WITH PRIORITY ENCODED SELECTS
|
//module mux2es (dout, in0, in1, sel0, sel1) ;
|
//module mux2es (dout, in0, in1, sel0, sel1) ;
|
//
|
//
|
//parameter SIZE = 1;
|
//parameter SIZE = 1;
|
| Line 763... |
Line 778... |
// clk - output of the clk header
|
// clk - output of the clk header
|
// rclk - input clk
|
// rclk - input clk
|
// enb_l - Active low clock enable
|
// enb_l - Active low clock enable
|
// tmb_l - Active low clock enable ( in scan mode, this input is !se )
|
// tmb_l - Active low clock enable ( in scan mode, this input is !se )
|
|
|
|
`ifndef SIMPLY_RISC_TWEAKS
|
module clken_buf (clk, rclk, enb_l, tmb_l);
|
module clken_buf (clk, rclk, enb_l, tmb_l);
|
output clk;
|
output clk;
|
input rclk, enb_l, tmb_l;
|
input rclk, enb_l, tmb_l;
|
reg clken;
|
reg clken;
|
|
|
| Line 776... |
Line 792... |
assign clk = clken & rclk;
|
assign clk = clken & rclk;
|
|
|
endmodule
|
endmodule
|
|
|
|
|
|
|
// The following flops are maintained and used in ENET , MAC IP ONLY
|
// The following flops are maintained and used in ENET , MAC IP ONLY
|
// -- Mimi X61467
|
// -- Mimi X61467
|
|
|
// POSITIVE-EDGE TRIGGERED FLOP with SET_L, without SCAN.
|
// POSITIVE-EDGE TRIGGERED FLOP with SET_L, without SCAN.
|
|
|
module dffsl_ns (din, clk, set_l, q);
|
module dffsl_ns (din, clk, set_l, q);
|
// synopsys template
|
// synopsys template
|
parameter SIZE = 1;
|
parameter SIZE = 1;
|
|
|
input [SIZE-1:0] din ; // data in
|
input [SIZE-1:0] din ; // data in
|
| Line 800... |
Line 814... |
always @ (posedge clk)
|
always @ (posedge clk)
|
q[SIZE-1:0] <= set_l ? din[SIZE-1:0] : {SIZE{1'b1}};
|
q[SIZE-1:0] <= set_l ? din[SIZE-1:0] : {SIZE{1'b1}};
|
|
|
endmodule // dffsl_ns
|
endmodule // dffsl_ns
|
|
|
// POSITIVE-EDGE TRIGGERED FLOP with SET_L, without SCAN.
|
|
|
|
|
// POSITIVE-EDGE TRIGGERED FLOP with SET_L, without SCAN.
|
module dffsl_async_ns (din, clk, set_l, q);
|
module dffsl_async_ns (din, clk, set_l, q);
|
// synopsys template
|
// synopsys template
|
parameter SIZE = 1;
|
parameter SIZE = 1;
|
|
|
input [SIZE-1:0] din ; // data in
|
input [SIZE-1:0] din ; // data in
|
| Line 820... |
Line 834... |
always @ (posedge clk or negedge set_l)
|
always @ (posedge clk or negedge set_l)
|
q[SIZE-1:0] <= ~set_l ? {SIZE{1'b1}} : ({SIZE{~set_l}} | din[SIZE-1:0]);
|
q[SIZE-1:0] <= ~set_l ? {SIZE{1'b1}} : ({SIZE{~set_l}} | din[SIZE-1:0]);
|
|
|
endmodule // dffsl_async_ns
|
endmodule // dffsl_async_ns
|
|
|
// POSITIVE-EDGE TRIGGERED FLOP WITH SET_H , without SCAN.
|
|
|
|
|
// POSITIVE-EDGE TRIGGERED FLOP WITH SET_H , without SCAN.
|
module dffr_ns_r1 (din, clk, rst, q);
|
module dffr_ns_r1 (din, clk, rst, q);
|
// synopsys template
|
// synopsys template
|
parameter SIZE = 1;
|
parameter SIZE = 1;
|
|
|
input [SIZE-1:0] din ; // data in
|
input [SIZE-1:0] din ; // data in
|
| Line 841... |
Line 855... |
always @ (posedge clk)
|
always @ (posedge clk)
|
q[SIZE-1:0] <= rst ? {SIZE{1'b1}} : din[SIZE-1:0];
|
q[SIZE-1:0] <= rst ? {SIZE{1'b1}} : din[SIZE-1:0];
|
|
|
endmodule // dffr_ns_r1
|
endmodule // dffr_ns_r1
|
|
|
// POSITIVE-EDGE TRIGGERED ASYNC RESET_H FLOP , without SCAN.
|
|
|
|
|
// POSITIVE-EDGE TRIGGERED ASYNC RESET_H FLOP , without SCAN.
|
module dffr_async_ns (din, clk, rst, q);
|
module dffr_async_ns (din, clk, rst, q);
|
// synopsys template
|
// synopsys template
|
|
|
parameter SIZE = 1;
|
parameter SIZE = 1;
|
|
|
| Line 863... |
Line 877... |
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
q[SIZE-1:0] <= rst ? {SIZE{1'b0}} : din[SIZE-1:0];
|
q[SIZE-1:0] <= rst ? {SIZE{1'b0}} : din[SIZE-1:0];
|
|
|
endmodule // dffr_async_ns
|
endmodule // dffr_async_ns
|
|
|
// POSITIVE-EDGE TRIGGERED ASYNC SET_H FLOP , without SCAN.
|
|
|
|
|
// POSITIVE-EDGE TRIGGERED ASYNC SET_H FLOP , without SCAN.
|
module dffr_async_ns_r1 (din, clk, rst, q);
|
module dffr_async_ns_r1 (din, clk, rst, q);
|
// synopsys template
|
// synopsys template
|
|
|
parameter SIZE = 1;
|
parameter SIZE = 1;
|
|
|
| Line 887... |
Line 901... |
|
|
endmodule // dffr_async_ns_r1
|
endmodule // dffr_async_ns_r1
|
|
|
|
|
// NEGATIVE-EDGE TRIGGERED ASYNC SET_H FLOP , without SCAN.
|
// NEGATIVE-EDGE TRIGGERED ASYNC SET_H FLOP , without SCAN.
|
|
|
module dffr_async_ns_cl_r1 (din, clkl, rst, q);
|
module dffr_async_ns_cl_r1 (din, clkl, rst, q);
|
// synopsys template
|
// synopsys template
|
parameter SIZE = 1;
|
parameter SIZE = 1;
|
|
|
input [SIZE-1:0] din ; // data in
|
input [SIZE-1:0] din ; // data in
|
| Line 906... |
Line 919... |
// synopsys sync_set_reset "rst"
|
// synopsys sync_set_reset "rst"
|
always @ (negedge clkl or posedge rst)
|
always @ (negedge clkl or posedge rst)
|
q[SIZE-1:0] <= rst ? {SIZE{1'b1}} : din[SIZE-1:0];
|
q[SIZE-1:0] <= rst ? {SIZE{1'b1}} : din[SIZE-1:0];
|
|
|
endmodule // dffr_async_ns_cl_r1
|
endmodule // dffr_async_ns_cl_r1
|
|
`endif
|
|
|
No newline at end of file
|
No newline at end of file
|
