| Line 75... |
Line 75... |
// reg declaration does not imply state being maintained
|
// reg declaration does not imply state being maintained
|
// across cycles. Used to construct case statement and
|
// across cycles. Used to construct case statement and
|
// always updated by inputs every cycle.
|
// always updated by inputs every cycle.
|
reg [SIZE-1:0] dout ;
|
reg [SIZE-1:0] dout ;
|
|
|
|
`ifdef VERPLEX
|
|
$constraint dl_1c_chk4 ($one_cold ({sel3_l,sel2_l,sel1_l,sel0_l}));
|
|
`endif
|
|
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wire [3:0] sel = {sel3_l,sel2_l,sel1_l,sel0_l}; // 0in one_cold
|
wire [3:0] sel = {sel3_l,sel2_l,sel1_l,sel0_l}; // 0in one_cold
|
|
|
always @ (sel0_l or sel1_l or sel2_l or sel3_l or in0 or in1 or in2 or in3)
|
always @ (sel0_l or sel1_l or sel2_l or sel3_l or in0 or in1 or in2 or in3)
|
|
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| Line 96... |
Line 96... |
|
|
endmodule // dp_mux4ds
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endmodule // dp_mux4ds
|
|
|
// ----------------------------------------------------------------------
|
// ----------------------------------------------------------------------
|
|
|
|
`ifndef SIMPLY_RISC_TWEAKS
|
// 5:1 MUX WITH DECODED SELECTS
|
// 5:1 MUX WITH DECODED SELECTS
|
module dp_mux5ds (dout, in0, in1, in2, in3, in4,
|
module dp_mux5ds (dout, in0, in1, in2, in3, in4,
|
sel0_l, sel1_l, sel2_l, sel3_l, sel4_l) ;
|
sel0_l, sel1_l, sel2_l, sel3_l, sel4_l) ;
|
// synopsys template
|
// synopsys template
|
|
|
| Line 121... |
Line 121... |
// reg declaration does not imply state being maintained
|
// reg declaration does not imply state being maintained
|
// across cycles. Used to construct case statement and
|
// across cycles. Used to construct case statement and
|
// always updated by inputs every cycle.
|
// always updated by inputs every cycle.
|
reg [SIZE-1:0] dout ;
|
reg [SIZE-1:0] dout ;
|
|
|
|
`ifdef VERPLEX
|
|
$constraint dl_1c_chk5 ($one_cold ({sel4_l,sel3_l,sel2_l,sel1_l,sel0_l}));
|
|
`endif
|
|
|
wire [4:0] sel = {sel4_l,sel3_l,sel2_l,sel1_l,sel0_l}; // 0in one_cold
|
wire [4:0] sel = {sel4_l,sel3_l,sel2_l,sel1_l,sel0_l}; // 0in one_cold
|
|
|
always @ (sel0_l or sel1_l or sel2_l or sel3_l or sel4_l or
|
always @ (sel0_l or sel1_l or sel2_l or sel3_l or sel4_l or
|
in0 or in1 or in2 or in3 or in4)
|
in0 or in1 or in2 or in3 or in4)
|
| Line 142... |
Line 142... |
default : dout = {SIZE{1'bx}} ;
|
default : dout = {SIZE{1'bx}} ;
|
endcase
|
endcase
|
|
|
endmodule // dp_mux5ds
|
endmodule // dp_mux5ds
|
|
|
// --------------------------------------------------------------------
|
|
|
|
|
// --------------------------------------------------------------------
|
// 8:1 MUX WITH DECODED SELECTS
|
// 8:1 MUX WITH DECODED SELECTS
|
module dp_mux8ds (dout, in0, in1, in2, in3,
|
module dp_mux8ds (dout, in0, in1, in2, in3,
|
in4, in5, in6, in7,
|
in4, in5, in6, in7,
|
sel0_l, sel1_l, sel2_l, sel3_l,
|
sel0_l, sel1_l, sel2_l, sel3_l,
|
sel4_l, sel5_l, sel6_l, sel7_l) ;
|
sel4_l, sel5_l, sel6_l, sel7_l) ;
|
| Line 176... |
Line 176... |
// reg declaration does not imply state being maintained
|
// reg declaration does not imply state being maintained
|
// across cycles. Used to construct case statement and
|
// across cycles. Used to construct case statement and
|
// always updated by inputs every cycle.
|
// always updated by inputs every cycle.
|
reg [SIZE-1:0] dout ;
|
reg [SIZE-1:0] dout ;
|
|
|
|
`ifdef VERPLEX
|
|
$constraint dl_1c_chk8 ($one_cold ({sel7_l,sel6_l,sel5_l,sel4_l,
|
|
sel3_l,sel2_l,sel1_l,sel0_l}));
|
|
`endif
|
|
|
wire [7:0] sel = {sel7_l,sel6_l,sel5_l,sel4_l,
|
wire [7:0] sel = {sel7_l,sel6_l,sel5_l,sel4_l,
|
sel3_l,sel2_l,sel1_l,sel0_l}; // 0in one_cold
|
sel3_l,sel2_l,sel1_l,sel0_l}; // 0in one_cold
|
|
|
always @ (sel0_l or sel1_l or sel2_l or sel3_l or in0 or in1 or in2 or in3 or
|
always @ (sel0_l or sel1_l or sel2_l or sel3_l or in0 or in1 or in2 or in3 or
|
| Line 201... |
Line 201... |
8'b11111111 : dout = {SIZE{1'bx}} ;
|
8'b11111111 : dout = {SIZE{1'bx}} ;
|
default : dout = {SIZE{1'bx}} ;
|
default : dout = {SIZE{1'bx}} ;
|
endcase
|
endcase
|
|
|
endmodule // dp_mux8ds
|
endmodule // dp_mux8ds
|
|
`endif
|
|
|
// ----------------------------------------------------------------------
|
// ----------------------------------------------------------------------
|
|
|
|
|
// 3:1 MUX WITH DECODED SELECTS
|
// 3:1 MUX WITH DECODED SELECTS
|
| Line 226... |
Line 226... |
// reg declaration does not imply state being maintained
|
// reg declaration does not imply state being maintained
|
// across cycles. Used to construct case statement and
|
// across cycles. Used to construct case statement and
|
// always updated by inputs every cycle.
|
// always updated by inputs every cycle.
|
reg [SIZE-1:0] dout ;
|
reg [SIZE-1:0] dout ;
|
|
|
|
`ifdef VERPLEX
|
|
$constraint dl_1c_chk3 ($one_cold ({sel2_l,sel1_l,sel0_l}));
|
|
`endif
|
|
|
wire [2:0] sel = {sel2_l,sel1_l,sel0_l}; // 0in one_cold
|
wire [2:0] sel = {sel2_l,sel1_l,sel0_l}; // 0in one_cold
|
|
|
always @ (sel0_l or sel1_l or sel2_l or in0 or in1 or in2)
|
always @ (sel0_l or sel1_l or sel2_l or in0 or in1 or in2)
|
|
|
