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[/] [s1_core/] [trunk/] [hdl/] [rtl/] [sparc_core/] [tlu_hyperv.v] - Diff between revs 105 and 113

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Line 16... Line 16... 
// You should have received a copy of the GNU General Public
 
// You should have received a copy of the GNU General Public
 
// License along with this work; if not, write to the Free Software
 
// License along with this work; if not, write to the Free Software
 
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
 
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
 
// 
// 
// ========== Copyright Header End ============================================
 
// ========== Copyright Header End ============================================
 
 
 
`ifdef SIMPLY_RISC_TWEAKS
 
 
 
`define SIMPLY_RISC_SCANIN .si(0)
 
 
 
`else
 
 
 
`define SIMPLY_RISC_SCANIN .si()
 
 
 
`endif
 
////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////
 
/*
 
/*
 
//      Description:    Block that contain most of the Hypervisor support
 
//      Description:    Block that contain most of the Hypervisor support
 
//                      additions
 
//                      additions
 
*/
 
*/
 
////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////
 
// Global header file includes
 
// Global header file includes
 
////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////
 
// system level definition file which contains the/*
 
`include        "sys.h" // system level definition file which contains the
 
/* ========== Copyright Header Begin ==========================================
 
                        // time scale definition
 
*
 
 
 
* OpenSPARC T1 Processor File: sys.h
 
 
 
* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
 
 
 
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
 
 
 
*
 
 
 
* The above named program is free software; you can redistribute it and/or
 
 
 
* modify it under the terms of the GNU General Public
 
 
 
* License version 2 as published by the Free Software Foundation.
 
 
 
*
 
 
 
* The above named program is distributed in the hope that it will be
 
 
 
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
 
 
 
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 
 
 
* General Public License for more details.
 
 
 
*
 
 
 
* You should have received a copy of the GNU General Public
 
 
 
* License along with this work; if not, write to the Free Software
 
 
 
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
 
 
 
*
 
 
 
* ========== Copyright Header End ============================================
 
 
 
*/
 
 
 
// -*- verilog -*-
 
 
 
////////////////////////////////////////////////////////////////////////
 
 
 
/*
 
 
 
//
 
 
 
// Description:         Global header file that contain definitions that
 
 
 
//                      are common/shared at the systme level
 
 
 
*/
 
 
 
////////////////////////////////////////////////////////////////////////
 
 
 
//
 
 
 
// Setting the time scale
 
 
 
// If the timescale changes, JP_TIMESCALE may also have to change.
 
 
 
`timescale      1ps/1ps
 
 
 
 
 
 
 
//
 
 
 
// JBUS clock
 
 
 
// =========
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Afara Link Defines
 
 
 
// ==================
 
 
 
 
 
 
 
// Reliable Link
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Afara Link Objects
 
 
 
 
 
 
 
 
 
 
 
// Afara Link Object Format - Reliable Link
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Afara Link Object Format - Congestion
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Afara Link Object Format - Acknowledge
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Afara Link Object Format - Request
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Afara Link Object Format - Message
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Acknowledge Types
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Request Types
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Afara Link Frame
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// UCB Packet Type
 
 
 
// ===============
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// UCB Data Packet Format
 
 
 
// ======================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Size encoding for the UCB_SIZE_HI/LO field
 
 
 
// 000 - byte
 
 
 
// 001 - half-word
 
 
 
// 010 - word
 
 
 
// 011 - double-word
 
 
 
// 111 - quad-word
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// UCB Interrupt Packet Format
 
 
 
// ===========================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//`define UCB_THR_HI             9      // (6) cpu/thread ID shared with
 
 
 
//`define UCB_THR_LO             4             data packet format
 
 
 
//`define UCB_PKT_HI             3      // (4) packet type shared with
 
 
 
//`define UCB_PKT_LO             0      //     data packet format
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// FCRAM Bus Widths
 
 
 
// ================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// ENET clock periods
 
 
 
// ==================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// JBus Bridge defines
 
 
 
// =================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// PCI Device Address Configuration
 
 
 
// ================================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
                        // time scale definition
 
 
 
 
 
 
 
/*
 
 
 
/* ========== Copyright Header Begin ==========================================
 
 
 
*
 
 
 
* OpenSPARC T1 Processor File: tlu.h
 
 
 
* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
 
 
 
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
 
 
 
*
 
 
 
* The above named program is free software; you can redistribute it and/or
 
 
 
* modify it under the terms of the GNU General Public
 
 
 
* License version 2 as published by the Free Software Foundation.
 
 
 
*
 
 
 
* The above named program is distributed in the hope that it will be
 
 
 
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
 
 
 
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 
 
 
* General Public License for more details.
 
 
 
*
 
 
 
* You should have received a copy of the GNU General Public
 
 
 
* License along with this work; if not, write to the Free Software
 
 
 
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
 
 
 
*
 
 
 
* ========== Copyright Header End ============================================
 
 
 
*/
 
 
 
// ifu trap types
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// modified for hypervisor support
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
// modified due to bug 2588
 
 
 
// `define      TSA_PSTATE_VRANGE2_LO 16 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// added due to Niagara SRAMs methodology
 
 
 
// The following defines have been replaced due
 
 
 
// the memory macro replacement from:
 
 
 
// bw_r_rf32x144 -> 2x bw_r_rf32x80
 
 
 
/*
 
 
 
`define TSA_MEM_WIDTH     144
 
 
 
`define TSA_HTSTATE_HI    142 //  3 bits
 
 
 
`define TSA_HTSTATE_LO    140
 
 
 
`define TSA_TPC_HI        138 // 47 bits
 
 
 
`define TSA_TPC_LO         92
 
 
 
`define TSA_TNPC_HI        90 // 47 bits
 
 
 
`define TSA_TNPC_LO        44
 
 
 
`define TSA_TSTATE_HI      40 // 29 bits
 
 
 
`define TSA_TSTATE_LO      12
 
 
 
`define TSA_TTYPE_HI        8 //  9 bits
 
 
 
`define TSA_TTYPE_LO        0
 
 
 
`define TSA_MEM_CWP_LO     12
 
 
 
`define TSA_MEM_CWP_HI     14
 
 
 
`define TSA_MEM_PSTATE_LO  15
 
 
 
`define TSA_MEM_PSTATE_HI  22
 
 
 
`define TSA_MEM_ASI_LO     23
 
 
 
`define TSA_MEM_ASI_HI     30
 
 
 
`define TSA_MEM_CCR_LO     31
 
 
 
`define TSA_MEM_CCR_HI     38
 
 
 
`define TSA_MEM_GL_LO      39
 
 
 
`define TSA_MEM_GL_HI      40
 
 
 
*/
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// HPSTATE position definitions within wsr
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// TSTATE postition definitions within wsr
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// modified due to bug 2588
 
 
 
 
 
 
 
 
 
 
 
// added for bug 2584 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// tick_cmp and stick_cmp definitions
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// PIB WRAP
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// HPSTATE postition definitions
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// HTBA definitions
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// TBA definitions
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// added for the hypervisor support
 
 
 
 
 
 
 
 
 
 
 
// modified due to bug 2588
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// compressed PSTATE WSR definitions
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// ASI_QUEUE for hypervisor
 
 
 
// Queues are: CPU_MONODO
 
 
 
//             DEV_MONODO
 
 
 
//             RESUMABLE_ERROR
 
 
 
//             NON_RESUMABLE_ERROR
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// for address range checking
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// Niagara scratch-pads
 
 
 
// VA address of 0x20 and 0x28 are exclusive to hypervisor
 
 
 
// 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// range checking 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// PIB related definitions
 
 
 
// Bit definition for events
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// 
 
 
// PIB related definitions
 
 
 
// PCR and PIC address definitions
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// 
 
 
// PCR bit definitions
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// PIC definitions
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// PIC  mask bit position definitions
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// added define from sparc_tlu_int.v 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// shadow scan related definitions 
 
 
 
 
 
 
// modified due to logic redistribution
 
 
 
// `define TCL_SSCAN_WIDTH 12 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// `define TCL_SSCAN_LO 51 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// 
 
 
// position definitions - TDP
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// 
 
 
// position definitions - TCL
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// 
 
 
// To speedup POR for verification purposes
 
 
 
 
 
 
 
 
 
`include "tlu.h"
 
 
 
 
 
////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////
 
// Local header file includes / local defines
 
// Local header file includes / local defines
 
////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////
 
 
 
 
Line 745... Line 75... 
output [1:0] tlu_exu_agp;
 
output [1:0] tlu_exu_agp;
 
// output [1:0] tlu_exu_agp_tid;  
// output [1:0] tlu_exu_agp_tid;  
output tlu_exu_agp_swap;
 
output tlu_exu_agp_swap;
 
//
 
//
 
// global register outputs
 
// global register outputs
 
output [2-1:0] tlu_gl_lvl0; // global register value t0 
output [`TSA_GLOBAL_WIDTH-1:0] tlu_gl_lvl0; // global register value t0 
output [2-1:0] tlu_gl_lvl1; // global register value t1 
output [`TSA_GLOBAL_WIDTH-1:0] tlu_gl_lvl1; // global register value t1 
output [2-1:0] tlu_gl_lvl2; // global register value t2 
output [`TSA_GLOBAL_WIDTH-1:0] tlu_gl_lvl2; // global register value t2 
output [2-1:0] tlu_gl_lvl3; // global register value t3 
output [`TSA_GLOBAL_WIDTH-1:0] tlu_gl_lvl3; // global register value t3 
 
 
 
 
// mux selects to choose source of data to store in the hpstate regs 
// mux selects to choose source of data to store in the hpstate regs 
output [1:0] tlu_hpstate_din_sel0;
 
output [1:0] tlu_hpstate_din_sel0;
 
output [1:0] tlu_hpstate_din_sel1;
 
output [1:0] tlu_hpstate_din_sel1;
 
output [1:0] tlu_hpstate_din_sel2;
 
output [1:0] tlu_hpstate_din_sel2;
Line 765... Line 95... 
// output       tlu_rdpr_mx5_active; 
// output       tlu_rdpr_mx5_active; 
//
 
//
 
// hpstate write enable
 
// hpstate write enable
 
// modified for timing
 
// modified for timing
 
// output [`TLU_THRD_NUM-1:0] tlu_update_hpstate_l_g;
 
// output [`TLU_THRD_NUM-1:0] tlu_update_hpstate_l_g;
 
output [4-1:0] tlu_update_hpstate_l_w2;
 
output [`TLU_THRD_NUM-1:0] tlu_update_hpstate_l_w2;
 
//
 
//
 
// htick compare reg write enable 
// htick compare reg write enable 
// output [`TLU_THRD_NUM-1:0] htickcmp_intdis_en;
 
// output [`TLU_THRD_NUM-1:0] htickcmp_intdis_en;
 
// htick compare interrupt disable
 
// htick compare interrupt disable
 
output tlu_htickcmp_intdis;
 
output tlu_htickcmp_intdis;
 
 
 
 
 
//  clock enable for hintp regs.
 
//  clock enable for hintp regs.
 
// output [`TLU_THRD_NUM-1:0] tlu_hintp_en_l_g;
 
// output [`TLU_THRD_NUM-1:0] tlu_hintp_en_l_g;
 
// wr control for hintp regs.
 
// wr control for hintp regs.
 
output [4-1:0] tlu_wr_hintp_g;
 
output [`TLU_THRD_NUM-1:0] tlu_wr_hintp_g;
 
// set control for hintp regs.
 
// set control for hintp regs.
 
// output [`TLU_THRD_NUM-1:0] tlu_set_hintp_g;
 
// output [`TLU_THRD_NUM-1:0] tlu_set_hintp_g;
 
output [4-1:0] tlu_set_hintp_sel_g;
 
output [`TLU_THRD_NUM-1:0] tlu_set_hintp_sel_g;
 
//
 
//
 
// update enable for the htba registers 
// update enable for the htba registers 
output [4-1:0] tlu_htba_en_l;
 
output [`TLU_THRD_NUM-1:0] tlu_htba_en_l;
 
// 
// 
// hypervisor lite indicator
 
// hypervisor lite indicator
 
// output [`TLU_THRD_NUM-1:0] tlu_hyper_lite;
 
// output [`TLU_THRD_NUM-1:0] tlu_hyper_lite;
 
// 
// 
// hyper-privileged scratch-pad data access exception 
// hyper-privileged scratch-pad data access exception 
output tlu_hscpd_dacc_excpt_m;
 
output tlu_hscpd_dacc_excpt_m;
 
//
 
//
 
// store instruction to alt space
 
// store instruction to alt space
 
output tlu_asi_write_g;
 
output tlu_asi_write_g;
 
output [4-1:0] inc_ind_asi_wr_indr;
 
output [`TLU_THRD_NUM-1:0] inc_ind_asi_wr_indr;
 
output [4-1:0] inc_ind_asi_wr_inrr;
 
output [`TLU_THRD_NUM-1:0] inc_ind_asi_wr_inrr;
 
output [4-1:0] inc_ind_asi_rd_invr;
 
output [`TLU_THRD_NUM-1:0] inc_ind_asi_rd_invr;
 
output [4-1:0] tlu_local_thrid_g;
 
output [`TLU_THRD_NUM-1:0] tlu_local_thrid_g;
 
 
 
 
 
// read and write valids for the scratch-pad 
// read and write valids for the scratch-pad 
output tlu_scpd_rd_vld_m, tlu_scpd_wr_vld_g;
 
output tlu_scpd_rd_vld_m, tlu_scpd_wr_vld_g;
 
output [5-1:0] tlu_scpd_wr_addr_g;
 
output [`SCPD_RW_ADDR_WIDTH-1:0] tlu_scpd_wr_addr_g;
 
output [5-1:0] tlu_scpd_rd_addr_m;
 
output [`SCPD_RW_ADDR_WIDTH-1:0] tlu_scpd_rd_addr_m;
 
//
 
//
 
// decode of the htstate register write/read
 
// decode of the htstate register write/read
 
output tlu_htstate_rw_d;
 
output tlu_htstate_rw_d;
 
output tlu_htstate_rw_g;
 
output tlu_htstate_rw_g;
 
// 
// 
// select for rdpr read in tlu_tdp
 
// select for rdpr read in tlu_tdp
 
// output tlu_htba_rsr_sel; 
// output tlu_htba_rsr_sel; 
// 
// 
// 
// 
output [4-1:0] tlu_cpu_mondo_cmp;
 
output [`TLU_THRD_NUM-1:0] tlu_cpu_mondo_cmp;
 
output [4-1:0] tlu_dev_mondo_cmp;
 
output [`TLU_THRD_NUM-1:0] tlu_dev_mondo_cmp;
 
output [4-1:0] tlu_resum_err_cmp;
 
output [`TLU_THRD_NUM-1:0] tlu_resum_err_cmp;
 
output tlu_qtail_dacc_excpt_m;
 
output tlu_qtail_dacc_excpt_m;
 
//
 
//
 
// asi queue rdata output
 
// asi queue rdata output
 
output [8-1:0] tlu_asi_queue_rdata_g;
 
output [`TLU_ASI_QUE_WIDTH-1:0] tlu_asi_queue_rdata_g;
 
output tlu_asi_queue_rd_vld_g;
 
output tlu_asi_queue_rd_vld_g;
 
output tlu_ld_data_vld_g;
 
output tlu_ld_data_vld_g;
 
// output tlu_scpd_rd_vld_g;
 
// output tlu_scpd_rd_vld_g;
 
output tlu_va_ill_g;
 
output tlu_va_ill_g;
 
// output tlu_va_all_zero_g;
 
// output tlu_va_all_zero_g;
Line 840... Line 170... 
// modified for timing 
// modified for timing 
// input tlu_wsr_inst_g;
 
// input tlu_wsr_inst_g;
 
input tlu_wsr_inst_nq_g;
 
input tlu_wsr_inst_nq_g;
 
 
 
 
 
// non-threaded por instruciton 
// non-threaded por instruciton 
input [4-1:0] tlu_por_rstint_g;
 
input [`TLU_THRD_NUM-1:0] tlu_por_rstint_g;
 
// 
// 
// addr of sr(st/pr)
 
// addr of sr(st/pr)
 
input [7-1:0] ifu_tlu_sraddr_d;
 
input [`TLU_ASR_ADDR_WIDTH-1:0] ifu_tlu_sraddr_d;
 
//
 
//
 
// staged pr/st data from irf.
 
// staged pr/st data from irf.
 
input [4-1:0] tlu_wsr_data_w_global;
 
input [`TLU_GLOBAL_WIDTH-1:0] tlu_wsr_data_w_global;
 
 
 
 
 
// restored global value for done/retry instructions 
// restored global value for done/retry instructions 
input [2-1:0] tlu_dnrtry_global_g;
 
input [`TSA_GLOBAL_WIDTH-1:0] tlu_dnrtry_global_g;
 
 
 
 
 
// thread specific done and retry signals
 
// thread specific done and retry signals
 
input tlu_dnrtry0_inst_g, tlu_dnrtry1_inst_g;
 
input tlu_dnrtry0_inst_g, tlu_dnrtry1_inst_g;
 
input tlu_dnrtry2_inst_g, tlu_dnrtry3_inst_g;
 
input tlu_dnrtry2_inst_g, tlu_dnrtry3_inst_g;
 
// 
// 
// thread specific trap assetion signals
 
// thread specific trap assetion signals
 
// modified due to timing
 
// modified due to timing
 
// input tlu_thrd0_traps, tlu_thrd1_traps;
 
// input tlu_thrd0_traps, tlu_thrd1_traps;
 
// input tlu_thrd2_traps, tlu_thrd3_traps;
 
// input tlu_thrd2_traps, tlu_thrd3_traps;
 
input [4-1:0] tlu_thrd_traps_w2;
 
input [`TLU_THRD_NUM-1:0] tlu_thrd_traps_w2;
 
// 
// 
// indicating whether the trap is supervisor or hypervisor 
// indicating whether the trap is supervisor or hypervisor 
// added for bug 2889
 
// added for bug 2889
 
// modified due to timing
 
// modified due to timing
 
// input tlu_select_tba_g; 
// input tlu_select_tba_g;
Line 872... Line 202... 
input tlu_tick_ctl_din;
 
input tlu_tick_ctl_din;
 
// htick compare match
 
// htick compare match
 
// input tlu_htick_match;       
// input tlu_htick_match;       
//
 
//
 
// select src for tickcmp 
// select src for tickcmp 
input [4-1:0] tlu_tickcmp_sel;
 
input [`TLU_THRD_NUM-1:0] tlu_tickcmp_sel;
 
// 
// 
// pstate - supervisor privilege  
// pstate - supervisor privilege  
input [4-1:0] tlu_pstate_priv;
 
input [`TLU_THRD_NUM-1:0] tlu_pstate_priv;
 
// hpstate - hypervisor privilege  
// hpstate - hypervisor privilege  
input [4-1:0] tlu_hpstate_priv;
 
input [`TLU_THRD_NUM-1:0] tlu_hpstate_priv;
 
// hpstate - hypervisor lite enb  
// hpstate - hypervisor lite enb  
input [4-1:0] tlu_hpstate_enb;
 
input [`TLU_THRD_NUM-1:0] tlu_hpstate_enb;
 
// thread id for the agp that needs swap
 
// thread id for the agp that needs swap
 
// modified for timing
 
// modified for timing
 
// input [1:0] tlu_agp_tid_g;
 
// input [1:0] tlu_agp_tid_g;
 
input [1:0] tlu_agp_tid_w2;
 
input [1:0] tlu_agp_tid_w2;
 
// ASI addresses and valid bits for decode to 
// ASI addresses and valid bits for decode to
Line 898... Line 228... 
input       lsu_tlu_early_flush_w;   // trap flush 
input       lsu_tlu_early_flush_w;   // trap flush 
input       tlu_asi_data_nf_vld_w2;   // trap flush 
input       tlu_asi_data_nf_vld_w2;   // trap flush 
input       tlu_inst_vld_m;     // instruciton valid 
input       tlu_inst_vld_m;     // instruciton valid 
//
 
//
 
// asi to be read/written
 
// asi to be read/written
 
input [8-1:0] tlu_asi_state_e;
 
input [`TLU_ASI_STATE_WIDTH-1:0] tlu_asi_state_e;
 
// input [`TLU_ASI_VA_WIDTH-1:0] exu_lsu_ldst_va_e;  
// input [`TLU_ASI_VA_WIDTH-1:0] exu_lsu_ldst_va_e;  
input [10-1:0] lsu_tlu_ldst_va_m;
 
input [`TLU_ASI_VA_WIDTH-1:0] lsu_tlu_ldst_va_m;
 
// head and tail pointers
 
// head and tail pointers
 
input [8-1:0] tlu_asi_queue_data_g;
 
input [`TLU_ASI_QUE_WIDTH-1:0] tlu_asi_queue_data_g;
 
 
 
 
 
//reset
 
//reset
 
// input tlu_rst_l;  // unit reset
 
// input tlu_rst_l;  // unit reset
 
input grst_l ;  // unit reset
 
input grst_l ;  // unit reset
 
input arst_l ;  // unit reset
 
input arst_l ;  // unit reset
Line 920... Line 250... 
/*AUTOOUTPUT*/
 
/*AUTOOUTPUT*/
 
//
 
//
 
// staged thread id
 
// staged thread id
 
wire [1:0] thrid_e, thrid_m, thrid_g;
 
wire [1:0] thrid_e, thrid_m, thrid_g;
 
// decoded thread id
 
// decoded thread id
 
wire [4-1:0] thread_sel_id_e;
 
wire [`TLU_THRD_NUM-1:0] thread_sel_id_e;
 
wire [4-1:0] thread_sel_id_m;
 
wire [`TLU_THRD_NUM-1:0] thread_sel_id_m;
 
wire [4-1:0] thread_sel_id_g;
 
wire [`TLU_THRD_NUM-1:0] thread_sel_id_g;
 
wire [4-1:0] thread_sel_id_w2;
 
wire [`TLU_THRD_NUM-1:0] thread_sel_id_w2;
 
// 
// 
// flush due to "early traps"
 
// flush due to "early traps"
 
wire        local_flush_all_w;   // trap flush 
wire        local_flush_all_w;   // trap flush 
wire        local_flush_all_w2;   // trap flush 
wire        local_flush_all_w2;   // trap flush 
//
 
//
 
// por indicators generations 
// por indicators generations 
wire por_rstint0_g, por_rstint1_g;
 
wire por_rstint0_g, por_rstint1_g;
 
wire por_rstint2_g, por_rstint3_g;
 
wire por_rstint2_g, por_rstint3_g;
 
//
 
//
 
// GL register definitions - one GL register/thread
 
// GL register definitions - one GL register/thread
 
wire [2-1:0] gl_lvl0, gl_lvl1, gl_lvl2, gl_lvl3;
 
wire [`TSA_GLOBAL_WIDTH-1:0] gl_lvl0, gl_lvl1, gl_lvl2, gl_lvl3;
 
// updated value of the GL registers 
// updated value of the GL registers 
wire [2-1:0] gl_lvl0_new, gl_lvl1_new;
 
wire [`TSA_GLOBAL_WIDTH-1:0] gl_lvl0_new, gl_lvl1_new;
 
wire [2-1:0] gl_lvl2_new, gl_lvl3_new;
 
wire [`TSA_GLOBAL_WIDTH-1:0] gl_lvl2_new, gl_lvl3_new;
 
wire [2-1:0] gl_lvl0_update_g, gl_lvl1_update_g;
 
wire [`TSA_GLOBAL_WIDTH-1:0] gl_lvl0_update_g, gl_lvl1_update_g;
 
wire [2-1:0] gl_lvl2_update_g, gl_lvl3_update_g;
 
wire [`TSA_GLOBAL_WIDTH-1:0] gl_lvl2_update_g, gl_lvl3_update_g;
 
wire [2-1:0] gl_lvl0_update_w2, gl_lvl1_update_w2;
 
wire [`TSA_GLOBAL_WIDTH-1:0] gl_lvl0_update_w2, gl_lvl1_update_w2;
 
wire [2-1:0] gl_lvl2_update_w2, gl_lvl3_update_w2;
 
wire [`TSA_GLOBAL_WIDTH-1:0] gl_lvl2_update_w2, gl_lvl3_update_w2;
 
wire [2-1:0] wsr_gl_lvl0_data, wsr_gl_lvl1_data;
 
wire [`TSA_GLOBAL_WIDTH-1:0] wsr_gl_lvl0_data, wsr_gl_lvl1_data;
 
wire [2-1:0] wsr_gl_lvl2_data, wsr_gl_lvl3_data;
 
wire [`TSA_GLOBAL_WIDTH-1:0] wsr_gl_lvl2_data, wsr_gl_lvl3_data;
 
wire [2-1:0] dnrtry_gl_lvl0_data, dnrtry_gl_lvl1_data;
 
wire [`TSA_GLOBAL_WIDTH-1:0] dnrtry_gl_lvl0_data, dnrtry_gl_lvl1_data;
 
wire [2-1:0] dnrtry_gl_lvl2_data, dnrtry_gl_lvl3_data;
 
wire [`TSA_GLOBAL_WIDTH-1:0] dnrtry_gl_lvl2_data, dnrtry_gl_lvl3_data;
 
// value to be incremented for the GL registers
 
// value to be incremented for the GL registers
 
// modified due to timing
 
// modified due to timing
 
// wire gl0_incr_sel, gl1_incr_sel, gl2_incr_sel, gl3_incr_sel; 
// wire gl0_incr_sel, gl1_incr_sel, gl2_incr_sel, gl3_incr_sel; 
// wire[1:0] gl_lvl0_incr, gl_lvl1_incr, gl_lvl2_incr, gl_lvl3_incr; 
// wire[1:0] gl_lvl0_incr, gl_lvl1_incr, gl_lvl2_incr, gl_lvl3_incr; 
// indicators to signal gl is at certain pre-defined values 
// indicators to signal gl is at certain pre-defined values 
// added for timing
 
// added for timing
 
wire [4-1:0] gl_incr_sel_w2;
 
wire [`TLU_THRD_NUM-1:0] gl_incr_sel_w2;
 
wire [4-1:0] gl_update_sel_g;
 
wire [`TLU_THRD_NUM-1:0] gl_update_sel_g;
 
wire [4-1:0] gl_update_sel_w2;
 
wire [`TLU_THRD_NUM-1:0] gl_update_sel_w2;
 
wire [4-1:0] gl_priv_max_sel_w2;
 
wire [`TLU_THRD_NUM-1:0] gl_priv_max_sel_w2;
 
wire gl_lvl0_at_maxgl, gl_lvl1_at_maxgl;
 
wire gl_lvl0_at_maxgl, gl_lvl1_at_maxgl;
 
wire gl_lvl2_at_maxgl, gl_lvl3_at_maxgl;
 
wire gl_lvl2_at_maxgl, gl_lvl3_at_maxgl;
 
wire gl_lvl0_at_maxstl, gl_lvl1_at_maxstl;
 
wire gl_lvl0_at_maxstl, gl_lvl1_at_maxstl;
 
wire gl_lvl2_at_maxstl, gl_lvl3_at_maxstl;
 
wire gl_lvl2_at_maxstl, gl_lvl3_at_maxstl;
 
// gl write enables  
// gl write enables  
wire gl0_en, gl1_en, gl2_en, gl3_en;
 
wire gl0_en, gl1_en, gl2_en, gl3_en;
 
wire [4-1:0] dnrtry_inst_w2;
 
wire [`TLU_THRD_NUM-1:0] dnrtry_inst_w2;
 
// maxgl control
 
// maxgl control
 
wire [4-1:0] maxstl_gl_dnrtry_sel;
 
wire [`TLU_THRD_NUM-1:0] maxstl_gl_dnrtry_sel;
 
wire [4-1:0] maxstl_gl_wr_sel;
 
wire [`TLU_THRD_NUM-1:0] maxstl_gl_wr_sel;
 
wire [4-1:0] maxgl_gl_wr_sel;
 
wire [`TLU_THRD_NUM-1:0] maxgl_gl_wr_sel;
 
// decoded thread info for agp swap
 
// decoded thread info for agp swap
 
// wire [`TLU_THRD_NUM-1:0] agp_thrid;
 
// wire [`TLU_THRD_NUM-1:0] agp_thrid;
 
wire [4-1:0] agp_thrid_w2;
 
wire [`TLU_THRD_NUM-1:0] agp_thrid_w2;
 
// modified for for timing fix
 
// modified for for timing fix
 
// wire agp_swap; 
// wire agp_swap; 
// wire [1:0] agp_new; 
// wire [1:0] agp_new; 
wire wsr_inst_g, wsr_inst_w2;
 
wire wsr_inst_g, wsr_inst_w2;
 
wire agp_swap_w2, agp_swap_w3;
 
wire agp_swap_w2, agp_swap_w3;
 
wire [1:0] agp_new_w2, agp_new_w3;
 
wire [1:0] agp_new_w2, agp_new_w3;
 
//
 
//
 
// hyper-privileged ASR registers
 
// hyper-privileged ASR registers
 
wire [4-1:0] tlu_wr_hintp_g;
 
wire [`TLU_THRD_NUM-1:0] tlu_wr_hintp_g;
 
wire htba_rw_d, hpstate_rw_d, htstate_rw_d, hintp_rw_d;
 
wire htba_rw_d, hpstate_rw_d, htstate_rw_d, hintp_rw_d;
 
wire htickcmp_rw_d, gl_rw_d;
 
wire htickcmp_rw_d, gl_rw_d;
 
wire htba_rw_e, hpstate_rw_e, htstate_rw_e, hintp_rw_e;
 
wire htba_rw_e, hpstate_rw_e, htstate_rw_e, hintp_rw_e;
 
wire htickcmp_rw_e, gl_rw_e;
 
wire htickcmp_rw_e, gl_rw_e;
 
wire htba_rw_m, hpstate_rw_m, htstate_rw_m, hintp_rw_m;
 
wire htba_rw_m, hpstate_rw_m, htstate_rw_m, hintp_rw_m;
 
wire htickcmp_rw_m, gl_rw_m;
 
wire htickcmp_rw_m, gl_rw_m;
 
wire htba_rw_g, hpstate_rw_g, htstate_rw_g, hintp_rw_g;
 
wire htba_rw_g, hpstate_rw_g, htstate_rw_g, hintp_rw_g;
 
wire htickcmp_rw_g, gl_rw_g;
 
wire htickcmp_rw_g, gl_rw_g;
 
wire [4-1:0] htickcmp_intdis_en;
 
wire [`TLU_THRD_NUM-1:0] htickcmp_intdis_en;
 
wire hpstate_rw_w2;
 
wire hpstate_rw_w2;
 
//
 
//
 
// hyper-lite mode indicator
 
// hyper-lite mode indicator
 
wire [4-1:0] tlu_hyper_lite;
 
wire [`TLU_THRD_NUM-1:0] tlu_hyper_lite;
 
// 
// 
// contorls to update the hpstate registers
 
// contorls to update the hpstate registers
 
// wire update_hpstate0_g, update_hpstate1_g;
 
// wire update_hpstate0_g, update_hpstate1_g;
 
// wire update_hpstate2_g, update_hpstate3_g;
 
// wire update_hpstate2_g, update_hpstate3_g;
 
wire [4-1:0] update_hpstate_g;
 
wire [`TLU_THRD_NUM-1:0] update_hpstate_g;
 
wire [4-1:0] update_hpstate_w2;
 
wire [`TLU_THRD_NUM-1:0] update_hpstate_w2;
 
//
 
//
 
// htick interrupt disable control
 
// htick interrupt disable control
 
wire htick_intdis0, htick_intdis1;
 
wire htick_intdis0, htick_intdis1;
 
wire htick_intdis2, htick_intdis3;
 
wire htick_intdis2, htick_intdis3;
 
//
 
//
 
// local addr of sr(st/pr) 
// local addr of sr(st/pr) 
wire [7-3:0] sraddr;
 
wire [`TLU_ASR_ADDR_WIDTH-3:0] sraddr;
 
 
 
 
 
// ASI_QUEUE for hyper visor
 
// ASI_QUEUE for hyper visor
 
// thread 0
 
// thread 0
 
wire [8-1:0] cpu_mondo0_head;
 
wire [`TLU_ASI_QUE_WIDTH-1:0] cpu_mondo0_head;
 
wire [8-1:0] cpu_mondo0_tail;
 
wire [`TLU_ASI_QUE_WIDTH-1:0] cpu_mondo0_tail;
 
wire [8-1:0] dev_mondo0_head;
 
wire [`TLU_ASI_QUE_WIDTH-1:0] dev_mondo0_head;
 
wire [8-1:0] dev_mondo0_tail;
 
wire [`TLU_ASI_QUE_WIDTH-1:0] dev_mondo0_tail;
 
wire [8-1:0] resum_err0_head;
 
wire [`TLU_ASI_QUE_WIDTH-1:0] resum_err0_head;
 
wire [8-1:0] resum_err0_tail;
 
wire [`TLU_ASI_QUE_WIDTH-1:0] resum_err0_tail;
 
wire [8-1:0] nresum_err0_head;
 
wire [`TLU_ASI_QUE_WIDTH-1:0] nresum_err0_head;
 
wire [8-1:0] nresum_err0_tail;
 
wire [`TLU_ASI_QUE_WIDTH-1:0] nresum_err0_tail;
 
// thread 1
 
// thread 1
 
wire [8-1:0] cpu_mondo1_head;
 
wire [`TLU_ASI_QUE_WIDTH-1:0] cpu_mondo1_head;
 
wire [8-1:0] cpu_mondo1_tail;
 
wire [`TLU_ASI_QUE_WIDTH-1:0] cpu_mondo1_tail;
 
wire [8-1:0] dev_mondo1_head;
 
wire [`TLU_ASI_QUE_WIDTH-1:0] dev_mondo1_head;
 
wire [8-1:0] dev_mondo1_tail;
 
wire [`TLU_ASI_QUE_WIDTH-1:0] dev_mondo1_tail;
 
wire [8-1:0] resum_err1_head;
 
wire [`TLU_ASI_QUE_WIDTH-1:0] resum_err1_head;
 
wire [8-1:0] resum_err1_tail;
 
wire [`TLU_ASI_QUE_WIDTH-1:0] resum_err1_tail;
 
wire [8-1:0] nresum_err1_head;
 
wire [`TLU_ASI_QUE_WIDTH-1:0] nresum_err1_head;
 
wire [8-1:0] nresum_err1_tail;
 
wire [`TLU_ASI_QUE_WIDTH-1:0] nresum_err1_tail;
 
// thread 2
 
// thread 2
 
wire [8-1:0] cpu_mondo2_head;
 
wire [`TLU_ASI_QUE_WIDTH-1:0] cpu_mondo2_head;
 
wire [8-1:0] cpu_mondo2_tail;
 
wire [`TLU_ASI_QUE_WIDTH-1:0] cpu_mondo2_tail;
 
wire [8-1:0] dev_mondo2_head;
 
wire [`TLU_ASI_QUE_WIDTH-1:0] dev_mondo2_head;
 
wire [8-1:0] dev_mondo2_tail;
 
wire [`TLU_ASI_QUE_WIDTH-1:0] dev_mondo2_tail;
 
wire [8-1:0] resum_err2_head;
 
wire [`TLU_ASI_QUE_WIDTH-1:0] resum_err2_head;
 
wire [8-1:0] resum_err2_tail;
 
wire [`TLU_ASI_QUE_WIDTH-1:0] resum_err2_tail;
 
wire [8-1:0] nresum_err2_head;
 
wire [`TLU_ASI_QUE_WIDTH-1:0] nresum_err2_head;
 
wire [8-1:0] nresum_err2_tail;
 
wire [`TLU_ASI_QUE_WIDTH-1:0] nresum_err2_tail;
 
// thread 3
 
// thread 3
 
wire [8-1:0] cpu_mondo3_head;
 
wire [`TLU_ASI_QUE_WIDTH-1:0] cpu_mondo3_head;
 
wire [8-1:0] cpu_mondo3_tail;
 
wire [`TLU_ASI_QUE_WIDTH-1:0] cpu_mondo3_tail;
 
wire [8-1:0] dev_mondo3_head;
 
wire [`TLU_ASI_QUE_WIDTH-1:0] dev_mondo3_head;
 
wire [8-1:0] dev_mondo3_tail;
 
wire [`TLU_ASI_QUE_WIDTH-1:0] dev_mondo3_tail;
 
wire [8-1:0] resum_err3_head;
 
wire [`TLU_ASI_QUE_WIDTH-1:0] resum_err3_head;
 
wire [8-1:0] resum_err3_tail;
 
wire [`TLU_ASI_QUE_WIDTH-1:0] resum_err3_tail;
 
wire [8-1:0] nresum_err3_head;
 
wire [`TLU_ASI_QUE_WIDTH-1:0] nresum_err3_head;
 
wire [8-1:0] nresum_err3_tail;
 
wire [`TLU_ASI_QUE_WIDTH-1:0] nresum_err3_tail;
 
//
 
//
 
// read asi data from the asi queues
 
// read asi data from the asi queues
 
wire [8-1:0] cpu_mondo_hd_rdata;
 
wire [`TLU_ASI_QUE_WIDTH-1:0] cpu_mondo_hd_rdata;
 
wire [8-1:0] cpu_mondo_ta_rdata;
 
wire [`TLU_ASI_QUE_WIDTH-1:0] cpu_mondo_ta_rdata;
 
wire [8-1:0] dev_mondo_hd_rdata;
 
wire [`TLU_ASI_QUE_WIDTH-1:0] dev_mondo_hd_rdata;
 
wire [8-1:0] dev_mondo_ta_rdata;
 
wire [`TLU_ASI_QUE_WIDTH-1:0] dev_mondo_ta_rdata;
 
wire [8-1:0] resum_err_hd_rdata;
 
wire [`TLU_ASI_QUE_WIDTH-1:0] resum_err_hd_rdata;
 
wire [8-1:0] resum_err_ta_rdata;
 
wire [`TLU_ASI_QUE_WIDTH-1:0] resum_err_ta_rdata;
 
wire [8-1:0] nresum_err_hd_rdata;
 
wire [`TLU_ASI_QUE_WIDTH-1:0] nresum_err_hd_rdata;
 
wire [8-1:0] nresum_err_ta_rdata;
 
wire [`TLU_ASI_QUE_WIDTH-1:0] nresum_err_ta_rdata;
 
wire [8-1:0] asi_queue_rdata1_g;
 
wire [`TLU_ASI_QUE_WIDTH-1:0] asi_queue_rdata1_g;
 
wire [8-1:0] asi_queue_rdata2_g;
 
wire [`TLU_ASI_QUE_WIDTH-1:0] asi_queue_rdata2_g;
 
wire asi_qrdata_mx_sel2;
 
wire asi_qrdata_mx_sel2;
 
//
 
//
 
// head and tail comparison results
 
// head and tail comparison results
 
// modified due to timing violations
 
// modified due to timing violations
 
// wire cpu_mondo_head_rw_e,  cpu_mondo_tail_rw_e;
 
// wire cpu_mondo_head_rw_e,  cpu_mondo_tail_rw_e;
Line 1079... Line 409... 
// wire cpu_mondo_hd_onehot_g, cpu_mondo_ta_onehot_g;
 
// wire cpu_mondo_hd_onehot_g, cpu_mondo_ta_onehot_g;
 
// wire dev_mondo_hd_onehot_g, dev_mondo_ta_onehot_g;
 
// wire dev_mondo_hd_onehot_g, dev_mondo_ta_onehot_g;
 
// wire resum_err_hd_onehot_g, resum_err_ta_onehot_g;
 
// wire resum_err_hd_onehot_g, resum_err_ta_onehot_g;
 
// wire nresum_err_hd_onehot_g, nresum_err_ta_onehot_g;
 
// wire nresum_err_hd_onehot_g, nresum_err_ta_onehot_g;
 
// read 
// read 
wire [4-1:0] cpu_mondo_head_rd_g;
 
wire [`TLU_THRD_NUM-1:0] cpu_mondo_head_rd_g;
 
wire cpu_mondo_hd_rd_g;
 
wire cpu_mondo_hd_rd_g;
 
wire [4-1:0] cpu_mondo_tail_rd_g;
 
wire [`TLU_THRD_NUM-1:0] cpu_mondo_tail_rd_g;
 
wire cpu_mondo_ta_rd_g;
 
wire cpu_mondo_ta_rd_g;
 
wire [4-1:0] dev_mondo_head_rd_g;
 
wire [`TLU_THRD_NUM-1:0] dev_mondo_head_rd_g;
 
wire dev_mondo_hd_rd_g;
 
wire dev_mondo_hd_rd_g;
 
wire [4-1:0] dev_mondo_tail_rd_g;
 
wire [`TLU_THRD_NUM-1:0] dev_mondo_tail_rd_g;
 
wire dev_mondo_ta_rd_g;
 
wire dev_mondo_ta_rd_g;
 
wire [4-1:0] resum_err_head_rd_g;
 
wire [`TLU_THRD_NUM-1:0] resum_err_head_rd_g;
 
wire resum_err_hd_rd_g;
 
wire resum_err_hd_rd_g;
 
wire [4-1:0] resum_err_tail_rd_g;
 
wire [`TLU_THRD_NUM-1:0] resum_err_tail_rd_g;
 
wire resum_err_ta_rd_g;
 
wire resum_err_ta_rd_g;
 
wire [4-1:0] nresum_err_head_rd_g;
 
wire [`TLU_THRD_NUM-1:0] nresum_err_head_rd_g;
 
wire nresum_err_hd_rd_g;
 
wire nresum_err_hd_rd_g;
 
wire [4-1:0] nresum_err_tail_rd_g;
 
wire [`TLU_THRD_NUM-1:0] nresum_err_tail_rd_g;
 
wire nresum_err_ta_rd_g;
 
wire nresum_err_ta_rd_g;
 
wire [3:0] asi_qrdata_mx1_sel;
 
wire [3:0] asi_qrdata_mx1_sel;
 
wire [3:0] asi_qrdata_mx2_sel;
 
wire [3:0] asi_qrdata_mx2_sel;
 
// write 
// write 
wire [4-1:0] cpu_mondo_head_wr_g;
 
wire [`TLU_THRD_NUM-1:0] cpu_mondo_head_wr_g;
 
wire [4-1:0] cpu_mondo_tail_wr_g;
 
wire [`TLU_THRD_NUM-1:0] cpu_mondo_tail_wr_g;
 
wire [4-1:0] dev_mondo_head_wr_g;
 
wire [`TLU_THRD_NUM-1:0] dev_mondo_head_wr_g;
 
wire [4-1:0] dev_mondo_tail_wr_g;
 
wire [`TLU_THRD_NUM-1:0] dev_mondo_tail_wr_g;
 
wire [4-1:0] resum_err_head_wr_g;
 
wire [`TLU_THRD_NUM-1:0] resum_err_head_wr_g;
 
wire [4-1:0] resum_err_tail_wr_g;
 
wire [`TLU_THRD_NUM-1:0] resum_err_tail_wr_g;
 
wire [4-1:0] nresum_err_head_wr_g;
 
wire [`TLU_THRD_NUM-1:0] nresum_err_head_wr_g;
 
wire [4-1:0] nresum_err_tail_wr_g;
 
wire [`TLU_THRD_NUM-1:0] nresum_err_tail_wr_g;
 
// 
// 
// ASI va address
 
// ASI va address
 
// modified due to timing fix
 
// modified due to timing fix
 
// wire [`TLU_ASI_VA_WIDTH-1:0] tlu_ldst_va_e;
 
// wire [`TLU_ASI_VA_WIDTH-1:0] tlu_ldst_va_e;
 
wire [10-1:0] tlu_ldst_va_m;
 
wire [`TLU_ASI_VA_WIDTH-1:0] tlu_ldst_va_m;
 
//
 
//
 
// ASI read or write enables
 
// ASI read or write enables
 
wire asi_queue_write_e;
 
wire asi_queue_write_e;
 
wire asi_queue_read_e;
 
wire asi_queue_read_e;
 
wire asi_queue_write_pq_m;
 
wire asi_queue_write_pq_m;
Line 1164... Line 494... 
wire hscpd_va_rw_m;
 
wire hscpd_va_rw_m;
 
//
 
//
 
// relevant portion of the va address for the scratch-pad 
// relevant portion of the va address for the scratch-pad 
// modified due to timing fix
 
// modified due to timing fix
 
// wire [`TLU_ASI_SCPD_VA_HI:0]       scpd_addr_va_e;
 
// wire [`TLU_ASI_SCPD_VA_HI:0]       scpd_addr_va_e;
 
wire [3-1:0] scpd_addr_va_m;
 
wire [`SCPD_ASI_VA_ADDR_WIDTH-1:0] scpd_addr_va_m;
 
wire [3-1:0] scpd_addr_va_g;
 
wire [`SCPD_ASI_VA_ADDR_WIDTH-1:0] scpd_addr_va_g;
 
//
 
//
 
// load instruction data valid
 
// load instruction data valid
 
wire asi_ld_addr_vld_m, asi_ld_addr_vld_g;
 
wire asi_ld_addr_vld_m, asi_ld_addr_vld_g;
 
 
 
 
 
// privilege or hyper-privileged address indicators
 
// privilege or hyper-privileged address indicators
Line 1189... Line 519... 
    .din  (grst_l),
 
    .din  (grst_l),
 
    .clk  (clk),
 
    .clk  (clk),
 
    .rst_l(arst_l),
 
    .rst_l(arst_l),
 
    .q    (local_rst_l),
 
    .q    (local_rst_l),
 
    .se   (se),
 
    .se   (se),
 
    .si   (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so   ()
 
    .so   ()
 
);
 
);
 
 
 
 
 
assign local_rst = ~local_rst_l;
 
assign local_rst = ~local_rst_l;
 
 
 
 
Line 1223... Line 553... 
assign  thread_sel_id_e[0] = ~thrid_e[1] & ~thrid_e[0];
 
assign  thread_sel_id_e[0] = ~thrid_e[1] & ~thrid_e[0];
 
assign  thread_sel_id_e[1] = ~thrid_e[1] &  thrid_e[0];
 
assign  thread_sel_id_e[1] = ~thrid_e[1] &  thrid_e[0];
 
assign  thread_sel_id_e[2] =  thrid_e[1] & ~thrid_e[0];
 
assign  thread_sel_id_e[2] =  thrid_e[1] & ~thrid_e[0];
 
assign  thread_sel_id_e[3] =  thrid_e[1] &  thrid_e[0];
 
assign  thread_sel_id_e[3] =  thrid_e[1] &  thrid_e[0];
 
 
 
 
 
dff #(4) dff_thread_sel_id_m (
 
dff_s #(`TLU_THRD_NUM) dff_thread_sel_id_m (
 
    .din (thread_sel_id_e[4-1:0]),
 
    .din (thread_sel_id_e[`TLU_THRD_NUM-1:0]),
 
    .q   (thread_sel_id_m[4-1:0]),
 
    .q   (thread_sel_id_m[`TLU_THRD_NUM-1:0]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff #(4) dff_thread_id_sel_g (
 
dff_s #(`TLU_THRD_NUM) dff_thread_id_sel_g (
 
    .din (thread_sel_id_m[4-1:0]),
 
    .din (thread_sel_id_m[`TLU_THRD_NUM-1:0]),
 
    .q   (thread_sel_id_g[4-1:0]),
 
    .q   (thread_sel_id_g[`TLU_THRD_NUM-1:0]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff #(4) dff_thread_id_sel_w2 (
 
dff_s #(`TLU_THRD_NUM) dff_thread_id_sel_w2 (
 
    .din (thread_sel_id_g[4-1:0]),
 
    .din (thread_sel_id_g[`TLU_THRD_NUM-1:0]),
 
    .q   (thread_sel_id_w2[4-1:0]),
 
    .q   (thread_sel_id_w2[`TLU_THRD_NUM-1:0]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff #(2) dff_thrid_e (
 
dff_s #(2) dff_thrid_e (
 
    .din (ifu_tlu_thrid_d[1:0]),
 
    .din (ifu_tlu_thrid_d[1:0]),
 
    .q   (thrid_e[1:0]),
 
    .q   (thrid_e[1:0]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff #(2) dff_thrid_m (
 
dff_s #(2) dff_thrid_m (
 
    .din (thrid_e[1:0]),
 
    .din (thrid_e[1:0]),
 
    .q   (thrid_m[1:0]),
 
    .q   (thrid_m[1:0]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff #(2) dff_thrid_g (
 
dff_s #(2) dff_thrid_g (
 
    .din (thrid_m[1:0]),
 
    .din (thrid_m[1:0]),
 
    .q   (thrid_g[1:0]),
 
    .q   (thrid_g[1:0]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
//
 
//
 
// modified due to rte failure
 
// modified due to rte failure
 
assign tlu_local_thrid_g[0] = ~(|thrid_g[1:0]);
 
assign tlu_local_thrid_g[0] = ~(|thrid_g[1:0]);
Line 1313... Line 643... 
// flush signal - modified for timing
 
// flush signal - modified for timing
 
// assign  local_flush_all_w = tlu_nlsu_flush_w | lsu_tlu_early_flush_w;
 
// assign  local_flush_all_w = tlu_nlsu_flush_w | lsu_tlu_early_flush_w;
 
assign  local_flush_all_w =
 
assign  local_flush_all_w =
 
            tlu_local_flush_w | lsu_tlu_early_flush_w | ifu_tlu_flush_fd_w;
 
            tlu_local_flush_w | lsu_tlu_early_flush_w | ifu_tlu_flush_fd_w;
 
 
 
 
 
dffr dffr_local_flush_all_w2 (
 
dffr_s dffr_local_flush_all_w2 (
 
    .din (local_flush_all_w),
 
    .din (local_flush_all_w),
 
    .q   (local_flush_all_w2),
 
    .q   (local_flush_all_w2),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so ()
 
    .so ()
 
);
 
);
 
 
 
 
 
// added for timing
 
// added for timing
 
assign tlu_lsu_int_ldxa_vld_w2 =
 
assign tlu_lsu_int_ldxa_vld_w2 =
 
           tlu_asi_data_nf_vld_w2 & ~local_flush_all_w2;
 
           tlu_asi_data_nf_vld_w2 & ~local_flush_all_w2;
 
 
 
 
 
assign  asr_hyperp = ifu_tlu_sraddr_d[7-1];
 
assign  asr_hyperp = ifu_tlu_sraddr_d[`TLU_ASR_ADDR_WIDTH-1];
 
assign  asr_priv   = ifu_tlu_sraddr_d[7-2];
 
assign  asr_priv   = ifu_tlu_sraddr_d[`TLU_ASR_ADDR_WIDTH-2];
 
 
 
 
 
assign  sraddr[7-3:0]    =
 
assign  sraddr[`TLU_ASR_ADDR_WIDTH-3:0]  =
 
            ifu_tlu_sraddr_d[7-3:0];
 
            ifu_tlu_sraddr_d[`TLU_ASR_ADDR_WIDTH-3:0];
 
 
 
 
 
// hypervisor tick compare - 0x1f - hyper-priviledged
 
// hypervisor tick compare - 0x1f - hyper-priviledged
 
assign htickcmp_rw_d = sraddr[4] & sraddr[3] & sraddr[2] & sraddr[1] & sraddr[0] &
 
assign htickcmp_rw_d = sraddr[4] & sraddr[3] & sraddr[2] & sraddr[1] & sraddr[0] &
 
                                   asr_hyperp;
 
                                   asr_hyperp;
 
//
 
//
Line 1361... Line 691... 
assign gl_rw_d = sraddr[4] & ~sraddr[3] & ~sraddr[2] & ~sraddr[1] & ~sraddr[0] &
 
assign gl_rw_d = sraddr[4] & ~sraddr[3] & ~sraddr[2] & ~sraddr[1] & ~sraddr[0] &
 
                             asr_priv;
 
                             asr_priv;
 
//
 
//
 
// staging of the ASR decoded controls
 
// staging of the ASR decoded controls
 
// staging from d to e stage
 
// staging from d to e stage
 
dff dff_htba_rw_d_e (
 
dff_s dff_htba_rw_d_e (
 
    .din (htba_rw_d),
 
    .din (htba_rw_d),
 
    .q   (htba_rw_e),
 
    .q   (htba_rw_e),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_hpstate_rw_d_e (
 
dff_s dff_hpstate_rw_d_e (
 
    .din (hpstate_rw_d),
 
    .din (hpstate_rw_d),
 
    .q   (hpstate_rw_e),
 
    .q   (hpstate_rw_e),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_htstate_rw_d_e (
 
dff_s dff_htstate_rw_d_e (
 
    .din (htstate_rw_d),
 
    .din (htstate_rw_d),
 
    .q   (htstate_rw_e),
 
    .q   (htstate_rw_e),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_hintp_rw_e (
 
dff_s dff_hintp_rw_e (
 
    .din (hintp_rw_d),
 
    .din (hintp_rw_d),
 
    .q   (hintp_rw_e),
 
    .q   (hintp_rw_e),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_htickcmp_rw_d_e (
 
dff_s dff_htickcmp_rw_d_e (
 
    .din (htickcmp_rw_d),
 
    .din (htickcmp_rw_d),
 
    .q   (htickcmp_rw_e),
 
    .q   (htickcmp_rw_e),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_gl_rw_d_e (
 
dff_s dff_gl_rw_d_e (
 
    .din (gl_rw_d),
 
    .din (gl_rw_d),
 
    .q   (gl_rw_e),
 
    .q   (gl_rw_e),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
// staging from e to m stage
 
// staging from e to m stage
 
dff dff_htba_rw_m_m (
 
dff_s dff_htba_rw_m_m (
 
    .din (htba_rw_e),
 
    .din (htba_rw_e),
 
    .q   (htba_rw_m),
 
    .q   (htba_rw_m),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_hpstate_rw_m_m (
 
dff_s dff_hpstate_rw_m_m (
 
    .din (hpstate_rw_e),
 
    .din (hpstate_rw_e),
 
    .q   (hpstate_rw_m),
 
    .q   (hpstate_rw_m),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_htstate_rw_m_m (
 
dff_s dff_htstate_rw_m_m (
 
    .din (htstate_rw_e),
 
    .din (htstate_rw_e),
 
    .q   (htstate_rw_m),
 
    .q   (htstate_rw_m),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_hintp_rw_m_m (
 
dff_s dff_hintp_rw_m_m (
 
    .din (hintp_rw_e),
 
    .din (hintp_rw_e),
 
    .q   (hintp_rw_m),
 
    .q   (hintp_rw_m),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_htickcmp_rw_m_m (
 
dff_s dff_htickcmp_rw_m_m (
 
    .din (htickcmp_rw_e),
 
    .din (htickcmp_rw_e),
 
    .q   (htickcmp_rw_m),
 
    .q   (htickcmp_rw_m),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_gl_rw_m_m (
 
dff_s dff_gl_rw_m_m (
 
    .din (gl_rw_e),
 
    .din (gl_rw_e),
 
    .q   (gl_rw_m),
 
    .q   (gl_rw_m),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
// staging from e to g stage
 
// staging from e to g stage
 
dff dff_gl_rw_m_g (
 
dff_s dff_gl_rw_m_g (
 
    .din (gl_rw_m),
 
    .din (gl_rw_m),
 
    .q   (gl_rw_g),
 
    .q   (gl_rw_g),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_hpstate_rw_m_g (
 
dff_s dff_hpstate_rw_m_g (
 
    .din (hpstate_rw_m),
 
    .din (hpstate_rw_m),
 
    .q   (hpstate_rw_g),
 
    .q   (hpstate_rw_g),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_htickcmp_rw_m_g (
 
dff_s dff_htickcmp_rw_m_g (
 
    .din (htickcmp_rw_m),
 
    .din (htickcmp_rw_m),
 
    .q   (htickcmp_rw_g),
 
    .q   (htickcmp_rw_g),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_htba_rw_m_g (
 
dff_s dff_htba_rw_m_g (
 
    .din (htba_rw_m),
 
    .din (htba_rw_m),
 
    .q   (htba_rw_g),
 
    .q   (htba_rw_g),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_hintp_rw_g (
 
dff_s dff_hintp_rw_g (
 
    .din (hintp_rw_m),
 
    .din (hintp_rw_m),
 
    .q   (hintp_rw_g),
 
    .q   (hintp_rw_g),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_htstate_rw_m_g (
 
dff_s dff_htstate_rw_m_g (
 
    .din (htstate_rw_m),
 
    .din (htstate_rw_m),
 
    .q   (htstate_rw_g),
 
    .q   (htstate_rw_g),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
//
 
//
 
// stage to w2
 
// stage to w2
 
dff dff_hpstate_rw_m_w2 (
 
dff_s dff_hpstate_rw_m_w2 (
 
    .din (hpstate_rw_g),
 
    .din (hpstate_rw_g),
 
    .q   (hpstate_rw_w2),
 
    .q   (hpstate_rw_w2),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
// constructing the mux select to access the 
// constructing the mux select to access the 
// hyper-privileged ASR registers
 
// hyper-privileged ASR registers
Line 1563... Line 893... 
 
 
 
 
////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////
 
// GL register controls 
// GL register controls 
////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////
 
 
 
 
 
dffr #(4)  dffr_gl_update_sel_w2 (
 
dffr_s #(`TLU_THRD_NUM)  dffr_gl_update_sel_w2 (
 
    .din (gl_update_sel_g[4-1:0]),
 
    .din (gl_update_sel_g[`TLU_THRD_NUM-1:0]),
 
    .q   (gl_update_sel_w2[4-1:0]),
 
    .q   (gl_update_sel_w2[`TLU_THRD_NUM-1:0]),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so ()
 
    .so ()
 
);
 
);
 
 
 
 
 
dffr #(4) dffr_dnrtry_inst_w2 (
 
dffr_s #(`TLU_THRD_NUM) dffr_dnrtry_inst_w2 (
 
    .din ({tlu_dnrtry3_inst_g, tlu_dnrtry2_inst_g,
 
    .din ({tlu_dnrtry3_inst_g, tlu_dnrtry2_inst_g,
 
           tlu_dnrtry1_inst_g,tlu_dnrtry0_inst_g}),
 
           tlu_dnrtry1_inst_g,tlu_dnrtry0_inst_g}),
 
    .q   (dnrtry_inst_w2[4-1:0]),
 
    .q   (dnrtry_inst_w2[`TLU_THRD_NUM-1:0]),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so ()
 
    .so ()
 
);
 
);
 
//
 
//
 
// added for timing 
// added for timing 
assign wsr_inst_g = tlu_wsr_inst_nq_g & ~ifu_tlu_flush_fd_w;
 
assign wsr_inst_g = tlu_wsr_inst_nq_g & ~ifu_tlu_flush_fd_w;
 
 
 
 
 
dffr dffr_wsr_inst_w2 (
 
dffr_s dffr_wsr_inst_w2 (
 
    .din (wsr_inst_g),
 
    .din (wsr_inst_g),
 
    .q   (wsr_inst_w2),
 
    .q   (wsr_inst_w2),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so ()
 
    .so ()
 
);
 
);
 
 
 
 
 
// THREAD0
 
// THREAD0
 
 
 
 
 
assign gl_lvl0_at_maxgl  = (gl_lvl0[2-1:0] == 2'b11);
 
assign gl_lvl0_at_maxgl  = (gl_lvl0[`TSA_GLOBAL_WIDTH-1:0] == `MAXGL_GL);
 
assign gl_lvl0_at_maxstl = (gl_lvl0[2-1:0] == 2'b10);
 
assign gl_lvl0_at_maxstl = (gl_lvl0[`TSA_GLOBAL_WIDTH-1:0] == `MAXSTL_GL);
 
// 
// 
// generate the control to prevent writing beyond maxstl or maxgl
 
// generate the control to prevent writing beyond maxstl or maxgl
 
 
 
 
 
assign maxstl_gl_wr_sel[0] =
 
assign maxstl_gl_wr_sel[0] =
 
           ~tlu_hyper_lite[0] &
 
           ~tlu_hyper_lite[0] &
 
           (tlu_wsr_data_w_global[4-1:0] > {1'b0,3'b010});
 
           (tlu_wsr_data_w_global[`TLU_GLOBAL_WIDTH-1:0] > {1'b0,`MAXSTL});
 
assign maxstl_gl_wr_sel[1] =
 
assign maxstl_gl_wr_sel[1] =
 
           ~tlu_hyper_lite[1] &
 
           ~tlu_hyper_lite[1] &
 
           (tlu_wsr_data_w_global[4-1:0] > {1'b0,3'b010});
 
           (tlu_wsr_data_w_global[`TLU_GLOBAL_WIDTH-1:0] > {1'b0,`MAXSTL});
 
assign maxstl_gl_wr_sel[2] =
 
assign maxstl_gl_wr_sel[2] =
 
           ~tlu_hyper_lite[2] &
 
           ~tlu_hyper_lite[2] &
 
           (tlu_wsr_data_w_global[4-1:0] > {1'b0,3'b010});
 
           (tlu_wsr_data_w_global[`TLU_GLOBAL_WIDTH-1:0] > {1'b0,`MAXSTL});
 
assign maxstl_gl_wr_sel[3] =
 
assign maxstl_gl_wr_sel[3] =
 
           ~tlu_hyper_lite[3] &
 
           ~tlu_hyper_lite[3] &
 
           (tlu_wsr_data_w_global[4-1:0] > {1'b0,3'b010});
 
           (tlu_wsr_data_w_global[`TLU_GLOBAL_WIDTH-1:0] > {1'b0,`MAXSTL});
 
//
 
//
 
// added for bug 79252 
// added for bug 79252 
assign maxstl_gl_dnrtry_sel[0] =
 
assign maxstl_gl_dnrtry_sel[0] =
 
           ~tlu_hyper_lite[0] &
 
           ~tlu_hyper_lite[0] &
 
           (&tlu_dnrtry_global_g[2-1:0]);
 
           (&tlu_dnrtry_global_g[`TSA_GLOBAL_WIDTH-1:0]);
 
assign maxstl_gl_dnrtry_sel[1] =
 
assign maxstl_gl_dnrtry_sel[1] =
 
           ~tlu_hyper_lite[1] &
 
           ~tlu_hyper_lite[1] &
 
           (&tlu_dnrtry_global_g[2-1:0]);
 
           (&tlu_dnrtry_global_g[`TSA_GLOBAL_WIDTH-1:0]);
 
assign maxstl_gl_dnrtry_sel[2] =
 
assign maxstl_gl_dnrtry_sel[2] =
 
           ~tlu_hyper_lite[2] &
 
           ~tlu_hyper_lite[2] &
 
           (&tlu_dnrtry_global_g[2-1:0]);
 
           (&tlu_dnrtry_global_g[`TSA_GLOBAL_WIDTH-1:0]);
 
assign maxstl_gl_dnrtry_sel[3] =
 
assign maxstl_gl_dnrtry_sel[3] =
 
           ~tlu_hyper_lite[3] &
 
           ~tlu_hyper_lite[3] &
 
           (&tlu_dnrtry_global_g[2-1:0]);
 
           (&tlu_dnrtry_global_g[`TSA_GLOBAL_WIDTH-1:0]);
 
//
 
//
 
// added for bug 79252
 
// added for bug 79252
 
assign dnrtry_gl_lvl0_data[2-1:0] =
 
assign dnrtry_gl_lvl0_data[`TSA_GLOBAL_WIDTH-1:0] =
 
            (maxstl_gl_dnrtry_sel[0])? 2'b10:
 
            (maxstl_gl_dnrtry_sel[0])? `MAXSTL_GL:
 
            tlu_dnrtry_global_g[2-1:0];
 
            tlu_dnrtry_global_g[`TSA_GLOBAL_WIDTH-1:0];
 
assign dnrtry_gl_lvl1_data[2-1:0] =
 
assign dnrtry_gl_lvl1_data[`TSA_GLOBAL_WIDTH-1:0] =
 
            (maxstl_gl_dnrtry_sel[1])? 2'b10:
 
            (maxstl_gl_dnrtry_sel[1])? `MAXSTL_GL:
 
            tlu_dnrtry_global_g[2-1:0];
 
            tlu_dnrtry_global_g[`TSA_GLOBAL_WIDTH-1:0];
 
assign dnrtry_gl_lvl2_data[2-1:0] =
 
assign dnrtry_gl_lvl2_data[`TSA_GLOBAL_WIDTH-1:0] =
 
            (maxstl_gl_dnrtry_sel[2])? 2'b10:
 
            (maxstl_gl_dnrtry_sel[2])? `MAXSTL_GL:
 
            tlu_dnrtry_global_g[2-1:0];
 
            tlu_dnrtry_global_g[`TSA_GLOBAL_WIDTH-1:0];
 
assign dnrtry_gl_lvl3_data[2-1:0] =
 
assign dnrtry_gl_lvl3_data[`TSA_GLOBAL_WIDTH-1:0] =
 
            (maxstl_gl_dnrtry_sel[3])? 2'b10:
 
            (maxstl_gl_dnrtry_sel[3])? `MAXSTL_GL:
 
            tlu_dnrtry_global_g[2-1:0];
 
            tlu_dnrtry_global_g[`TSA_GLOBAL_WIDTH-1:0];
 
 
 
 
 
// 
// 
// maxgl cap
 
// maxgl cap
 
assign maxgl_gl_wr_sel[0] =
 
assign maxgl_gl_wr_sel[0] =
 
           tlu_hyper_lite[0] &
 
           tlu_hyper_lite[0] &
 
           (tlu_wsr_data_w_global[4-1:0] > 4'b0011);
 
           (tlu_wsr_data_w_global[`TLU_GLOBAL_WIDTH-1:0] > `MAXGL);
 
assign maxgl_gl_wr_sel[1] =
 
assign maxgl_gl_wr_sel[1] =
 
           tlu_hyper_lite[1] &
 
           tlu_hyper_lite[1] &
 
           (tlu_wsr_data_w_global[4-1:0] > 4'b0011);
 
           (tlu_wsr_data_w_global[`TLU_GLOBAL_WIDTH-1:0] > `MAXGL);
 
assign maxgl_gl_wr_sel[2] =
 
assign maxgl_gl_wr_sel[2] =
 
           tlu_hyper_lite[2] &
 
           tlu_hyper_lite[2] &
 
           (tlu_wsr_data_w_global[4-1:0] > 4'b0011);
 
           (tlu_wsr_data_w_global[`TLU_GLOBAL_WIDTH-1:0] > `MAXGL);
 
assign maxgl_gl_wr_sel[3] =
 
assign maxgl_gl_wr_sel[3] =
 
           tlu_hyper_lite[3] &
 
           tlu_hyper_lite[3] &
 
           (tlu_wsr_data_w_global[4-1:0] > 4'b0011);
 
           (tlu_wsr_data_w_global[`TLU_GLOBAL_WIDTH-1:0] > `MAXGL);
 
//
 
//
 
// trap level to be incremented if thread not at MAXGL and not in redmode
 
// trap level to be incremented if thread not at MAXGL and not in redmode
 
// modified for bug 2889
 
// modified for bug 2889
 
// modified due to timing
 
// modified due to timing
 
/*
 
/*
Line 1683... Line 1013... 
                   ((tlu_dnrtry0_inst_g) ?
 
                   ((tlu_dnrtry0_inst_g) ?
 
                         tlu_dnrtry_global_g[`TSA_GLOBAL_WIDTH-1:0] :     // done/retry restore
 
                         tlu_dnrtry_global_g[`TSA_GLOBAL_WIDTH-1:0] :     // done/retry restore
 
                         gl_lvl0[`TSA_GLOBAL_WIDTH-1:0] + gl_lvl0_incr[1:0])); // trap increments
 
                         gl_lvl0[`TSA_GLOBAL_WIDTH-1:0] + gl_lvl0_incr[1:0])); // trap increments
 
*/
 
*/
 
// modified for bug 79252 
// modified for bug 79252 
assign wsr_gl_lvl0_data[2-1:0] =
 
assign wsr_gl_lvl0_data[`TSA_GLOBAL_WIDTH-1:0] =
 
            (maxstl_gl_wr_sel[0])? 2'b10:
 
            (maxstl_gl_wr_sel[0])? `MAXSTL_GL:
 
           ((maxgl_gl_wr_sel[0]) ? 2'b11 :
 
           ((maxgl_gl_wr_sel[0]) ? `MAXGL_GL :
 
            tlu_wsr_data_w_global[2-1:0]);
 
            tlu_wsr_data_w_global[`TSA_GLOBAL_WIDTH-1:0]);
 
assign gl_lvl0_update_g[2-1:0] =
 
assign gl_lvl0_update_g[`TSA_GLOBAL_WIDTH-1:0] =
 
                (gl_rw_g & wsr_inst_g & thread_sel_id_g[0]) ?
 
                (gl_rw_g & wsr_inst_g & thread_sel_id_g[0]) ?
 
                         wsr_gl_lvl0_data[2-1:0] :
 
                         wsr_gl_lvl0_data[`TSA_GLOBAL_WIDTH-1:0] :
 
               ((local_rst | por_rstint0_g) ? 2'b11 :
 
               ((local_rst | por_rstint0_g) ? `MAXGL_GL :
 
                         dnrtry_gl_lvl0_data[2-1:0]);     // done/retry restore
 
                         dnrtry_gl_lvl0_data[`TSA_GLOBAL_WIDTH-1:0]);     // done/retry restore
 
                         // tlu_dnrtry_global_g[`TSA_GLOBAL_WIDTH-1:0]);     // done/retry restore
 
                         // tlu_dnrtry_global_g[`TSA_GLOBAL_WIDTH-1:0]);     // done/retry restore
 
 
 
 
 
dffe #(2) dffe_gl_lvl0_update_w2 (
 
dffe_s #(`TSA_GLOBAL_WIDTH) dffe_gl_lvl0_update_w2 (
 
     .din (gl_lvl0_update_g[2-1:0]),
 
     .din (gl_lvl0_update_g[`TSA_GLOBAL_WIDTH-1:0]),
 
     .q   (gl_lvl0_update_w2[2-1:0]),
 
     .q   (gl_lvl0_update_w2[`TSA_GLOBAL_WIDTH-1:0]),
 
     .en  (gl_update_sel_g[0]),
 
     .en  (gl_update_sel_g[0]),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
//
 
//
 
// modified for bug3468 and bug3505
 
// modified for bug3468 and bug3505
 
assign gl_incr_sel_w2[0] =
 
assign gl_incr_sel_w2[0] =
Line 1720... Line 1050... 
           (gl_lvl0_at_maxgl & tlu_select_tba_w2) & tlu_thrd_traps_w2[0];
 
           (gl_lvl0_at_maxgl & tlu_select_tba_w2) & tlu_thrd_traps_w2[0];
 
assign gl0_en =
 
assign gl0_en =
 
           gl_incr_sel_w2[0] | gl_update_sel_w2[0] | gl_priv_max_sel_w2[0];
 
           gl_incr_sel_w2[0] | gl_update_sel_w2[0] | gl_priv_max_sel_w2[0];
 
// assign gl0_en = gl_incr_sel_w2[0] | gl_update_sel_w2[0]; 
// assign gl0_en = gl_incr_sel_w2[0] | gl_update_sel_w2[0]; 
 
 
 
 
assign gl_lvl0_new[2-1:0] =
 
assign gl_lvl0_new[`TSA_GLOBAL_WIDTH-1:0] =
 
           (gl_update_sel_w2[0]) ? gl_lvl0_update_w2:
 
           (gl_update_sel_w2[0]) ? gl_lvl0_update_w2:
 
           (~gl_update_sel_w2[0] & gl_priv_max_sel_w2[0]) ?
 
           (~gl_update_sel_w2[0] & gl_priv_max_sel_w2[0]) ?
 
            2'b10:
 
            `MAXSTL_GL:
 
            gl_lvl0[2-1:0] + 2'b01;
 
            gl_lvl0[`TSA_GLOBAL_WIDTH-1:0] + 2'b01;
 
 
 
 
 
// Reset required as processor will start out at gl=1 after reset.
 
// Reset required as processor will start out at gl=1 after reset.
 
/****************************
 
/****************************
 
   to fix bug 6028 manually in the gate netlist, the following needs
 
   to fix bug 6028 manually in the gate netlist, the following needs
 
   to be a mux_flop with recirculating path from q to d0 input. But
 
   to be a mux_flop with recirculating path from q to d0 input. But
 
   to make it resetable, need to brake this recirculating path and
 
   to make it resetable, need to brake this recirculating path and
 
   insert an AND gate such that local_rst_l is ANDed with the q output.
 
   insert an AND gate such that local_rst_l is ANDed with the q output.
 
 
 
 
 
dffe #(`TSA_GLOBAL_WIDTH) dffe_gl0 (
 
dffe_s #(`TSA_GLOBAL_WIDTH) dffe_gl0 (
 
     .din (gl_lvl0_new[`TSA_GLOBAL_WIDTH-1:0]),
 
     .din (gl_lvl0_new[`TSA_GLOBAL_WIDTH-1:0]),
 
     .q   (gl_lvl0[`TSA_GLOBAL_WIDTH-1:0]),
 
     .q   (gl_lvl0[`TSA_GLOBAL_WIDTH-1:0]),
 
     .en  (gl0_en),
 
     .en  (gl0_en),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
******************************/
 
******************************/
 
 
 
 
 
wire [1:0] gl_lvl0_or_rst, gl_lvl0_or_rst_or_new;
 
wire [1:0] gl_lvl0_or_rst, gl_lvl0_or_rst_or_new;
 
 
 
 
 
assign gl_lvl0_or_rst[1:0] = gl_lvl0[1:0] & {2{~local_rst}};
 
assign gl_lvl0_or_rst[1:0] = gl_lvl0[1:0] & {2{~local_rst}};
 
 
 
 
 
assign gl_lvl0_or_rst_or_new[1:0] = (gl0_en&~local_rst) ? gl_lvl0_new[1:0] : gl_lvl0_or_rst[1:0];
 
assign gl_lvl0_or_rst_or_new[1:0] = (gl0_en&~local_rst) ? gl_lvl0_new[1:0] : gl_lvl0_or_rst[1:0];
 
 
 
 
 
dff    #(2) dffe_gl0 (
 
dff_s    #(2) dffe_gl0 (
 
        .din(gl_lvl0_or_rst_or_new[1:0]) ,
 
        .din(gl_lvl0_or_rst_or_new[1:0]) ,
 
        .q(gl_lvl0[1:0]),
 
        .q(gl_lvl0[1:0]),
 
        .clk (clk), .se(se), .si(), .so());
 
        .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
 
 
 
 
 
/******************************/
 
/******************************/
 
 
 
 
 
 
 
 
 
assign tlu_gl_lvl0[2-1:0] = gl_lvl0[2-1:0];
 
assign tlu_gl_lvl0[`TSA_GLOBAL_WIDTH-1:0] = gl_lvl0[`TSA_GLOBAL_WIDTH-1:0];
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
`ifdef FPGA_SYN_1THREAD
 
 
 
`else
 
 
 
 
 
// THREAD1
 
// THREAD1
 
 
 
 
 
assign gl_lvl1_at_maxgl  = (gl_lvl1[2-1:0] == 2'b11);
 
assign gl_lvl1_at_maxgl  = (gl_lvl1[`TSA_GLOBAL_WIDTH-1:0] == `MAXGL_GL);
 
assign gl_lvl1_at_maxstl = (gl_lvl1[2-1:0] == 2'b10);
 
assign gl_lvl1_at_maxstl = (gl_lvl1[`TSA_GLOBAL_WIDTH-1:0] == `MAXSTL_GL);
 
//
 
//
 
// trap level to be incremented if thread not at MAXGL and not in redmode
 
// trap level to be incremented if thread not at MAXGL and not in redmode
 
// modified for bug 2889
 
// modified for bug 2889
 
// modified due to timing 
// modified due to timing 
/*
 
/*
Line 1792... Line 1122... 
                         dnrtry_gl_lvl1_data[`TSA_GLOBAL_WIDTH-1:0] :     // done/retry restore
 
                         dnrtry_gl_lvl1_data[`TSA_GLOBAL_WIDTH-1:0] :     // done/retry restore
 
                         // tlu_dnrtry_global_g[`TSA_GLOBAL_WIDTH-1:0] :     // done/retry restore
 
                         // tlu_dnrtry_global_g[`TSA_GLOBAL_WIDTH-1:0] :     // done/retry restore
 
                         gl_lvl1[`TSA_GLOBAL_WIDTH-1:0] + gl_lvl1_incr[1:0])); // trap increments
 
                         gl_lvl1[`TSA_GLOBAL_WIDTH-1:0] + gl_lvl1_incr[1:0])); // trap increments
 
 
 
 
 
*/
 
*/
 
assign wsr_gl_lvl1_data[2-1:0] =
 
assign wsr_gl_lvl1_data[`TSA_GLOBAL_WIDTH-1:0] =
 
            (maxstl_gl_wr_sel[1])? 2'b10:
 
            (maxstl_gl_wr_sel[1])? `MAXSTL_GL:
 
           ((maxgl_gl_wr_sel[1]) ? 2'b11 :
 
           ((maxgl_gl_wr_sel[1]) ? `MAXGL_GL :
 
            tlu_wsr_data_w_global[2-1:0]);
 
            tlu_wsr_data_w_global[`TSA_GLOBAL_WIDTH-1:0]);
 
assign gl_lvl1_update_g[2-1:0] =
 
assign gl_lvl1_update_g[`TSA_GLOBAL_WIDTH-1:0] =
 
                (gl_rw_g & wsr_inst_g & thread_sel_id_g[1]) ?
 
                (gl_rw_g & wsr_inst_g & thread_sel_id_g[1]) ?
 
                         wsr_gl_lvl1_data[2-1:0] :
 
                         wsr_gl_lvl1_data[`TSA_GLOBAL_WIDTH-1:0] :
 
               ((local_rst | por_rstint1_g) ? 2'b11 :
 
               ((local_rst | por_rstint1_g) ? `MAXGL_GL :
 
                         dnrtry_gl_lvl1_data[2-1:0]);     // done/retry restore
 
                         dnrtry_gl_lvl1_data[`TSA_GLOBAL_WIDTH-1:0]);     // done/retry restore
 
                         // tlu_dnrtry_global_g[`TSA_GLOBAL_WIDTH-1:0]);     // done/retry restore
 
                         // tlu_dnrtry_global_g[`TSA_GLOBAL_WIDTH-1:0]);     // done/retry restore
 
 
 
 
 
dffe #(2) dffe_gl_lvl1_update_w2 (
 
dffe_s #(`TSA_GLOBAL_WIDTH) dffe_gl_lvl1_update_w2 (
 
     .din (gl_lvl1_update_g[2-1:0]),
 
     .din (gl_lvl1_update_g[`TSA_GLOBAL_WIDTH-1:0]),
 
     .q   (gl_lvl1_update_w2[2-1:0]),
 
     .q   (gl_lvl1_update_w2[`TSA_GLOBAL_WIDTH-1:0]),
 
     .en  (gl_update_sel_g[1]),
 
     .en  (gl_update_sel_g[1]),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
//
 
//
 
// modified for bug3468 and bug3505
 
// modified for bug3468 and bug3505
 
assign gl_incr_sel_w2[1] =
 
assign gl_incr_sel_w2[1] =
Line 1830... Line 1160... 
// 
// 
assign gl1_en =
 
assign gl1_en =
 
           gl_incr_sel_w2[1] | gl_update_sel_w2[1] | gl_priv_max_sel_w2[1];
 
           gl_incr_sel_w2[1] | gl_update_sel_w2[1] | gl_priv_max_sel_w2[1];
 
// assign gl1_en = gl_incr_sel_w2[1] | gl_update_sel_w2[1]; 
// assign gl1_en = gl_incr_sel_w2[1] | gl_update_sel_w2[1]; 
 
 
 
 
assign gl_lvl1_new[2-1:0] =
 
assign gl_lvl1_new[`TSA_GLOBAL_WIDTH-1:0] =
 
           (gl_update_sel_w2[1]) ? gl_lvl1_update_w2:
 
           (gl_update_sel_w2[1]) ? gl_lvl1_update_w2:
 
           (~gl_update_sel_w2[1] & gl_priv_max_sel_w2[1]) ?
 
           (~gl_update_sel_w2[1] & gl_priv_max_sel_w2[1]) ?
 
            2'b10:
 
            `MAXSTL_GL:
 
            gl_lvl1[2-1:0] + 2'b01;
 
            gl_lvl1[`TSA_GLOBAL_WIDTH-1:0] + 2'b01;
 
 
 
 
 
// Reset required as processor will start out at gl=1 after reset.
 
// Reset required as processor will start out at gl=1 after reset.
 
/****************************
 
/****************************
 
   to fix bug 6028 manually in the gate netlist, the following needs
 
   to fix bug 6028 manually in the gate netlist, the following needs
 
   to be a mux_flop with recirculating path from q to d0 input. But
 
   to be a mux_flop with recirculating path from q to d0 input. But
 
   to make it resetable, need to brake this recirculating path and
 
   to make it resetable, need to brake this recirculating path and
 
   insert an AND gate such that local_rst_l is ANDed with the q output.
 
   insert an AND gate such that local_rst_l is ANDed with the q output.
 
dffe #(`TSA_GLOBAL_WIDTH) dffe_gl1 (
 
dffe_s #(`TSA_GLOBAL_WIDTH) dffe_gl1 (
 
     .din (gl_lvl1_new[`TSA_GLOBAL_WIDTH-1:0]),
 
     .din (gl_lvl1_new[`TSA_GLOBAL_WIDTH-1:0]),
 
     .q   (gl_lvl1[`TSA_GLOBAL_WIDTH-1:0]),
 
     .q   (gl_lvl1[`TSA_GLOBAL_WIDTH-1:0]),
 
     .en  (gl1_en),
 
     .en  (gl1_en),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
******************************/
 
******************************/
 
 
 
 
 
wire [1:0] gl_lvl1_or_rst, gl_lvl1_or_rst_or_new;
 
wire [1:0] gl_lvl1_or_rst, gl_lvl1_or_rst_or_new;
 
 
 
 
 
assign gl_lvl1_or_rst[1:0] = gl_lvl1[1:0] & {2{~local_rst}};
 
assign gl_lvl1_or_rst[1:0] = gl_lvl1[1:0] & {2{~local_rst}};
 
 
 
 
 
assign gl_lvl1_or_rst_or_new[1:0] = (gl1_en&~local_rst) ? gl_lvl1_new[1:0] : gl_lvl1_or_rst[1:0];
 
assign gl_lvl1_or_rst_or_new[1:0] = (gl1_en&~local_rst) ? gl_lvl1_new[1:0] : gl_lvl1_or_rst[1:0];
 
 
 
 
 
dff    #(2) dffe_gl1 (
 
dff_s    #(2) dffe_gl1 (
 
        .din(gl_lvl1_or_rst_or_new[1:0]) ,
 
        .din(gl_lvl1_or_rst_or_new[1:0]) ,
 
        .q(gl_lvl1[1:0]),
 
        .q(gl_lvl1[1:0]),
 
        .clk (clk), .se(se), .si(), .so());
 
        .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
 
 
 
 
 
/******************************/
 
/******************************/
 
 
 
 
 
 
 
 
 
assign tlu_gl_lvl1[2-1:0] = gl_lvl1[2-1:0];
 
assign tlu_gl_lvl1[`TSA_GLOBAL_WIDTH-1:0] = gl_lvl1[`TSA_GLOBAL_WIDTH-1:0];
 
 
 
 
 
// THREAD2
 
// THREAD2
 
 
 
 
 
assign gl_lvl2_at_maxgl  = (gl_lvl2[2-1:0] == 2'b11);
 
assign gl_lvl2_at_maxgl  = (gl_lvl2[`TSA_GLOBAL_WIDTH-1:0] == `MAXGL_GL);
 
assign gl_lvl2_at_maxstl = (gl_lvl2[2-1:0] == 2'b10);
 
assign gl_lvl2_at_maxstl = (gl_lvl2[`TSA_GLOBAL_WIDTH-1:0] == `MAXSTL_GL);
 
//
 
//
 
// trap level to be incremented if thread not at MAXGL and not in redmode
 
// trap level to be incremented if thread not at MAXGL and not in redmode
 
// modified for bug 2889
 
// modified for bug 2889
 
// modified due to timing
 
// modified due to timing
 
/*
 
/*
Line 1896... Line 1226... 
                   ((local_rst | por_rstint2_g) ? `MAXGL_GL :
 
                   ((local_rst | por_rstint2_g) ? `MAXGL_GL :
 
                   ((tlu_dnrtry2_inst_g) ?
 
                   ((tlu_dnrtry2_inst_g) ?
 
                         tlu_dnrtry_global_g[`TSA_GLOBAL_WIDTH-1:0] :     // done/retry restore
 
                         tlu_dnrtry_global_g[`TSA_GLOBAL_WIDTH-1:0] :     // done/retry restore
 
                         gl_lvl2[`TSA_GLOBAL_WIDTH-1:0] + gl_lvl2_incr[1:0])); // trap increments
 
                         gl_lvl2[`TSA_GLOBAL_WIDTH-1:0] + gl_lvl2_incr[1:0])); // trap increments
 
*/
 
*/
 
assign wsr_gl_lvl2_data[2-1:0] =
 
assign wsr_gl_lvl2_data[`TSA_GLOBAL_WIDTH-1:0] =
 
            (maxstl_gl_wr_sel[2])? 2'b10:
 
            (maxstl_gl_wr_sel[2])? `MAXSTL_GL:
 
           ((maxgl_gl_wr_sel[2]) ? 2'b11 :
 
           ((maxgl_gl_wr_sel[2]) ? `MAXGL_GL :
 
            tlu_wsr_data_w_global[2-1:0]);
 
            tlu_wsr_data_w_global[`TSA_GLOBAL_WIDTH-1:0]);
 
assign gl_lvl2_update_g[2-1:0] =
 
assign gl_lvl2_update_g[`TSA_GLOBAL_WIDTH-1:0] =
 
                (gl_rw_g & wsr_inst_g & thread_sel_id_g[2]) ?
 
                (gl_rw_g & wsr_inst_g & thread_sel_id_g[2]) ?
 
                         wsr_gl_lvl2_data[2-1:0] :
 
                         wsr_gl_lvl2_data[`TSA_GLOBAL_WIDTH-1:0] :
 
               ((local_rst | por_rstint2_g) ? 2'b11 :
 
               ((local_rst | por_rstint2_g) ? `MAXGL_GL :
 
                         dnrtry_gl_lvl2_data[2-1:0]);     // done/retry restore
 
                         dnrtry_gl_lvl2_data[`TSA_GLOBAL_WIDTH-1:0]);     // done/retry restore
 
                         // tlu_dnrtry_global_g[`TSA_GLOBAL_WIDTH-1:0]);     // done/retry restore
 
                         // tlu_dnrtry_global_g[`TSA_GLOBAL_WIDTH-1:0]);     // done/retry restore
 
 
 
 
 
dffe #(2) dffe_gl_lvl2_update_w2 (
 
dffe_s #(`TSA_GLOBAL_WIDTH) dffe_gl_lvl2_update_w2 (
 
     .din (gl_lvl2_update_g[2-1:0]),
 
     .din (gl_lvl2_update_g[`TSA_GLOBAL_WIDTH-1:0]),
 
     .q   (gl_lvl2_update_w2[2-1:0]),
 
     .q   (gl_lvl2_update_w2[`TSA_GLOBAL_WIDTH-1:0]),
 
     .en  (gl_update_sel_g[2]),
 
     .en  (gl_update_sel_g[2]),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
//
 
//
 
// modified for bug3468 and bug3505
 
// modified for bug3468 and bug3505
 
assign gl_incr_sel_w2[2] =
 
assign gl_incr_sel_w2[2] =
Line 1934... Line 1264... 
//
 
//
 
assign gl2_en =
 
assign gl2_en =
 
           gl_incr_sel_w2[2] | gl_update_sel_w2[2] | gl_priv_max_sel_w2[2];
 
           gl_incr_sel_w2[2] | gl_update_sel_w2[2] | gl_priv_max_sel_w2[2];
 
// assign gl2_en = gl_incr_sel_w2[2] | gl_update_sel_w2[2]; 
// assign gl2_en = gl_incr_sel_w2[2] | gl_update_sel_w2[2]; 
 
 
 
 
assign gl_lvl2_new[2-1:0] =
 
assign gl_lvl2_new[`TSA_GLOBAL_WIDTH-1:0] =
 
           (gl_update_sel_w2[2]) ? gl_lvl2_update_w2:
 
           (gl_update_sel_w2[2]) ? gl_lvl2_update_w2:
 
           (~gl_update_sel_w2[2] & gl_priv_max_sel_w2[2]) ?
 
           (~gl_update_sel_w2[2] & gl_priv_max_sel_w2[2]) ?
 
            2'b10:
 
            `MAXSTL_GL:
 
            gl_lvl2[2-1:0] + 2'b01;
 
            gl_lvl2[`TSA_GLOBAL_WIDTH-1:0] + 2'b01;
 
 
 
 
 
// Reset required as processor will start out at gl=1 after reset.
 
// Reset required as processor will start out at gl=1 after reset.
 
/****************************
 
/****************************
 
   to fix bug 6028 manually in the gate netlist, the following needs
 
   to fix bug 6028 manually in the gate netlist, the following needs
 
   to be a mux_flop with recirculating path from q to d0 input. But
 
   to be a mux_flop with recirculating path from q to d0 input. But
 
   to make it resetable, need to brake this recirculating path and
 
   to make it resetable, need to brake this recirculating path and
 
   insert an AND gate such that local_rst_l is ANDed with the q output.
 
   insert an AND gate such that local_rst_l is ANDed with the q output.
 
dffe #(`TSA_GLOBAL_WIDTH) dffe_gl2 (
 
dffe_s #(`TSA_GLOBAL_WIDTH) dffe_gl2 (
 
     .din (gl_lvl2_new[`TSA_GLOBAL_WIDTH-1:0]),
 
     .din (gl_lvl2_new[`TSA_GLOBAL_WIDTH-1:0]),
 
     .q   (gl_lvl2[`TSA_GLOBAL_WIDTH-1:0]),
 
     .q   (gl_lvl2[`TSA_GLOBAL_WIDTH-1:0]),
 
     .en  (gl2_en),
 
     .en  (gl2_en),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
******************************/
 
******************************/
 
 
 
 
 
wire [1:0] gl_lvl2_or_rst, gl_lvl2_or_rst_or_new;
 
wire [1:0] gl_lvl2_or_rst, gl_lvl2_or_rst_or_new;
 
 
 
 
 
assign gl_lvl2_or_rst[1:0] = gl_lvl2[1:0] & {2{~local_rst}};
 
assign gl_lvl2_or_rst[1:0] = gl_lvl2[1:0] & {2{~local_rst}};
 
 
 
 
 
assign gl_lvl2_or_rst_or_new[1:0] = (gl2_en&~local_rst) ? gl_lvl2_new[1:0] : gl_lvl2_or_rst[1:0];
 
assign gl_lvl2_or_rst_or_new[1:0] = (gl2_en&~local_rst) ? gl_lvl2_new[1:0] : gl_lvl2_or_rst[1:0];
 
 
 
 
 
dff    #(2) dffe_gl2 (
 
dff_s    #(2) dffe_gl2 (
 
        .din(gl_lvl2_or_rst_or_new[1:0]) ,
 
        .din(gl_lvl2_or_rst_or_new[1:0]) ,
 
        .q(gl_lvl2[1:0]),
 
        .q(gl_lvl2[1:0]),
 
        .clk (clk), .se(se), .si(), .so());
 
        .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
 
 
 
 
 
/******************************/
 
/******************************/
 
 
 
 
 
assign tlu_gl_lvl2[2-1:0] = gl_lvl2[2-1:0];
 
assign tlu_gl_lvl2[`TSA_GLOBAL_WIDTH-1:0] = gl_lvl2[`TSA_GLOBAL_WIDTH-1:0];
 
 
 
 
 
// THREAD3
 
// THREAD3
 
 
 
 
 
assign gl_lvl3_at_maxgl  = (gl_lvl3[2-1:0] == 2'b11);
 
assign gl_lvl3_at_maxgl  = (gl_lvl3[`TSA_GLOBAL_WIDTH-1:0] == `MAXGL_GL);
 
assign gl_lvl3_at_maxstl = (gl_lvl3[2-1:0] == 2'b10);
 
assign gl_lvl3_at_maxstl = (gl_lvl3[`TSA_GLOBAL_WIDTH-1:0] == `MAXSTL_GL);
 
//
 
//
 
// trap level to be incremented if thread not at MAXGL and not in redmode
 
// trap level to be incremented if thread not at MAXGL and not in redmode
 
// modified for bug 2889
 
// modified for bug 2889
 
// modified due to timing
 
// modified due to timing
 
/*
 
/*
Line 1999... Line 1329... 
               ((local_rst | por_rstint3_g) ? `MAXGL_GL :
 
               ((local_rst | por_rstint3_g) ? `MAXGL_GL :
 
                   ((tlu_dnrtry3_inst_g) ?
 
                   ((tlu_dnrtry3_inst_g) ?
 
                         tlu_dnrtry_global_g[`TSA_GLOBAL_WIDTH-1:0] :     // done/retry restore
 
                         tlu_dnrtry_global_g[`TSA_GLOBAL_WIDTH-1:0] :     // done/retry restore
 
                     gl_lvl3[`TSA_GLOBAL_WIDTH-1:0] + gl_lvl3_incr[1:0])); // trap increments
 
                     gl_lvl3[`TSA_GLOBAL_WIDTH-1:0] + gl_lvl3_incr[1:0])); // trap increments
 
*/
 
*/
 
assign wsr_gl_lvl3_data[2-1:0] =
 
assign wsr_gl_lvl3_data[`TSA_GLOBAL_WIDTH-1:0] =
 
            (maxstl_gl_wr_sel[3])? 2'b10:
 
            (maxstl_gl_wr_sel[3])? `MAXSTL_GL:
 
           ((maxgl_gl_wr_sel[3]) ? 2'b11 :
 
           ((maxgl_gl_wr_sel[3]) ? `MAXGL_GL :
 
            tlu_wsr_data_w_global[2-1:0]);
 
            tlu_wsr_data_w_global[`TSA_GLOBAL_WIDTH-1:0]);
 
assign gl_lvl3_update_g[2-1:0] =
 
assign gl_lvl3_update_g[`TSA_GLOBAL_WIDTH-1:0] =
 
                (gl_rw_g & wsr_inst_g & thread_sel_id_g[3]) ?
 
                (gl_rw_g & wsr_inst_g & thread_sel_id_g[3]) ?
 
                         wsr_gl_lvl3_data[2-1:0] :
 
                         wsr_gl_lvl3_data[`TSA_GLOBAL_WIDTH-1:0] :
 
               ((local_rst | por_rstint3_g) ? 2'b11 :
 
               ((local_rst | por_rstint3_g) ? `MAXGL_GL :
 
                         dnrtry_gl_lvl3_data[2-1:0]);     // done/retry restore
 
                         dnrtry_gl_lvl3_data[`TSA_GLOBAL_WIDTH-1:0]);     // done/retry restore
 
                         // tlu_dnrtry_global_g[`TSA_GLOBAL_WIDTH-1:0]);     // done/retry restore
 
                         // tlu_dnrtry_global_g[`TSA_GLOBAL_WIDTH-1:0]);     // done/retry restore
 
 
 
 
 
dffe #(2) dffe_gl_lvl3_update_w2 (
 
dffe_s #(`TSA_GLOBAL_WIDTH) dffe_gl_lvl3_update_w2 (
 
     .din (gl_lvl3_update_g[2-1:0]),
 
     .din (gl_lvl3_update_g[`TSA_GLOBAL_WIDTH-1:0]),
 
     .q   (gl_lvl3_update_w2[2-1:0]),
 
     .q   (gl_lvl3_update_w2[`TSA_GLOBAL_WIDTH-1:0]),
 
     .en  (gl_update_sel_g[3]),
 
     .en  (gl_update_sel_g[3]),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
//
 
//
 
// modified for bug3468
 
// modified for bug3468
 
assign gl_incr_sel_w2[3] =
 
assign gl_incr_sel_w2[3] =
Line 2037... Line 1367... 
// 
// 
assign gl3_en =
 
assign gl3_en =
 
           gl_incr_sel_w2[3] | gl_update_sel_w2[3] | gl_priv_max_sel_w2[3];
 
           gl_incr_sel_w2[3] | gl_update_sel_w2[3] | gl_priv_max_sel_w2[3];
 
// assign gl3_en = gl_incr_sel_w2[3] | gl_update_sel_w2[3]; 
// assign gl3_en = gl_incr_sel_w2[3] | gl_update_sel_w2[3]; 
 
 
 
 
assign gl_lvl3_new[2-1:0] =
 
assign gl_lvl3_new[`TSA_GLOBAL_WIDTH-1:0] =
 
           (gl_update_sel_w2[3]) ? gl_lvl3_update_w2:
 
           (gl_update_sel_w2[3]) ? gl_lvl3_update_w2:
 
           (~gl_update_sel_w2[3] & gl_priv_max_sel_w2[3]) ?
 
           (~gl_update_sel_w2[3] & gl_priv_max_sel_w2[3]) ?
 
            2'b10:
 
            `MAXSTL_GL:
 
            gl_lvl3[2-1:0] + 2'b01;
 
            gl_lvl3[`TSA_GLOBAL_WIDTH-1:0] + 2'b01;
 
 
 
 
 
// Reset required as processor will start out at gl1 after reset.
 
// Reset required as processor will start out at gl1 after reset.
 
/****************************
 
/****************************
 
   to fix bug 6028 manually in the gate netlist, the following needs
 
   to fix bug 6028 manually in the gate netlist, the following needs
 
   to be a mux_flop with recirculating path from q to d0 input. But
 
   to be a mux_flop with recirculating path from q to d0 input. But
 
   to make it resetable, need to brake this recirculating path and
 
   to make it resetable, need to brake this recirculating path and
 
   insert an AND gate such that local_rst_l is ANDed with the q output.
 
   insert an AND gate such that local_rst_l is ANDed with the q output.
 
dffe #(`TSA_GLOBAL_WIDTH) dffe_gl3 (
 
dffe_s #(`TSA_GLOBAL_WIDTH) dffe_gl3 (
 
     .din (gl_lvl3_new[`TSA_GLOBAL_WIDTH-1:0]),
 
     .din (gl_lvl3_new[`TSA_GLOBAL_WIDTH-1:0]),
 
     .q   (gl_lvl3[`TSA_GLOBAL_WIDTH-1:0]),
 
     .q   (gl_lvl3[`TSA_GLOBAL_WIDTH-1:0]),
 
     .en  (gl3_en),
 
     .en  (gl3_en),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
******************************/
 
******************************/
 
 
 
 
 
wire [1:0] gl_lvl3_or_rst, gl_lvl3_or_rst_or_new;
 
wire [1:0] gl_lvl3_or_rst, gl_lvl3_or_rst_or_new;
 
 
 
 
 
assign gl_lvl3_or_rst[1:0] = gl_lvl3[1:0] & {2{~local_rst}};
 
assign gl_lvl3_or_rst[1:0] = gl_lvl3[1:0] & {2{~local_rst}};
 
 
 
 
 
assign gl_lvl3_or_rst_or_new[1:0] = (gl3_en&~local_rst) ? gl_lvl3_new[1:0] : gl_lvl3_or_rst[1:0];
 
assign gl_lvl3_or_rst_or_new[1:0] = (gl3_en&~local_rst) ? gl_lvl3_new[1:0] : gl_lvl3_or_rst[1:0];
 
 
 
 
 
dff    #(2) dffe_gl3 (
 
dff_s    #(2) dffe_gl3 (
 
        .din(gl_lvl3_or_rst_or_new[1:0]) ,
 
        .din(gl_lvl3_or_rst_or_new[1:0]) ,
 
        .q(gl_lvl3[1:0]),
 
        .q(gl_lvl3[1:0]),
 
        .clk (clk), .se(se), .si(), .so());
 
        .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
 
 
 
 
 
/******************************/
 
/******************************/
 
 
 
 
 
assign tlu_gl_lvl3[2-1:0] = gl_lvl3[2-1:0];
 
assign tlu_gl_lvl3[`TSA_GLOBAL_WIDTH-1:0] = gl_lvl3[`TSA_GLOBAL_WIDTH-1:0];
 
 
 
 
 
 // !`ifdef FPGA_SYN_1THREAD
 
`endif // !`ifdef FPGA_SYN_1THREAD
 
 
 
 
 
////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////
 
// Global swap 
// Global swap 
////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////
 
// modified due to timing
 
// modified due to timing
Line 2103... Line 1433... 
           (agp_thrid[1])? gl_lvl1_new[1:0] :
 
           (agp_thrid[1])? gl_lvl1_new[1:0] :
 
               ((agp_thrid[2])? gl_lvl2_new[1:0] :
 
               ((agp_thrid[2])? gl_lvl2_new[1:0] :
 
                   ((agp_thrid[3])? gl_lvl3_new[1:0] :
 
                   ((agp_thrid[3])? gl_lvl3_new[1:0] :
 
                        gl_lvl0_new[1:0]));
 
                        gl_lvl0_new[1:0]));
 
 
 
 
 
dffr dffr_tlu_exu_agp_swap (
 
dffr_s dffr_tlu_exu_agp_swap (
 
    .din (agp_swap),
 
    .din (agp_swap),
 
    .q   (tlu_exu_agp_swap),
 
    .q   (tlu_exu_agp_swap),
 
    .clk (clk),
 
    .clk (clk),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff #(2) dff_tlu_exu_agp (
 
dff_s #(2) dff_tlu_exu_agp (
 
    .din (agp_new[1:0]),
 
    .din (agp_new[1:0]),
 
    .q   (tlu_exu_agp[1:0]),
 
    .q   (tlu_exu_agp[1:0]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff #(2) dff_tlu_exu_agp_tid (
 
dff_s #(2) dff_tlu_exu_agp_tid (
 
    .din (tlu_agp_tid_g[1:0]),
 
    .din (tlu_agp_tid_g[1:0]),
 
    .q   (tlu_exu_agp_tid[1:0]),
 
    .q   (tlu_exu_agp_tid[1:0]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
*/
 
*/
 
 
 
 
 
assign agp_thrid_w2[0] = ~tlu_agp_tid_w2[0] & ~tlu_agp_tid_w2[1] & gl0_en;
 
assign agp_thrid_w2[0] = ~tlu_agp_tid_w2[0] & ~tlu_agp_tid_w2[1] & gl0_en;
 
 
 
 
 
 
 
`ifdef FPGA_SYN_1THREAD
 
 
 
   assign agp_thrid_w2[1] = 1'b0;
 
 
 
   assign agp_thrid_w2[2] = 1'b0;
 
 
 
   assign agp_thrid_w2[3] = 1'b0;
 
 
 
   assign agp_swap_w2 = (agp_thrid_w2[0])?
 
 
 
                          |(gl_lvl0_new[1:0] ^ gl_lvl0[1:0]):1'b0;
 
 
 
   dffr_s dffr_agp_swap_w3 (
 
 
 
    .din (agp_swap_w2),
 
 
 
    .q   (agp_swap_w3),
 
 
 
    .rst (local_rst),
 
 
 
    .clk (clk),
 
 
 
    .se  (se),
 
 
 
    `SIMPLY_RISC_SCANIN,
 
 
 
    .so ()
 
 
 
);
 
 
 
 
 
 
 
   assign agp_new_w2[1:0] = gl_lvl0_new[1:0];
 
 
 
 
 
 
 
`else
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
assign agp_thrid_w2[1] =  tlu_agp_tid_w2[0] & ~tlu_agp_tid_w2[1] & gl1_en;
 
assign agp_thrid_w2[1] =  tlu_agp_tid_w2[0] & ~tlu_agp_tid_w2[1] & gl1_en;
 
assign agp_thrid_w2[2] = ~tlu_agp_tid_w2[0] &  tlu_agp_tid_w2[1] & gl2_en;
 
assign agp_thrid_w2[2] = ~tlu_agp_tid_w2[0] &  tlu_agp_tid_w2[1] & gl2_en;
 
assign agp_thrid_w2[3] =  tlu_agp_tid_w2[0] &  tlu_agp_tid_w2[1] & gl3_en;
 
assign agp_thrid_w2[3] =  tlu_agp_tid_w2[0] &  tlu_agp_tid_w2[1] & gl3_en;
 
 
 
 
Line 2168... Line 1498... 
                     ((agp_thrid_w2[2])?
 
                     ((agp_thrid_w2[2])?
 
                         |(gl_lvl2_new[1:0] ^ gl_lvl2[1:0]):
 
                         |(gl_lvl2_new[1:0] ^ gl_lvl2[1:0]):
 
                         ((agp_thrid_w2[3])?
 
                         ((agp_thrid_w2[3])?
 
                            |(gl_lvl3_new[1:0] ^ gl_lvl3[1:0]):1'b0)));
 
                            |(gl_lvl3_new[1:0] ^ gl_lvl3[1:0]):1'b0)));
 
 
 
 
 
dffr dffr_agp_swap_w3 (
 
dffr_s dffr_agp_swap_w3 (
 
    .din (agp_swap_w2),
 
    .din (agp_swap_w2),
 
    .q   (agp_swap_w3),
 
    .q   (agp_swap_w3),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so ()
 
    .so ()
 
);
 
);
 
 
 
 
 
assign agp_new_w2[1:0] =
 
assign agp_new_w2[1:0] =
 
           (agp_thrid_w2[1])? gl_lvl1_new[1:0] :
 
           (agp_thrid_w2[1])? gl_lvl1_new[1:0] :
 
               ((agp_thrid_w2[2])? gl_lvl2_new[1:0] :
 
               ((agp_thrid_w2[2])? gl_lvl2_new[1:0] :
 
                   ((agp_thrid_w2[3])? gl_lvl3_new[1:0] :
 
                   ((agp_thrid_w2[3])? gl_lvl3_new[1:0] :
 
                        gl_lvl0_new[1:0]));
 
                        gl_lvl0_new[1:0]));
 
 // !`ifdef FPGA_SYN_1THREAD
 
`endif // !`ifdef FPGA_SYN_1THREAD
 
 
 
 
 
//
 
//
 
// added for timing fixes
 
// added for timing fixes
 
dff #(2) dff_agp_new_w3 (
 
dff_s #(2) dff_agp_new_w3 (
 
    .din (agp_new_w2[1:0]),
 
    .din (agp_new_w2[1:0]),
 
    .q   (agp_new_w3[1:0]),
 
    .q   (agp_new_w3[1:0]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
assign tlu_exu_agp_swap = agp_swap_w3;
 
assign tlu_exu_agp_swap = agp_swap_w3;
 
assign tlu_exu_agp[1:0] = agp_new_w3[1:0];
 
assign tlu_exu_agp[1:0] = agp_new_w3[1:0];
 
 
 
 
 
////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////
 
// HPSTATE register controls 
// HPSTATE register controls 
////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////
 
//
 
//
 
// added for timing
 
// added for timing
 
dffr #(4) dffr_update_hpstate_w2 (
 
dffr_s #(`TLU_THRD_NUM) dffr_update_hpstate_w2 (
 
    .din (update_hpstate_g[4-1:0]),
 
    .din (update_hpstate_g[`TLU_THRD_NUM-1:0]),
 
    .q   (update_hpstate_w2[4-1:0]),
 
    .q   (update_hpstate_w2[`TLU_THRD_NUM-1:0]),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
// thread 0
 
// thread 0
 
assign tlu_hpstate_din_sel0[0] = dnrtry_inst_w2[0] & ~rst_tri_en;
 
assign tlu_hpstate_din_sel0[0] = dnrtry_inst_w2[0] & ~rst_tri_en;
Line 2330... Line 1660... 
assign htickcmp_intdis_en[0] =
 
assign htickcmp_intdis_en[0] =
 
           (htickcmp_rw_g & wsr_inst_g & thread_sel_id_g[0]) |
 
           (htickcmp_rw_g & wsr_inst_g & thread_sel_id_g[0]) |
 
            local_rst | por_rstint0_g;
 
            local_rst | por_rstint0_g;
 
// 
// 
// HTICK_CMP.INT_DIS
 
// HTICK_CMP.INT_DIS
 
dffe dffe_hintdis0  (
 
dffe_s dffe_hintdis0  (
 
     .din (tlu_tick_ctl_din),
 
     .din (tlu_tick_ctl_din),
 
     .q   (htick_intdis0),
 
     .q   (htick_intdis0),
 
     .en  (htickcmp_intdis_en[0]),
 
     .en  (htickcmp_intdis_en[0]),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so ()
 
     .so ()
 
);
 
);
 
 
 
 
 
// thread 1
 
// thread 1
 
assign htickcmp_intdis_en[1] =
 
assign htickcmp_intdis_en[1] =
 
           (htickcmp_rw_g & wsr_inst_g & thread_sel_id_g[1]) |
 
           (htickcmp_rw_g & wsr_inst_g & thread_sel_id_g[1]) |
 
                        local_rst | por_rstint1_g;
 
                        local_rst | por_rstint1_g;
 
// 
// 
// HTICK_CMP.INT_DIS
 
// HTICK_CMP.INT_DIS
 
dffe dffe_hintdis1  (
 
dffe_s dffe_hintdis1  (
 
     .din (tlu_tick_ctl_din),
 
     .din (tlu_tick_ctl_din),
 
     .q   (htick_intdis1),
 
     .q   (htick_intdis1),
 
     .en  (htickcmp_intdis_en[1]),
 
     .en  (htickcmp_intdis_en[1]),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so ()
 
     .so ()
 
);
 
);
 
 
 
 
 
// thread 2
 
// thread 2
 
assign htickcmp_intdis_en[2] =
 
assign htickcmp_intdis_en[2] =
 
           (htickcmp_rw_g & wsr_inst_g & thread_sel_id_g[2]) |
 
           (htickcmp_rw_g & wsr_inst_g & thread_sel_id_g[2]) |
 
                        local_rst | por_rstint2_g;
 
                        local_rst | por_rstint2_g;
 
// 
// 
// HTICK_CMP.INT_DIS
 
// HTICK_CMP.INT_DIS
 
dffe dffe_hintdis2  (
 
dffe_s dffe_hintdis2  (
 
     .din (tlu_tick_ctl_din),
 
     .din (tlu_tick_ctl_din),
 
     .q   (htick_intdis2),
 
     .q   (htick_intdis2),
 
     .en  (htickcmp_intdis_en[2]),
 
     .en  (htickcmp_intdis_en[2]),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so ()
 
     .so ()
 
);
 
);
 
 
 
 
 
// thread 3
 
// thread 3
 
assign htickcmp_intdis_en[3] =
 
assign htickcmp_intdis_en[3] =
 
           (htickcmp_rw_g & wsr_inst_g & thread_sel_id_g[3]) |
 
           (htickcmp_rw_g & wsr_inst_g & thread_sel_id_g[3]) |
 
                        local_rst | por_rstint3_g;
 
                        local_rst | por_rstint3_g;
 
// HTICK_CMP.INT_DIS
 
// HTICK_CMP.INT_DIS
 
//
 
//
 
dffe dffe_hintdis3  (
 
dffe_s dffe_hintdis3  (
 
     .din (tlu_tick_ctl_din),
 
     .din (tlu_tick_ctl_din),
 
     .q   (htick_intdis3),
 
     .q   (htick_intdis3),
 
     .en  (htickcmp_intdis_en[3]),
 
     .en  (htickcmp_intdis_en[3]),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so ()
 
     .so ()
 
);
 
);
 
//
 
//
 
// generating for the non-thread specific htick_cmp
 
// generating for the non-thread specific htick_cmp
 
// interrupt disable
 
// interrupt disable
Line 2482... Line 1812... 
 
 
 
 
// assign asi_queue_read_g  = 
// assign asi_queue_read_g  = 
//     ~(tlu_flush_pipe_w | ifu_tlu_flush_w) & asi_queue_read_uf_g;
 
//     ~(tlu_flush_pipe_w | ifu_tlu_flush_w) & asi_queue_read_uf_g;
 
//
 
//
 
// staging the asi controls
 
// staging the asi controls
 
dffr #(2) dffr_asi_ctl_m (
 
dffr_s #(2) dffr_asi_ctl_m (
 
    .din ({asi_queue_write_e, asi_queue_read_e}),
 
    .din ({asi_queue_write_e, asi_queue_read_e}),
 
    .q   ({asi_queue_write_pq_m, asi_queue_read_pq_m}),
 
    .q   ({asi_queue_write_pq_m, asi_queue_read_pq_m}),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dffr #(2) dffr_asi_ctl_g (
 
dffr_s #(2) dffr_asi_ctl_g (
 
    .din ({asi_queue_write_m, asi_queue_read_m}),
 
    .din ({asi_queue_write_m, asi_queue_read_m}),
 
    .q   ({asi_queue_write_uf_g, asi_queue_read_g}),
 
    .q   ({asi_queue_write_uf_g, asi_queue_read_g}),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
// 
// 
// ASI address decode 
// ASI address decode 
// decoding the ASI state 0x25 for the ASI_QUEUES
 
// decoding the ASI state 0x25 for the ASI_QUEUES
 
assign asi_queue_rw_e =
 
assign asi_queue_rw_e =
 
          (ifu_lsu_alt_space_e)?
 
          (ifu_lsu_alt_space_e)?
 
          (tlu_asi_state_e[8-1:0]==8'h25):
 
          (tlu_asi_state_e[`TLU_ASI_STATE_WIDTH-1:0]==`TLU_ASI_QUE_ASI):
 
           1'b0;
 
           1'b0;
 
//
 
//
 
// staging the asi controls
 
// staging the asi controls
 
dffr dffr_asi_queue_rw_m (
 
dffr_s dffr_asi_queue_rw_m (
 
    .din (asi_queue_rw_e),
 
    .din (asi_queue_rw_e),
 
    .q   (asi_queue_rw_m),
 
    .q   (asi_queue_rw_m),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dffr dffr_asi_queue_rw_g (
 
dffr_s dffr_asi_queue_rw_g (
 
    .din (asi_queue_rw_m),
 
    .din (asi_queue_rw_m),
 
    .q   (asi_queue_rw_g),
 
    .q   (asi_queue_rw_g),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
//
 
//
 
// modified due to timing violations
 
// modified due to timing violations
 
/*
 
/*
 
// assign tlu_ldst_va_e[`TLU_ASI_VA_WIDTH-1:0] =
 
// assign tlu_ldst_va_e[`TLU_ASI_VA_WIDTH-1:0] =
 
//          exu_lsu_ldst_va_e[`TLU_ASI_VA_WIDTH-1:0];
 
//          exu_lsu_ldst_va_e[`TLU_ASI_VA_WIDTH-1:0];
 
dff #(`TLU_ASI_VA_WIDTH) dff_tlu_ldst_va_m (
 
dff_s #(`TLU_ASI_VA_WIDTH) dff_tlu_ldst_va_m (
 
    .din (exu_lsu_ldst_va_e[`TLU_ASI_VA_WIDTH-1:0]),
 
    .din (exu_lsu_ldst_va_e[`TLU_ASI_VA_WIDTH-1:0]),
 
    .q   (tlu_ldst_va_m[`TLU_ASI_VA_WIDTH-1:0]),
 
    .q   (tlu_ldst_va_m[`TLU_ASI_VA_WIDTH-1:0]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
// modified for timing
 
// modified for timing
 
assign que_legal_va_e =
 
assign que_legal_va_e =
Line 2556... Line 1886... 
           (ifu_lsu_alt_space_e)?
 
           (ifu_lsu_alt_space_e)?
 
           (((|exu_lsu_ldst_va_e[`ASI_VA_WIDTH-1:`TLU_ASI_QUE_VA_HI+1]) |
 
           (((|exu_lsu_ldst_va_e[`ASI_VA_WIDTH-1:`TLU_ASI_QUE_VA_HI+1]) |
 
           (|exu_lsu_ldst_va_e[`TLU_ASI_QUE_VA_LO-1:0]) | ~que_legal_va_e) &
 
           (|exu_lsu_ldst_va_e[`TLU_ASI_QUE_VA_LO-1:0]) | ~que_legal_va_e) &
 
            asi_queue_pq_rw_e): 1'b0;
 
            asi_queue_pq_rw_e): 1'b0;
 
*/
 
*/
 
assign tlu_ldst_va_m[10-1:0] =
 
assign tlu_ldst_va_m[`TLU_ASI_VA_WIDTH-1:0] =
 
           lsu_tlu_ldst_va_m[10-1:0];
 
           lsu_tlu_ldst_va_m[`TLU_ASI_VA_WIDTH-1:0];
 
 
 
 
 
assign que_legal_va_m =
 
assign que_legal_va_m =
 
           cpu_mondo_head_rw_m  | cpu_mondo_tail_rw_m |
 
           cpu_mondo_head_rw_m  | cpu_mondo_tail_rw_m |
 
           dev_mondo_head_rw_m  | dev_mondo_tail_rw_m |
 
           dev_mondo_head_rw_m  | dev_mondo_tail_rw_m |
 
           resum_err_head_rw_m  | resum_err_tail_rw_m |
 
           resum_err_head_rw_m  | resum_err_tail_rw_m |
Line 2572... Line 1902... 
assign que_ill_va_m =
 
assign que_ill_va_m =
 
           (asi_queue_rw_m)? ~que_legal_va_m : 1'b0;
 
           (asi_queue_rw_m)? ~que_legal_va_m : 1'b0;
 
//
 
//
 
// staged illegal va range 
// staged illegal va range 
//
 
//
 
dffr dffr_que_ill_va_g (
 
dffr_s dffr_que_ill_va_g (
 
    .din (que_ill_va_m),
 
    .din (que_ill_va_m),
 
    .q   (que_ill_va_g),
 
    .q   (que_ill_va_g),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
// 
// 
// added for timing - interrupt register decodes
 
// added for timing - interrupt register decodes
 
// interrupt receiver registers
 
// interrupt receiver registers
 
assign asi_inrr_rw_e =
 
assign asi_inrr_rw_e =
 
          (ifu_lsu_alt_space_e)?
 
          (ifu_lsu_alt_space_e)?
 
          (tlu_asi_state_e[8-1:0]==8'h72):
 
          (tlu_asi_state_e[`TLU_ASI_STATE_WIDTH-1:0]==`TLU_INRR_ASI):
 
           1'b0;
 
           1'b0;
 
 
 
 
 
dffr dffr_asi_inrr_rw_m (
 
dffr_s dffr_asi_inrr_rw_m (
 
    .din (asi_inrr_rw_e),
 
    .din (asi_inrr_rw_e),
 
    .q   (asi_inrr_rw_m),
 
    .q   (asi_inrr_rw_m),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dffr dffr_asi_inrr_rw_g (
 
dffr_s dffr_asi_inrr_rw_g (
 
    .din (asi_inrr_rw_m),
 
    .din (asi_inrr_rw_m),
 
    .q   (asi_inrr_rw_g),
 
    .q   (asi_inrr_rw_g),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
assign inc_ind_asi_wr_inrr[0] =
 
assign inc_ind_asi_wr_inrr[0] =
 
           (asi_inrr_rw_g & asi_queue_write_uf_g   &
 
           (asi_inrr_rw_g & asi_queue_write_uf_g   &
Line 2625... Line 1955... 
           ~local_flush_all_w & thread_sel_id_g[3]);
 
           ~local_flush_all_w & thread_sel_id_g[3]);
 
//
 
//
 
// interrupt dispatch registers
 
// interrupt dispatch registers
 
assign asi_indr_rw_e =
 
assign asi_indr_rw_e =
 
          (ifu_lsu_alt_space_e)?
 
          (ifu_lsu_alt_space_e)?
 
          (tlu_asi_state_e[8-1:0]==8'h73):
 
          (tlu_asi_state_e[`TLU_ASI_STATE_WIDTH-1:0]==`TLU_INDR_ASI):
 
           1'b0;
 
           1'b0;
 
 
 
 
 
dffr dffr_asi_indr_rw_m (
 
dffr_s dffr_asi_indr_rw_m (
 
    .din (asi_indr_rw_e),
 
    .din (asi_indr_rw_e),
 
    .q   (asi_indr_rw_m),
 
    .q   (asi_indr_rw_m),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dffr dffr_asi_indr_rw_g (
 
dffr_s dffr_asi_indr_rw_g (
 
    .din (asi_indr_rw_m),
 
    .din (asi_indr_rw_m),
 
    .q   (asi_indr_rw_g),
 
    .q   (asi_indr_rw_g),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
assign inc_ind_asi_wr_indr[0] =
 
assign inc_ind_asi_wr_indr[0] =
 
           asi_indr_rw_g & ~local_flush_all_w & asi_queue_write_uf_g &
 
           asi_indr_rw_g & ~local_flush_all_w & asi_queue_write_uf_g &
Line 2665... Line 1995... 
 
 
 
 
//
 
//
 
// interrupt vector registers
 
// interrupt vector registers
 
assign asi_invr_rw_e =
 
assign asi_invr_rw_e =
 
          (ifu_lsu_alt_space_e)?
 
          (ifu_lsu_alt_space_e)?
 
          (tlu_asi_state_e[8-1:0]==8'h74):
 
          (tlu_asi_state_e[`TLU_ASI_STATE_WIDTH-1:0]==`TLU_INVR_ASI):
 
           1'b0;
 
           1'b0;
 
 
 
 
 
dffr dffr_asi_invr_rw_m (
 
dffr_s dffr_asi_invr_rw_m (
 
    .din (asi_invr_rw_e),
 
    .din (asi_invr_rw_e),
 
    .q   (asi_invr_rw_m),
 
    .q   (asi_invr_rw_m),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dffr dffr_asi_invr_rw_g (
 
dffr_s dffr_asi_invr_rw_g (
 
    .din (asi_invr_rw_m),
 
    .din (asi_invr_rw_m),
 
    .q   (asi_invr_rw_g),
 
    .q   (asi_invr_rw_g),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
assign inc_ind_asi_rd_invr[0] =
 
assign inc_ind_asi_rd_invr[0] =
 
           (asi_invr_rw_g & asi_queue_read_g &
 
           (asi_invr_rw_g & asi_queue_read_g &
Line 2705... Line 2035... 
//
 
//
 
// timing changes: all va e stage signals have been moved to m-stage
 
// timing changes: all va e stage signals have been moved to m-stage
 
// decoding the VA portion of the ASI address
 
// decoding the VA portion of the ASI address
 
// cpu_mondo_head: 0x3c0
 
// cpu_mondo_head: 0x3c0
 
assign cpu_mondo_head_rw_m =
 
assign cpu_mondo_head_rw_m =
 
          (tlu_ldst_va_m[10-1:0]==10'h3c0);
 
          (tlu_ldst_va_m[`TLU_ASI_VA_WIDTH-1:0]==`CPU_MONDO_HEAD);
 
//
 
//
 
// cpu_mondo_tail: 0x3c8
 
// cpu_mondo_tail: 0x3c8
 
assign cpu_mondo_tail_rw_m =
 
assign cpu_mondo_tail_rw_m =
 
          (tlu_ldst_va_m[10-1:0]==10'h3c8);
 
          (tlu_ldst_va_m[`TLU_ASI_VA_WIDTH-1:0]==`CPU_MONDO_TAIL);
 
//
 
//
 
// dev_mondo_head: 0x3d0
 
// dev_mondo_head: 0x3d0
 
assign dev_mondo_head_rw_m =
 
assign dev_mondo_head_rw_m =
 
          (tlu_ldst_va_m[10-1:0]==10'h3d0);
 
          (tlu_ldst_va_m[`TLU_ASI_VA_WIDTH-1:0]==`DEV_MONDO_HEAD);
 
//
 
//
 
// dev_mondo_tail: 0x3d8
 
// dev_mondo_tail: 0x3d8
 
assign dev_mondo_tail_rw_m =
 
assign dev_mondo_tail_rw_m =
 
          (tlu_ldst_va_m[10-1:0]==10'h3d8);
 
          (tlu_ldst_va_m[`TLU_ASI_VA_WIDTH-1:0]==`DEV_MONDO_TAIL);
 
//
 
//
 
// resum_err_head: 0x3e0
 
// resum_err_head: 0x3e0
 
assign resum_err_head_rw_m =
 
assign resum_err_head_rw_m =
 
          (tlu_ldst_va_m[10-1:0]==10'h3e0);
 
          (tlu_ldst_va_m[`TLU_ASI_VA_WIDTH-1:0]==`RESUM_ERR_HEAD);
 
//
 
//
 
// resum_err_tail: 0x3e8
 
// resum_err_tail: 0x3e8
 
assign resum_err_tail_rw_m =
 
assign resum_err_tail_rw_m =
 
          (tlu_ldst_va_m[10-1:0]==10'h3e8);
 
          (tlu_ldst_va_m[`TLU_ASI_VA_WIDTH-1:0]==`RESUM_ERR_TAIL);
 
//
 
//
 
// nresum_err_head: 0x3f0
 
// nresum_err_head: 0x3f0
 
assign nresum_err_head_rw_m =
 
assign nresum_err_head_rw_m =
 
          (tlu_ldst_va_m[10-1:0]==10'h3f0);
 
          (tlu_ldst_va_m[`TLU_ASI_VA_WIDTH-1:0]==`NRESUM_ERR_HEAD);
 
//
 
//
 
// nresum_err_tail: 0x3f8
 
// nresum_err_tail: 0x3f8
 
assign nresum_err_tail_rw_m =
 
assign nresum_err_tail_rw_m =
 
          (tlu_ldst_va_m[10-1:0]==10'h3f8);
 
          (tlu_ldst_va_m[`TLU_ASI_VA_WIDTH-1:0]==`NRESUM_ERR_TAIL);
 
//
 
//
 
// timing change: replaced by flopped tlu_ldst_va_m decodes
 
// timing change: replaced by flopped tlu_ldst_va_m decodes
 
// staging the ASI queue rw decodes
 
// staging the ASI queue rw decodes
 
// cpu_mondo_head
 
// cpu_mondo_head
 
/*
 
/*
 
dff dff_cpu_mondo_head_rw_m (
 
dff_s dff_cpu_mondo_head_rw_m (
 
     .din (cpu_mondo_head_rw_e),
 
     .din (cpu_mondo_head_rw_e),
 
     .q   (cpu_mondo_head_rw_m),
 
     .q   (cpu_mondo_head_rw_m),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
 
 
 
 
dff dff_dev_mondo_head_rw_m (
 
dff_s dff_dev_mondo_head_rw_m (
 
     .din (dev_mondo_head_rw_e),
 
     .din (dev_mondo_head_rw_e),
 
     .q   (dev_mondo_head_rw_m),
 
     .q   (dev_mondo_head_rw_m),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
 
 
 
 
dff dff_resum_err_head_rw_m (
 
dff_s dff_resum_err_head_rw_m (
 
     .din (resum_err_head_rw_e),
 
     .din (resum_err_head_rw_e),
 
     .q   (resum_err_head_rw_m),
 
     .q   (resum_err_head_rw_m),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
 
 
 
 
dff dff_nresum_err_head_rw_m (
 
dff_s dff_nresum_err_head_rw_m (
 
     .din (nresum_err_head_rw_e),
 
     .din (nresum_err_head_rw_e),
 
     .q   (nresum_err_head_rw_m),
 
     .q   (nresum_err_head_rw_m),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
 
 
 
 
dff dff_cpu_mondo_tail_rw_m (
 
dff_s dff_cpu_mondo_tail_rw_m (
 
     .din (cpu_mondo_tail_rw_e),
 
     .din (cpu_mondo_tail_rw_e),
 
     .q   (cpu_mondo_tail_rw_m),
 
     .q   (cpu_mondo_tail_rw_m),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
 
 
 
 
dff dff_dev_mondo_tail_rw_m (
 
dff_s dff_dev_mondo_tail_rw_m (
 
     .din (dev_mondo_tail_rw_e),
 
     .din (dev_mondo_tail_rw_e),
 
     .q   (dev_mondo_tail_rw_m),
 
     .q   (dev_mondo_tail_rw_m),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
 
 
 
 
dff dff_resum_err_tail_rw_m (
 
dff_s dff_resum_err_tail_rw_m (
 
     .din (resum_err_tail_rw_e),
 
     .din (resum_err_tail_rw_e),
 
     .q   (resum_err_tail_rw_m),
 
     .q   (resum_err_tail_rw_m),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
 
 
 
 
dff dff_nresum_err_tail_rw_m (
 
dff_s dff_nresum_err_tail_rw_m (
 
     .din (nresum_err_tail_rw_e),
 
     .din (nresum_err_tail_rw_e),
 
     .q   (nresum_err_tail_rw_m),
 
     .q   (nresum_err_tail_rw_m),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
//
 
//
 
// illegal range check
 
// illegal range check
 
dffr dffr_que_ill_va_m (
 
dffr_s dffr_que_ill_va_m (
 
    .din (que_ill_va_e),
 
    .din (que_ill_va_e),
 
    .q   (que_ill_va_m),
 
    .q   (que_ill_va_m),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
*/
 
*/
 
 
 
 
 
// staging the ASI queue rw decodes
 
// staging the ASI queue rw decodes
 
// cpu_mondo_head
 
// cpu_mondo_head
 
dff dff_cpu_mondo_head_rw_g (
 
dff_s dff_cpu_mondo_head_rw_g (
 
     .din (cpu_mondo_head_rw_m),
 
     .din (cpu_mondo_head_rw_m),
 
     .q   (cpu_mondo_head_rw_g),
 
     .q   (cpu_mondo_head_rw_g),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
//
 
//
 
// dev_mondo_head
 
// dev_mondo_head
 
dff dff_dev_mondo_head_rw_g (
 
dff_s dff_dev_mondo_head_rw_g (
 
     .din (dev_mondo_head_rw_m),
 
     .din (dev_mondo_head_rw_m),
 
     .q   (dev_mondo_head_rw_g),
 
     .q   (dev_mondo_head_rw_g),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
//
 
//
 
// resum_err_head
 
// resum_err_head
 
dff dff_resum_err_head_rw_g (
 
dff_s dff_resum_err_head_rw_g (
 
     .din (resum_err_head_rw_m),
 
     .din (resum_err_head_rw_m),
 
     .q   (resum_err_head_rw_g),
 
     .q   (resum_err_head_rw_g),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
//
 
//
 
// nresum_err_head
 
// nresum_err_head
 
dff dff_nresum_err_head_rw_g (
 
dff_s dff_nresum_err_head_rw_g (
 
     .din (nresum_err_head_rw_m),
 
     .din (nresum_err_head_rw_m),
 
     .q   (nresum_err_head_rw_g),
 
     .q   (nresum_err_head_rw_g),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
// 
// 
// cpu_mondo_tail
 
// cpu_mondo_tail
 
//
 
//
 
dff dff_cpu_mondo_tail_rw_g (
 
dff_s dff_cpu_mondo_tail_rw_g (
 
     .din (cpu_mondo_tail_rw_m),
 
     .din (cpu_mondo_tail_rw_m),
 
     .q   (cpu_mondo_tail_rw_g),
 
     .q   (cpu_mondo_tail_rw_g),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
//
 
//
 
// dev_mondo_tail
 
// dev_mondo_tail
 
//
 
//
 
dff dff_dev_mondo_tail_rw_g (
 
dff_s dff_dev_mondo_tail_rw_g (
 
     .din (dev_mondo_tail_rw_m),
 
     .din (dev_mondo_tail_rw_m),
 
     .q   (dev_mondo_tail_rw_g),
 
     .q   (dev_mondo_tail_rw_g),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
//
 
//
 
// resum_err_tail
 
// resum_err_tail
 
//
 
//
 
dff dff_resum_err_tail_rw_g (
 
dff_s dff_resum_err_tail_rw_g (
 
     .din (resum_err_tail_rw_m),
 
     .din (resum_err_tail_rw_m),
 
     .q   (resum_err_tail_rw_g),
 
     .q   (resum_err_tail_rw_g),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
//
 
//
 
// nresum_err_tail
 
// nresum_err_tail
 
//
 
//
 
dff dff_nresum_err_tail_rw_g (
 
dff_s dff_nresum_err_tail_rw_g (
 
     .din (nresum_err_tail_rw_m),
 
     .din (nresum_err_tail_rw_m),
 
     .q   (nresum_err_tail_rw_g),
 
     .q   (nresum_err_tail_rw_g),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
// 
// 
// generating thread specific read and write enables  
// generating thread specific read and write enables  
//
 
//
Line 3201... Line 2531... 
           asi_queue_rw_g    & thread_sel_id_g[3];
 
           asi_queue_rw_g    & thread_sel_id_g[3];
 
//
 
//
 
// storing the head and pointers for the queues
 
// storing the head and pointers for the queues
 
// thread 0
 
// thread 0
 
//
 
//
 
dffe #(8) dffe_cpu_mondo0_head (
 
dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_cpu_mondo0_head (
 
     .din (tlu_asi_queue_data_g[8-1:0]),
 
     .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .q   (cpu_mondo0_head[8-1:0]),
 
     .q   (cpu_mondo0_head[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .en  (cpu_mondo_head_wr_g[0]),
 
     .en  (cpu_mondo_head_wr_g[0]),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
 
 
 
 
dffe #(8) dffe_cpu_mondo0_tail (
 
dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_cpu_mondo0_tail (
 
     .din (tlu_asi_queue_data_g[8-1:0]),
 
     .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .q   (cpu_mondo0_tail[8-1:0]),
 
     .q   (cpu_mondo0_tail[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .en  (cpu_mondo_tail_wr_g[0]),
 
     .en  (cpu_mondo_tail_wr_g[0]),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
 
 
 
 
dffe #(8) dffe_dev_mondo0_head (
 
dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_dev_mondo0_head (
 
     .din (tlu_asi_queue_data_g[8-1:0]),
 
     .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .q   (dev_mondo0_head[8-1:0]),
 
     .q   (dev_mondo0_head[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .en  (dev_mondo_head_wr_g[0]),
 
     .en  (dev_mondo_head_wr_g[0]),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
 
 
 
 
dffe #(8) dffe_dev_mondo0_tail (
 
dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_dev_mondo0_tail (
 
     .din (tlu_asi_queue_data_g[8-1:0]),
 
     .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .q   (dev_mondo0_tail[8-1:0]),
 
     .q   (dev_mondo0_tail[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .en  (dev_mondo_tail_wr_g[0]),
 
     .en  (dev_mondo_tail_wr_g[0]),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
 
 
 
 
dffe #(8) dffe_resum_err0_head (
 
dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_resum_err0_head (
 
     .din (tlu_asi_queue_data_g[8-1:0]),
 
     .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .q   (resum_err0_head[8-1:0]),
 
     .q   (resum_err0_head[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .en  (resum_err_head_wr_g[0]),
 
     .en  (resum_err_head_wr_g[0]),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
 
 
 
 
dffe #(8) dffe_resum_err0_tail (
 
dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_resum_err0_tail (
 
     .din (tlu_asi_queue_data_g[8-1:0]),
 
     .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .q   (resum_err0_tail[8-1:0]),
 
     .q   (resum_err0_tail[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .en  (resum_err_tail_wr_g[0]),
 
     .en  (resum_err_tail_wr_g[0]),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
 
 
 
 
dffe #(8) dffe_nresum_err0_head (
 
dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_nresum_err0_head (
 
     .din (tlu_asi_queue_data_g[8-1:0]),
 
     .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .q   (nresum_err0_head[8-1:0]),
 
     .q   (nresum_err0_head[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .en  (nresum_err_head_wr_g[0]),
 
     .en  (nresum_err_head_wr_g[0]),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
 
 
 
 
dffe #(8) dffe_nresum_err0_tail (
 
dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_nresum_err0_tail (
 
     .din (tlu_asi_queue_data_g[8-1:0]),
 
     .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .q   (nresum_err0_tail[8-1:0]),
 
     .q   (nresum_err0_tail[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .en  (nresum_err_tail_wr_g[0]),
 
     .en  (nresum_err_tail_wr_g[0]),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
//
 
//
 
// thread 1
 
// thread 1
 
//
 
//
 
dffe #(8) dffe_cpu_mondo1_head (
 
dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_cpu_mondo1_head (
 
     .din (tlu_asi_queue_data_g[8-1:0]),
 
     .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .q   (cpu_mondo1_head[8-1:0]),
 
     .q   (cpu_mondo1_head[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .en  (cpu_mondo_head_wr_g[1]),
 
     .en  (cpu_mondo_head_wr_g[1]),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
 
 
 
 
dffe #(8) dffe_cpu_mondo1_tail (
 
dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_cpu_mondo1_tail (
 
     .din (tlu_asi_queue_data_g[8-1:0]),
 
     .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .q   (cpu_mondo1_tail[8-1:0]),
 
     .q   (cpu_mondo1_tail[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .en  (cpu_mondo_tail_wr_g[1]),
 
     .en  (cpu_mondo_tail_wr_g[1]),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
 
 
 
 
dffe #(8) dffe_dev_mondo1_head (
 
dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_dev_mondo1_head (
 
     .din (tlu_asi_queue_data_g[8-1:0]),
 
     .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .q   (dev_mondo1_head[8-1:0]),
 
     .q   (dev_mondo1_head[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .en  (dev_mondo_head_wr_g[1]),
 
     .en  (dev_mondo_head_wr_g[1]),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
 
 
 
 
dffe #(8) dffe_dev_mondo1_tail (
 
dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_dev_mondo1_tail (
 
     .din (tlu_asi_queue_data_g[8-1:0]),
 
     .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .q   (dev_mondo1_tail[8-1:0]),
 
     .q   (dev_mondo1_tail[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .en  (dev_mondo_tail_wr_g[1]),
 
     .en  (dev_mondo_tail_wr_g[1]),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
 
 
 
 
dffe #(8) dffe_resum_err1_head (
 
dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_resum_err1_head (
 
     .din (tlu_asi_queue_data_g[8-1:0]),
 
     .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .q   (resum_err1_head[8-1:0]),
 
     .q   (resum_err1_head[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .en  (resum_err_head_wr_g[1]),
 
     .en  (resum_err_head_wr_g[1]),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
 
 
 
 
dffe #(8) dffe_resum_err1_tail (
 
dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_resum_err1_tail (
 
     .din (tlu_asi_queue_data_g[8-1:0]),
 
     .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .q   (resum_err1_tail[8-1:0]),
 
     .q   (resum_err1_tail[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .en  (resum_err_tail_wr_g[1]),
 
     .en  (resum_err_tail_wr_g[1]),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
 
 
 
 
dffe #(8) dffe_nresum_err1_head (
 
dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_nresum_err1_head (
 
     .din (tlu_asi_queue_data_g[8-1:0]),
 
     .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .q   (nresum_err1_head[8-1:0]),
 
     .q   (nresum_err1_head[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .en  (nresum_err_head_wr_g[1]),
 
     .en  (nresum_err_head_wr_g[1]),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
 
 
 
 
dffe #(8) dffe_nresum_err1_tail (
 
dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_nresum_err1_tail (
 
     .din (tlu_asi_queue_data_g[8-1:0]),
 
     .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .q   (nresum_err1_tail[8-1:0]),
 
     .q   (nresum_err1_tail[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .en  (nresum_err_tail_wr_g[1]),
 
     .en  (nresum_err_tail_wr_g[1]),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
//
 
//
 
// thread 2
 
// thread 2
 
//
 
//
 
dffe #(8) dffe_cpu_mondo2_head (
 
dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_cpu_mondo2_head (
 
     .din (tlu_asi_queue_data_g[8-1:0]),
 
     .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .q   (cpu_mondo2_head[8-1:0]),
 
     .q   (cpu_mondo2_head[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .en  (cpu_mondo_head_wr_g[2]),
 
     .en  (cpu_mondo_head_wr_g[2]),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
 
 
 
 
dffe #(8) dffe_cpu_mondo2_tail (
 
dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_cpu_mondo2_tail (
 
     .din (tlu_asi_queue_data_g[8-1:0]),
 
     .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .q   (cpu_mondo2_tail[8-1:0]),
 
     .q   (cpu_mondo2_tail[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .en  (cpu_mondo_tail_wr_g[2]),
 
     .en  (cpu_mondo_tail_wr_g[2]),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
 
 
 
 
dffe #(8) dffe_dev_mondo2_head (
 
dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_dev_mondo2_head (
 
     .din (tlu_asi_queue_data_g[8-1:0]),
 
     .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .q   (dev_mondo2_head[8-1:0]),
 
     .q   (dev_mondo2_head[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .en  (dev_mondo_head_wr_g[2]),
 
     .en  (dev_mondo_head_wr_g[2]),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
 
 
 
 
dffe #(8) dffe_dev_mondo2_tail (
 
dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_dev_mondo2_tail (
 
     .din (tlu_asi_queue_data_g[8-1:0]),
 
     .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .q   (dev_mondo2_tail[8-1:0]),
 
     .q   (dev_mondo2_tail[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .en  (dev_mondo_tail_wr_g[2]),
 
     .en  (dev_mondo_tail_wr_g[2]),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
 
 
 
 
dffe #(8) dffe_resum_err2_head (
 
dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_resum_err2_head (
 
     .din (tlu_asi_queue_data_g[8-1:0]),
 
     .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .q   (resum_err2_head[8-1:0]),
 
     .q   (resum_err2_head[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .en  (resum_err_head_wr_g[2]),
 
     .en  (resum_err_head_wr_g[2]),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
 
 
 
 
dffe #(8) dffe_resum_err2_tail (
 
dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_resum_err2_tail (
 
     .din (tlu_asi_queue_data_g[8-1:0]),
 
     .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .q   (resum_err2_tail[8-1:0]),
 
     .q   (resum_err2_tail[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .en  (resum_err_tail_wr_g[2]),
 
     .en  (resum_err_tail_wr_g[2]),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
 
 
 
 
dffe #(8) dffe_nresum_err2_head (
 
dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_nresum_err2_head (
 
     .din (tlu_asi_queue_data_g[8-1:0]),
 
     .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .q   (nresum_err2_head[8-1:0]),
 
     .q   (nresum_err2_head[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .en  (nresum_err_head_wr_g[2]),
 
     .en  (nresum_err_head_wr_g[2]),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
 
 
 
 
dffe #(8) dffe_nresum_err2_tail (
 
dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_nresum_err2_tail (
 
     .din (tlu_asi_queue_data_g[8-1:0]),
 
     .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .q   (nresum_err2_tail[8-1:0]),
 
     .q   (nresum_err2_tail[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .en  (nresum_err_tail_wr_g[2]),
 
     .en  (nresum_err_tail_wr_g[2]),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
//
 
//
 
// thread 3
 
// thread 3
 
//
 
//
 
dffe #(8) dffe_cpu_mondo3_head (
 
dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_cpu_mondo3_head (
 
     .din (tlu_asi_queue_data_g[8-1:0]),
 
     .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .q   (cpu_mondo3_head[8-1:0]),
 
     .q   (cpu_mondo3_head[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .en  (cpu_mondo_head_wr_g[3]),
 
     .en  (cpu_mondo_head_wr_g[3]),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
 
 
 
 
dffe #(8) dffe_cpu_mondo3_tail (
 
dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_cpu_mondo3_tail (
 
     .din (tlu_asi_queue_data_g[8-1:0]),
 
     .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .q   (cpu_mondo3_tail[8-1:0]),
 
     .q   (cpu_mondo3_tail[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .en  (cpu_mondo_tail_wr_g[3]),
 
     .en  (cpu_mondo_tail_wr_g[3]),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
 
 
 
 
dffe #(8) dffe_dev_mondo3_head (
 
dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_dev_mondo3_head (
 
     .din (tlu_asi_queue_data_g[8-1:0]),
 
     .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .q   (dev_mondo3_head[8-1:0]),
 
     .q   (dev_mondo3_head[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .en  (dev_mondo_head_wr_g[3]),
 
     .en  (dev_mondo_head_wr_g[3]),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
 
 
 
 
dffe #(8) dffe_dev_mondo3_tail (
 
dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_dev_mondo3_tail (
 
     .din (tlu_asi_queue_data_g[8-1:0]),
 
     .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .q   (dev_mondo3_tail[8-1:0]),
 
     .q   (dev_mondo3_tail[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .en  (dev_mondo_tail_wr_g[3]),
 
     .en  (dev_mondo_tail_wr_g[3]),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
 
 
 
 
dffe #(8) dffe_resum_err3_head (
 
dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_resum_err3_head (
 
     .din (tlu_asi_queue_data_g[8-1:0]),
 
     .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .q   (resum_err3_head[8-1:0]),
 
     .q   (resum_err3_head[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .en  (resum_err_head_wr_g[3]),
 
     .en  (resum_err_head_wr_g[3]),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
 
 
 
 
dffe #(8) dffe_resum_err3_tail (
 
dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_resum_err3_tail (
 
     .din (tlu_asi_queue_data_g[8-1:0]),
 
     .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .q   (resum_err3_tail[8-1:0]),
 
     .q   (resum_err3_tail[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .en  (resum_err_tail_wr_g[3]),
 
     .en  (resum_err_tail_wr_g[3]),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
 
 
 
 
dffe #(8) dffe_nresum_err3_head (
 
dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_nresum_err3_head (
 
     .din (tlu_asi_queue_data_g[8-1:0]),
 
     .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .q   (nresum_err3_head[8-1:0]),
 
     .q   (nresum_err3_head[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .en  (nresum_err_head_wr_g[3]),
 
     .en  (nresum_err_head_wr_g[3]),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
 
 
 
 
dffe #(8) dffe_nresum_err3_tail (
 
dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_nresum_err3_tail (
 
     .din (tlu_asi_queue_data_g[8-1:0]),
 
     .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .q   (nresum_err3_tail[8-1:0]),
 
     .q   (nresum_err3_tail[`TLU_ASI_QUE_WIDTH-1:0]),
 
     .en  (nresum_err_tail_wr_g[3]),
 
     .en  (nresum_err_tail_wr_g[3]),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
//
 
//
 
// reading out the asi queues 
// reading out the asi queues 
// 
// 
// added for bug2332
 
// added for bug2332
 
// assign cpu_mondo_hd_onehot_g = 
// assign cpu_mondo_hd_onehot_g = 
//            ~(|cpu_mondo_head_rd_g[3:1]);
 
//            ~(|cpu_mondo_head_rd_g[3:1]);
 
// cpu_mondo_head
 
// cpu_mondo_head
 
mux4ds #(8) mx_cpu_mondo_head (
 
mux4ds #(`TLU_ASI_QUE_WIDTH) mx_cpu_mondo_head (
 
    .in0  (cpu_mondo0_head[8-1:0]),
 
    .in0  (cpu_mondo0_head[`TLU_ASI_QUE_WIDTH-1:0]),
 
    .in1  (cpu_mondo1_head[8-1:0]),
 
    .in1  (cpu_mondo1_head[`TLU_ASI_QUE_WIDTH-1:0]),
 
    .in2  (cpu_mondo2_head[8-1:0]),
 
    .in2  (cpu_mondo2_head[`TLU_ASI_QUE_WIDTH-1:0]),
 
    .in3  (cpu_mondo3_head[8-1:0]),
 
    .in3  (cpu_mondo3_head[`TLU_ASI_QUE_WIDTH-1:0]),
 
    .sel0 (cpu_mondo_head_rd_g[0]),
 
    .sel0 (cpu_mondo_head_rd_g[0]),
 
    .sel1 (cpu_mondo_head_rd_g[1]),
 
    .sel1 (cpu_mondo_head_rd_g[1]),
 
    .sel2 (cpu_mondo_head_rd_g[2]),
 
    .sel2 (cpu_mondo_head_rd_g[2]),
 
    .sel3 (cpu_mondo_head_rd_g[3]),
 
    .sel3 (cpu_mondo_head_rd_g[3]),
 
    .dout (cpu_mondo_hd_rdata[8-1:0])
 
    .dout (cpu_mondo_hd_rdata[`TLU_ASI_QUE_WIDTH-1:0])
 
);
 
);
 
//
 
//
 
// added for bug2332
 
// added for bug2332
 
// assign cpu_mondo_ta_onehot_g = 
// assign cpu_mondo_ta_onehot_g = 
//            ~(|cpu_mondo_tail_rd_g[3:1]);
 
//            ~(|cpu_mondo_tail_rd_g[3:1]);
 
// cpu_mondo_tail
 
// cpu_mondo_tail
 
mux4ds #(8) mx_cpu_mondo_tail (
 
mux4ds #(`TLU_ASI_QUE_WIDTH) mx_cpu_mondo_tail (
 
    .in0  (cpu_mondo0_tail[8-1:0]),
 
    .in0  (cpu_mondo0_tail[`TLU_ASI_QUE_WIDTH-1:0]),
 
    .in1  (cpu_mondo1_tail[8-1:0]),
 
    .in1  (cpu_mondo1_tail[`TLU_ASI_QUE_WIDTH-1:0]),
 
    .in2  (cpu_mondo2_tail[8-1:0]),
 
    .in2  (cpu_mondo2_tail[`TLU_ASI_QUE_WIDTH-1:0]),
 
    .in3  (cpu_mondo3_tail[8-1:0]),
 
    .in3  (cpu_mondo3_tail[`TLU_ASI_QUE_WIDTH-1:0]),
 
    .sel0 (cpu_mondo_tail_rd_g[0]),
 
    .sel0 (cpu_mondo_tail_rd_g[0]),
 
    .sel1 (cpu_mondo_tail_rd_g[1]),
 
    .sel1 (cpu_mondo_tail_rd_g[1]),
 
    .sel2 (cpu_mondo_tail_rd_g[2]),
 
    .sel2 (cpu_mondo_tail_rd_g[2]),
 
    .sel3 (cpu_mondo_tail_rd_g[3]),
 
    .sel3 (cpu_mondo_tail_rd_g[3]),
 
    .dout (cpu_mondo_ta_rdata[8-1:0])
 
    .dout (cpu_mondo_ta_rdata[`TLU_ASI_QUE_WIDTH-1:0])
 
);
 
);
 
//
 
//
 
// added for bug2332
 
// added for bug2332
 
// assign dev_mondo_hd_onehot_g = 
// assign dev_mondo_hd_onehot_g = 
//            ~(|dev_mondo_head_rd_g[3:1]);
 
//            ~(|dev_mondo_head_rd_g[3:1]);
 
// dev_mondo_head
 
// dev_mondo_head
 
mux4ds #(8) mx_dev_mondo_head (
 
mux4ds #(`TLU_ASI_QUE_WIDTH) mx_dev_mondo_head (
 
    .in0  (dev_mondo0_head[8-1:0]),
 
    .in0  (dev_mondo0_head[`TLU_ASI_QUE_WIDTH-1:0]),
 
    .in1  (dev_mondo1_head[8-1:0]),
 
    .in1  (dev_mondo1_head[`TLU_ASI_QUE_WIDTH-1:0]),
 
    .in2  (dev_mondo2_head[8-1:0]),
 
    .in2  (dev_mondo2_head[`TLU_ASI_QUE_WIDTH-1:0]),
 
    .in3  (dev_mondo3_head[8-1:0]),
 
    .in3  (dev_mondo3_head[`TLU_ASI_QUE_WIDTH-1:0]),
 
    .sel0 (dev_mondo_head_rd_g[0]),
 
    .sel0 (dev_mondo_head_rd_g[0]),
 
    .sel1 (dev_mondo_head_rd_g[1]),
 
    .sel1 (dev_mondo_head_rd_g[1]),
 
    .sel2 (dev_mondo_head_rd_g[2]),
 
    .sel2 (dev_mondo_head_rd_g[2]),
 
    .sel3 (dev_mondo_head_rd_g[3]),
 
    .sel3 (dev_mondo_head_rd_g[3]),
 
    .dout (dev_mondo_hd_rdata[8-1:0])
 
    .dout (dev_mondo_hd_rdata[`TLU_ASI_QUE_WIDTH-1:0])
 
);
 
);
 
//
 
//
 
// added for bug2332
 
// added for bug2332
 
// assign dev_mondo_ta_onehot_g = 
// assign dev_mondo_ta_onehot_g = 
//            ~(|dev_mondo_tail_rd_g[3:1]);
 
//            ~(|dev_mondo_tail_rd_g[3:1]);
 
// dev_mondo_tail
 
// dev_mondo_tail
 
mux4ds #(8) mx_dev_mondo_tail (
 
mux4ds #(`TLU_ASI_QUE_WIDTH) mx_dev_mondo_tail (
 
    .in0  (dev_mondo0_tail[8-1:0]),
 
    .in0  (dev_mondo0_tail[`TLU_ASI_QUE_WIDTH-1:0]),
 
    .in1  (dev_mondo1_tail[8-1:0]),
 
    .in1  (dev_mondo1_tail[`TLU_ASI_QUE_WIDTH-1:0]),
 
    .in2  (dev_mondo2_tail[8-1:0]),
 
    .in2  (dev_mondo2_tail[`TLU_ASI_QUE_WIDTH-1:0]),
 
    .in3  (dev_mondo3_tail[8-1:0]),
 
    .in3  (dev_mondo3_tail[`TLU_ASI_QUE_WIDTH-1:0]),
 
    .sel0 (dev_mondo_tail_rd_g[0]),
 
    .sel0 (dev_mondo_tail_rd_g[0]),
 
    .sel1 (dev_mondo_tail_rd_g[1]),
 
    .sel1 (dev_mondo_tail_rd_g[1]),
 
    .sel2 (dev_mondo_tail_rd_g[2]),
 
    .sel2 (dev_mondo_tail_rd_g[2]),
 
    .sel3 (dev_mondo_tail_rd_g[3]),
 
    .sel3 (dev_mondo_tail_rd_g[3]),
 
    .dout (dev_mondo_ta_rdata[8-1:0])
 
    .dout (dev_mondo_ta_rdata[`TLU_ASI_QUE_WIDTH-1:0])
 
);
 
);
 
//
 
//
 
// added for bug2332
 
// added for bug2332
 
// assign resum_err_hd_onehot_g = 
// assign resum_err_hd_onehot_g = 
//            ~(|resum_err_head_rd_g[3:1]);
 
//            ~(|resum_err_head_rd_g[3:1]);
 
// resum_err_head
 
// resum_err_head
 
mux4ds #(8) mx_resum_err_head (
 
mux4ds #(`TLU_ASI_QUE_WIDTH) mx_resum_err_head (
 
    .in0  (resum_err0_head[8-1:0]),
 
    .in0  (resum_err0_head[`TLU_ASI_QUE_WIDTH-1:0]),
 
    .in1  (resum_err1_head[8-1:0]),
 
    .in1  (resum_err1_head[`TLU_ASI_QUE_WIDTH-1:0]),
 
    .in2  (resum_err2_head[8-1:0]),
 
    .in2  (resum_err2_head[`TLU_ASI_QUE_WIDTH-1:0]),
 
    .in3  (resum_err3_head[8-1:0]),
 
    .in3  (resum_err3_head[`TLU_ASI_QUE_WIDTH-1:0]),
 
    .sel0 (resum_err_head_rd_g[0]),
 
    .sel0 (resum_err_head_rd_g[0]),
 
    .sel1 (resum_err_head_rd_g[1]),
 
    .sel1 (resum_err_head_rd_g[1]),
 
    .sel2 (resum_err_head_rd_g[2]),
 
    .sel2 (resum_err_head_rd_g[2]),
 
    .sel3 (resum_err_head_rd_g[3]),
 
    .sel3 (resum_err_head_rd_g[3]),
 
    .dout (resum_err_hd_rdata[8-1:0])
 
    .dout (resum_err_hd_rdata[`TLU_ASI_QUE_WIDTH-1:0])
 
);
 
);
 
//
 
//
 
// added for bug2332
 
// added for bug2332
 
// assign resum_err_ta_onehot_g = 
// assign resum_err_ta_onehot_g = 
//            ~(|resum_err_tail_rd_g[3:1]);
 
//            ~(|resum_err_tail_rd_g[3:1]);
 
// resum_err_tail
 
// resum_err_tail
 
mux4ds #(8) mx_resum_err_tail (
 
mux4ds #(`TLU_ASI_QUE_WIDTH) mx_resum_err_tail (
 
    .in0  (resum_err0_tail[8-1:0]),
 
    .in0  (resum_err0_tail[`TLU_ASI_QUE_WIDTH-1:0]),
 
    .in1  (resum_err1_tail[8-1:0]),
 
    .in1  (resum_err1_tail[`TLU_ASI_QUE_WIDTH-1:0]),
 
    .in2  (resum_err2_tail[8-1:0]),
 
    .in2  (resum_err2_tail[`TLU_ASI_QUE_WIDTH-1:0]),
 
    .in3  (resum_err3_tail[8-1:0]),
 
    .in3  (resum_err3_tail[`TLU_ASI_QUE_WIDTH-1:0]),
 
    .sel0 (resum_err_tail_rd_g[0]),
 
    .sel0 (resum_err_tail_rd_g[0]),
 
    .sel1 (resum_err_tail_rd_g[1]),
 
    .sel1 (resum_err_tail_rd_g[1]),
 
    .sel2 (resum_err_tail_rd_g[2]),
 
    .sel2 (resum_err_tail_rd_g[2]),
 
    .sel3 (resum_err_tail_rd_g[3]),
 
    .sel3 (resum_err_tail_rd_g[3]),
 
    .dout (resum_err_ta_rdata[8-1:0])
 
    .dout (resum_err_ta_rdata[`TLU_ASI_QUE_WIDTH-1:0])
 
);
 
);
 
//
 
//
 
// added for bug2332
 
// added for bug2332
 
// assign nresum_err_hd_onehot_g = 
// assign nresum_err_hd_onehot_g = 
//            ~(|nresum_err_head_rd_g[3:1]);
 
//            ~(|nresum_err_head_rd_g[3:1]);
 
// nresum_err_head
 
// nresum_err_head
 
mux4ds #(8) mx_nresum_err_head (
 
mux4ds #(`TLU_ASI_QUE_WIDTH) mx_nresum_err_head (
 
    .in0  (nresum_err0_head[8-1:0]),
 
    .in0  (nresum_err0_head[`TLU_ASI_QUE_WIDTH-1:0]),
 
    .in1  (nresum_err1_head[8-1:0]),
 
    .in1  (nresum_err1_head[`TLU_ASI_QUE_WIDTH-1:0]),
 
    .in2  (nresum_err2_head[8-1:0]),
 
    .in2  (nresum_err2_head[`TLU_ASI_QUE_WIDTH-1:0]),
 
    .in3  (nresum_err3_head[8-1:0]),
 
    .in3  (nresum_err3_head[`TLU_ASI_QUE_WIDTH-1:0]),
 
    .sel0 (nresum_err_head_rd_g[0]),
 
    .sel0 (nresum_err_head_rd_g[0]),
 
    .sel1 (nresum_err_head_rd_g[1]),
 
    .sel1 (nresum_err_head_rd_g[1]),
 
    .sel2 (nresum_err_head_rd_g[2]),
 
    .sel2 (nresum_err_head_rd_g[2]),
 
    .sel3 (nresum_err_head_rd_g[3]),
 
    .sel3 (nresum_err_head_rd_g[3]),
 
    .dout (nresum_err_hd_rdata[8-1:0])
 
    .dout (nresum_err_hd_rdata[`TLU_ASI_QUE_WIDTH-1:0])
 
);
 
);
 
//
 
//
 
// added for bug2332
 
// added for bug2332
 
// assign nresum_err_ta_onehot_g = 
// assign nresum_err_ta_onehot_g = 
//            ~(|nresum_err_tail_rd_g[3:1]);
 
//            ~(|nresum_err_tail_rd_g[3:1]);
 
// nresum_err_tail
 
// nresum_err_tail
 
mux4ds #(8) mx_nresum_err_tail (
 
mux4ds #(`TLU_ASI_QUE_WIDTH) mx_nresum_err_tail (
 
    .in0  (nresum_err0_tail[8-1:0]),
 
    .in0  (nresum_err0_tail[`TLU_ASI_QUE_WIDTH-1:0]),
 
    .in1  (nresum_err1_tail[8-1:0]),
 
    .in1  (nresum_err1_tail[`TLU_ASI_QUE_WIDTH-1:0]),
 
    .in2  (nresum_err2_tail[8-1:0]),
 
    .in2  (nresum_err2_tail[`TLU_ASI_QUE_WIDTH-1:0]),
 
    .in3  (nresum_err3_tail[8-1:0]),
 
    .in3  (nresum_err3_tail[`TLU_ASI_QUE_WIDTH-1:0]),
 
    .sel0 (nresum_err_tail_rd_g[0]),
 
    .sel0 (nresum_err_tail_rd_g[0]),
 
    .sel1 (nresum_err_tail_rd_g[1]),
 
    .sel1 (nresum_err_tail_rd_g[1]),
 
    .sel2 (nresum_err_tail_rd_g[2]),
 
    .sel2 (nresum_err_tail_rd_g[2]),
 
    .sel3 (nresum_err_tail_rd_g[3]),
 
    .sel3 (nresum_err_tail_rd_g[3]),
 
    .dout (nresum_err_ta_rdata[8-1:0])
 
    .dout (nresum_err_ta_rdata[`TLU_ASI_QUE_WIDTH-1:0])
 
);
 
);
 
// 
// 
// added for bug 2332
 
// added for bug 2332
 
assign asi_qrdata_mx1_sel[0] = cpu_mondo_hd_rd_g |
 
assign asi_qrdata_mx1_sel[0] = cpu_mondo_hd_rd_g |
 
                               ~(|asi_qrdata_mx1_sel[3:1]);
 
                               ~(|asi_qrdata_mx1_sel[3:1]);
 
assign asi_qrdata_mx1_sel[1] = cpu_mondo_ta_rd_g;
 
assign asi_qrdata_mx1_sel[1] = cpu_mondo_ta_rd_g;
 
assign asi_qrdata_mx1_sel[2] = dev_mondo_hd_rd_g;
 
assign asi_qrdata_mx1_sel[2] = dev_mondo_hd_rd_g;
 
assign asi_qrdata_mx1_sel[3] = dev_mondo_ta_rd_g;
 
assign asi_qrdata_mx1_sel[3] = dev_mondo_ta_rd_g;
 
// 
// 
// selecting between the eight queues
 
// selecting between the eight queues
 
mux4ds #(8) mx1_asi_queue_rdata (
 
mux4ds #(`TLU_ASI_QUE_WIDTH) mx1_asi_queue_rdata (
 
    .in0  (cpu_mondo_hd_rdata[8-1:0]),
 
    .in0  (cpu_mondo_hd_rdata[`TLU_ASI_QUE_WIDTH-1:0]),
 
    .in1  (cpu_mondo_ta_rdata[8-1:0]),
 
    .in1  (cpu_mondo_ta_rdata[`TLU_ASI_QUE_WIDTH-1:0]),
 
    .in2  (dev_mondo_hd_rdata[8-1:0]),
 
    .in2  (dev_mondo_hd_rdata[`TLU_ASI_QUE_WIDTH-1:0]),
 
    .in3  (dev_mondo_ta_rdata[8-1:0]),
 
    .in3  (dev_mondo_ta_rdata[`TLU_ASI_QUE_WIDTH-1:0]),
 
    .sel0 (asi_qrdata_mx1_sel[0]),
 
    .sel0 (asi_qrdata_mx1_sel[0]),
 
    .sel1 (asi_qrdata_mx1_sel[1]),
 
    .sel1 (asi_qrdata_mx1_sel[1]),
 
    .sel2 (asi_qrdata_mx1_sel[2]),
 
    .sel2 (asi_qrdata_mx1_sel[2]),
 
    .sel3 (asi_qrdata_mx1_sel[3]),
 
    .sel3 (asi_qrdata_mx1_sel[3]),
 
    .dout (asi_queue_rdata1_g[8-1:0])
 
    .dout (asi_queue_rdata1_g[`TLU_ASI_QUE_WIDTH-1:0])
 
);
 
);
 
// 
// 
// added for bug 2332
 
// added for bug 2332
 
assign asi_qrdata_mx2_sel[0] = resum_err_hd_rd_g |
 
assign asi_qrdata_mx2_sel[0] = resum_err_hd_rd_g |
 
                               ~(|asi_qrdata_mx2_sel[3:1]);
 
                               ~(|asi_qrdata_mx2_sel[3:1]);
 
assign asi_qrdata_mx2_sel[1] = resum_err_ta_rd_g;
 
assign asi_qrdata_mx2_sel[1] = resum_err_ta_rd_g;
 
assign asi_qrdata_mx2_sel[2] = nresum_err_hd_rd_g;
 
assign asi_qrdata_mx2_sel[2] = nresum_err_hd_rd_g;
 
assign asi_qrdata_mx2_sel[3] = nresum_err_ta_rd_g;
 
assign asi_qrdata_mx2_sel[3] = nresum_err_ta_rd_g;
 
 
 
 
 
mux4ds #(8) mx2_asi_queue_rdata (
 
mux4ds #(`TLU_ASI_QUE_WIDTH) mx2_asi_queue_rdata (
 
    .in0  (resum_err_hd_rdata[8-1:0]),
 
    .in0  (resum_err_hd_rdata[`TLU_ASI_QUE_WIDTH-1:0]),
 
    .in1  (resum_err_ta_rdata[8-1:0]),
 
    .in1  (resum_err_ta_rdata[`TLU_ASI_QUE_WIDTH-1:0]),
 
    .in2  (nresum_err_hd_rdata[8-1:0]),
 
    .in2  (nresum_err_hd_rdata[`TLU_ASI_QUE_WIDTH-1:0]),
 
    .in3  (nresum_err_ta_rdata[8-1:0]),
 
    .in3  (nresum_err_ta_rdata[`TLU_ASI_QUE_WIDTH-1:0]),
 
    .sel0 (asi_qrdata_mx2_sel[0]),
 
    .sel0 (asi_qrdata_mx2_sel[0]),
 
    .sel1 (asi_qrdata_mx2_sel[1]),
 
    .sel1 (asi_qrdata_mx2_sel[1]),
 
    .sel2 (asi_qrdata_mx2_sel[2]),
 
    .sel2 (asi_qrdata_mx2_sel[2]),
 
    .sel3 (asi_qrdata_mx2_sel[3]),
 
    .sel3 (asi_qrdata_mx2_sel[3]),
 
    .dout (asi_queue_rdata2_g[8-1:0])
 
    .dout (asi_queue_rdata2_g[`TLU_ASI_QUE_WIDTH-1:0])
 
);
 
);
 
//
 
//
 
// constructing the select for the final asi queue rdata output
 
// constructing the select for the final asi queue rdata output
 
assign asi_qrdata_mx_sel2 =
 
assign asi_qrdata_mx_sel2 =
 
           resum_err_hd_rd_g  | resum_err_ta_rd_g |
 
           resum_err_hd_rd_g  | resum_err_ta_rd_g |
 
           nresum_err_hd_rd_g | nresum_err_ta_rd_g;
 
           nresum_err_hd_rd_g | nresum_err_ta_rd_g;
 
//
 
//
 
mux2ds #(8) mx_tlu_asi_queue_rdata (
 
mux2ds #(`TLU_ASI_QUE_WIDTH) mx_tlu_asi_queue_rdata (
 
    .in0  (asi_queue_rdata2_g[8-1:0]),
 
    .in0  (asi_queue_rdata2_g[`TLU_ASI_QUE_WIDTH-1:0]),
 
    .in1  (asi_queue_rdata1_g[8-1:0]),
 
    .in1  (asi_queue_rdata1_g[`TLU_ASI_QUE_WIDTH-1:0]),
 
    .sel0 (asi_qrdata_mx_sel2),
 
    .sel0 (asi_qrdata_mx_sel2),
 
    .sel1 (~asi_qrdata_mx_sel2),
 
    .sel1 (~asi_qrdata_mx_sel2),
 
    .dout (tlu_asi_queue_rdata_g[8-1:0])
 
    .dout (tlu_asi_queue_rdata_g[`TLU_ASI_QUE_WIDTH-1:0])
 
);
 
);
 
//
 
//
 
// forming the valid signal for the asi queue rdata
 
// forming the valid signal for the asi queue rdata
 
assign tlu_asi_queue_rd_vld_g =
 
assign tlu_asi_queue_rd_vld_g =
 
       asi_qrdata_mx_sel2 | cpu_mondo_hd_rd_g | cpu_mondo_ta_rd_g |
 
       asi_qrdata_mx_sel2 | cpu_mondo_hd_rd_g | cpu_mondo_ta_rd_g |
Line 3723... Line 3053... 
////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////
 
//
 
//
 
// privileged scratch pad access
 
// privileged scratch pad access
 
assign asi_scpd_rw_e =
 
assign asi_scpd_rw_e =
 
           ifu_lsu_alt_space_e &
 
           ifu_lsu_alt_space_e &
 
          (tlu_asi_state_e[8-1:0]==8'h20);
 
          (tlu_asi_state_e[`TLU_ASI_STATE_WIDTH-1:0]==`PRI_SCPD_ASI_STATE);
 
 
 
 
 
// hyprivileged scratch pad access
 
// hyprivileged scratch pad access
 
assign asi_hscpd_rw_e =
 
assign asi_hscpd_rw_e =
 
           ifu_lsu_alt_space_e &
 
           ifu_lsu_alt_space_e &
 
          (tlu_asi_state_e[8-1:0]==8'h4f);
 
          (tlu_asi_state_e[`TLU_ASI_STATE_WIDTH-1:0]==`HPRI_SCPD_ASI_STATE);
 
//
 
//
 
// staged the scpd/hscpd rw ctls
 
// staged the scpd/hscpd rw ctls
 
dffr #(2) dffr_asi_scpd_rw_ctls (
 
dffr_s #(2) dffr_asi_scpd_rw_ctls (
 
    .din ({asi_hscpd_rw_e, asi_scpd_rw_e}),
 
    .din ({asi_hscpd_rw_e, asi_scpd_rw_e}),
 
    .q   ({asi_hscpd_rw_m, asi_scpd_rw_m}),
 
    .q   ({asi_hscpd_rw_m, asi_scpd_rw_m}),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
// address generation
 
// address generation
 
//
 
//
Line 3751... Line 3081... 
            tlu_ldst_va_e[`TLU_ASI_SCPD_VA_HI:`TLU_ASI_SCPD_VA_LO];
 
            tlu_ldst_va_e[`TLU_ASI_SCPD_VA_HI:`TLU_ASI_SCPD_VA_LO];
 
 
 
 
 
 staged the shifted va address
 
 staged the shifted va address
 
 modified due to timing fix
 
 modified due to timing fix
 
 
 
 
 
dff #(`SCPD_ASI_VA_ADDR_WIDTH) dff_scpd_addr_va_m (
 
dff_s #(`SCPD_ASI_VA_ADDR_WIDTH) dff_scpd_addr_va_m (
 
    .din (scpd_addr_va_e[`SCPD_ASI_VA_ADDR_WIDTH-1:0]),
 
    .din (scpd_addr_va_e[`SCPD_ASI_VA_ADDR_WIDTH-1:0]),
 
    .q   (scpd_addr_va_m[`SCPD_ASI_VA_ADDR_WIDTH-1:0]),
 
    .q   (scpd_addr_va_m[`SCPD_ASI_VA_ADDR_WIDTH-1:0]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
*/
 
*/
 
 
 
 
 
assign scpd_addr_va_m[3-1:0] =
 
assign scpd_addr_va_m[`SCPD_ASI_VA_ADDR_WIDTH-1:0] =
 
            tlu_ldst_va_m[5:3];
 
            tlu_ldst_va_m[`TLU_ASI_SCPD_VA_HI:`TLU_ASI_SCPD_VA_LO];
 
 
 
 
 
dff #(3) dff_scpd_addr_va_g (
 
dff_s #(`SCPD_ASI_VA_ADDR_WIDTH) dff_scpd_addr_va_g (
 
    .din (scpd_addr_va_m[3-1:0]),
 
    .din (scpd_addr_va_m[`SCPD_ASI_VA_ADDR_WIDTH-1:0]),
 
    .q   (scpd_addr_va_g[3-1:0]),
 
    .q   (scpd_addr_va_g[`SCPD_ASI_VA_ADDR_WIDTH-1:0]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
assign tlu_scpd_rd_addr_m[5-1:0] =
 
assign tlu_scpd_rd_addr_m[`SCPD_RW_ADDR_WIDTH-1:0] =
 
           {thrid_m[1:0], scpd_addr_va_m[3-1:0]};
 
           {thrid_m[1:0], scpd_addr_va_m[`SCPD_ASI_VA_ADDR_WIDTH-1:0]};
 
 
 
 
 
assign tlu_scpd_wr_addr_g[5-1:0] =
 
assign tlu_scpd_wr_addr_g[`SCPD_RW_ADDR_WIDTH-1:0] =
 
           {thrid_g[1:0], scpd_addr_va_g[3-1:0]};
 
           {thrid_g[1:0], scpd_addr_va_g[`SCPD_ASI_VA_ADDR_WIDTH-1:0]};
 
//
 
//
 
// illegal range check for scratch-pd va 
// illegal range check for scratch-pd va 
// modified due to timing
 
// modified due to timing
 
/*
 
/*
 
assign scpd_ill_va_e =
 
assign scpd_ill_va_e =
Line 3789... Line 3119... 
           ((asi_scpd_rw_e | asi_hscpd_rw_e) &
 
           ((asi_scpd_rw_e | asi_hscpd_rw_e) &
 
           ((|exu_lsu_ldst_va_e[`ASI_VA_WIDTH-1:`TLU_ASI_SCPD_VA_HI+1]) |
 
           ((|exu_lsu_ldst_va_e[`ASI_VA_WIDTH-1:`TLU_ASI_SCPD_VA_HI+1]) |
 
            (|exu_lsu_ldst_va_e[`TLU_ASI_SCPD_VA_LO-1:0]))) :
 
            (|exu_lsu_ldst_va_e[`TLU_ASI_SCPD_VA_LO-1:0]))) :
 
            1'b0;
 
            1'b0;
 
// staged illegal va range
 
// staged illegal va range
 
dffr dffr_scpd_ill_va_m (
 
dffr_s dffr_scpd_ill_va_m (
 
    .din (scpd_ill_va_e),
 
    .din (scpd_ill_va_e),
 
    .q   (scpd_ill_va_m),
 
    .q   (scpd_ill_va_m),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
*/
 
*/
 
//
 
//
 
assign va_not_baligned_m = (|tlu_ldst_va_m[3-1:0]);
 
assign va_not_baligned_m = (|tlu_ldst_va_m[`TLU_ASI_SCPD_VA_LO-1:0]);
 
assign scpd_ill_va_m =
 
assign scpd_ill_va_m =
 
           (asi_scpd_rw_m | asi_hscpd_rw_m) &
 
           (asi_scpd_rw_m | asi_hscpd_rw_m) &
 
            va_not_baligned_m;
 
            va_not_baligned_m;
 
 
 
 
 
// 
// 
dffr dffr_scpd_ill_va_g (
 
dffr_s dffr_scpd_ill_va_g (
 
    .din (scpd_ill_va_m),
 
    .din (scpd_ill_va_m),
 
    .q   (scpd_ill_va_g),
 
    .q   (scpd_ill_va_g),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
//
 
//
 
// generating read and write valid 
// generating read and write valid 
assign asi_scpd_rw_vld_m =
 
assign asi_scpd_rw_vld_m =
 
            (asi_scpd_rw_m | asi_hscpd_rw_m) &
 
            (asi_scpd_rw_m | asi_hscpd_rw_m) &
 
           ~(hscpd_data_acc_excpt_m | va_not_baligned_m);
 
           ~(hscpd_data_acc_excpt_m | va_not_baligned_m);
 
 
 
 
 
dffr dffr_asi_scpd_rw_vld_g (
 
dffr_s dffr_asi_scpd_rw_vld_g (
 
    .din (asi_scpd_rw_vld_m),
 
    .din (asi_scpd_rw_vld_m),
 
    .q   (asi_scpd_rw_vld_g),
 
    .q   (asi_scpd_rw_vld_g),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
assign tlu_scpd_wr_vld_g =
 
assign tlu_scpd_wr_vld_g =
 
           asi_queue_write_g & asi_scpd_rw_vld_g;
 
           asi_queue_write_g & asi_scpd_rw_vld_g;
Line 3847... Line 3177... 
// assign tlu_scpd_rd_vld_g = 
// assign tlu_scpd_rd_vld_g = 
//            asi_queue_read_g & asi_scpd_rw_vld_g; 
//            asi_queue_read_g & asi_scpd_rw_vld_g; 
 
 
 
 
// decoding for hypervisor only scratch-pad
 
// decoding for hypervisor only scratch-pad
 
assign hscpd_va_rw_m =
 
assign hscpd_va_rw_m =
 
          ((scpd_addr_va_m[3-1:0] ==
 
          ((scpd_addr_va_m[`SCPD_ASI_VA_ADDR_WIDTH-1:0] ==
 
            3'h4) |
 
            `HSCPD_ASI_VA_ADDR_LO) |
 
           (scpd_addr_va_m[3-1:0] ==
 
           (scpd_addr_va_m[`SCPD_ASI_VA_ADDR_WIDTH-1:0] ==
 
            3'h5));
 
            `HSCPD_ASI_VA_ADDR_HI));
 
 
 
 
 
////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////
 
// Potential trap indicators 
// Potential trap indicators 
////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////
 
// possible traps are: 
// possible traps are:
Line 3903... Line 3233... 
             asi_queue_read_m & (asi_queue_rw_m |
 
             asi_queue_read_m & (asi_queue_rw_m |
 
           ((asi_hscpd_rw_m | asi_scpd_rw_m) &
 
           ((asi_hscpd_rw_m | asi_scpd_rw_m) &
 
            ~hscpd_data_acc_excpt_m));
 
            ~hscpd_data_acc_excpt_m));
 
 
 
 
 
// staging the ld address valid 
// staging the ld address valid 
dffr dffr_asi_ld_addr_vld_g (
 
dffr_s dffr_asi_ld_addr_vld_g (
 
    .din (asi_ld_addr_vld_m),
 
    .din (asi_ld_addr_vld_m),
 
    .q   (asi_ld_addr_vld_g),
 
    .q   (asi_ld_addr_vld_g),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
//
 
//
 
// redefined va illegal checking - the following code is 
// redefined va illegal checking - the following code is 
// no longer necessary
 
// no longer necessary
Line 3922... Line 3252... 
assign va_all_zero_e =
 
assign va_all_zero_e =
 
            (~(|exu_lsu_ldst_va_e[`ASI_VA_WIDTH-1:0])) &
 
            (~(|exu_lsu_ldst_va_e[`ASI_VA_WIDTH-1:0])) &
 
             asi_queue_read_g;
 
             asi_queue_read_g;
 
//
 
//
 
// staged illegal va range
 
// staged illegal va range
 
dffr dffr_va_all_zero_m (
 
dffr_s dffr_va_all_zero_m (
 
    .din (va_all_zero_e),
 
    .din (va_all_zero_e),
 
    .q   (va_all_zero_m),
 
    .q   (va_all_zero_m),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
//
 
//
 
dffr dffr_va_all_zero_g (
 
dffr_s dffr_va_all_zero_g (
 
    .din (va_all_zero_m),
 
    .din (va_all_zero_m),
 
    .q   (va_all_zero_g),
 
    .q   (va_all_zero_g),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
assign tlu_va_all_zero_g = va_all_zero_g;
 
assign tlu_va_all_zero_g = va_all_zero_g;
 
*/
 
*/
Line 3953... Line 3283... 
// note: these traps are level-sensitive
 
// note: these traps are level-sensitive
 
//
 
//
 
// thread 0
 
// thread 0
 
 
 
 
 
assign tlu_cpu_mondo_cmp[0] =
 
assign tlu_cpu_mondo_cmp[0] =
 
           (|(cpu_mondo0_head[8-1:0] ^
 
           (|(cpu_mondo0_head[`TLU_ASI_QUE_WIDTH-1:0] ^
 
              cpu_mondo0_tail[8-1:0]));
 
              cpu_mondo0_tail[`TLU_ASI_QUE_WIDTH-1:0]));
 
assign tlu_dev_mondo_cmp[0]=
 
assign tlu_dev_mondo_cmp[0]=
 
           (|(dev_mondo0_head[8-1:0] ^
 
           (|(dev_mondo0_head[`TLU_ASI_QUE_WIDTH-1:0] ^
 
              dev_mondo0_tail[8-1:0]));
 
              dev_mondo0_tail[`TLU_ASI_QUE_WIDTH-1:0]));
 
assign tlu_resum_err_cmp[0] =
 
assign tlu_resum_err_cmp[0] =
 
           (|(resum_err0_head[8-1:0] ^
 
           (|(resum_err0_head[`TLU_ASI_QUE_WIDTH-1:0] ^
 
              resum_err0_tail[8-1:0]));
 
              resum_err0_tail[`TLU_ASI_QUE_WIDTH-1:0]));
 
// thread 1
 
// thread 1
 
 
 
 
 
assign tlu_cpu_mondo_cmp[1] =
 
assign tlu_cpu_mondo_cmp[1] =
 
           (|(cpu_mondo1_head[8-1:0] ^
 
           (|(cpu_mondo1_head[`TLU_ASI_QUE_WIDTH-1:0] ^
 
              cpu_mondo1_tail[8-1:0]));
 
              cpu_mondo1_tail[`TLU_ASI_QUE_WIDTH-1:0]));
 
assign tlu_dev_mondo_cmp[1]=
 
assign tlu_dev_mondo_cmp[1]=
 
           (|(dev_mondo1_head[8-1:0] ^
 
           (|(dev_mondo1_head[`TLU_ASI_QUE_WIDTH-1:0] ^
 
              dev_mondo1_tail[8-1:0]));
 
              dev_mondo1_tail[`TLU_ASI_QUE_WIDTH-1:0]));
 
assign tlu_resum_err_cmp[1] =
 
assign tlu_resum_err_cmp[1] =
 
           (|(resum_err1_head[8-1:0] ^
 
           (|(resum_err1_head[`TLU_ASI_QUE_WIDTH-1:0] ^
 
              resum_err1_tail[8-1:0]));
 
              resum_err1_tail[`TLU_ASI_QUE_WIDTH-1:0]));
 
//
 
//
 
// thread 2
 
// thread 2
 
 
 
 
 
assign tlu_cpu_mondo_cmp[2] =
 
assign tlu_cpu_mondo_cmp[2] =
 
           (|(cpu_mondo2_head[8-1:0] ^
 
           (|(cpu_mondo2_head[`TLU_ASI_QUE_WIDTH-1:0] ^
 
              cpu_mondo2_tail[8-1:0]));
 
              cpu_mondo2_tail[`TLU_ASI_QUE_WIDTH-1:0]));
 
assign tlu_dev_mondo_cmp[2]=
 
assign tlu_dev_mondo_cmp[2]=
 
           (|(dev_mondo2_head[8-1:0] ^
 
           (|(dev_mondo2_head[`TLU_ASI_QUE_WIDTH-1:0] ^
 
              dev_mondo2_tail[8-1:0]));
 
              dev_mondo2_tail[`TLU_ASI_QUE_WIDTH-1:0]));
 
assign tlu_resum_err_cmp[2] =
 
assign tlu_resum_err_cmp[2] =
 
           (|(resum_err2_head[8-1:0] ^
 
           (|(resum_err2_head[`TLU_ASI_QUE_WIDTH-1:0] ^
 
              resum_err2_tail[8-1:0]));
 
              resum_err2_tail[`TLU_ASI_QUE_WIDTH-1:0]));
 
// thread 3
 
// thread 3
 
 
 
 
 
assign tlu_cpu_mondo_cmp[3] =
 
assign tlu_cpu_mondo_cmp[3] =
 
           (|(cpu_mondo3_head[8-1:0] ^
 
           (|(cpu_mondo3_head[`TLU_ASI_QUE_WIDTH-1:0] ^
 
              cpu_mondo3_tail[8-1:0]));
 
              cpu_mondo3_tail[`TLU_ASI_QUE_WIDTH-1:0]));
 
assign tlu_dev_mondo_cmp[3]=
 
assign tlu_dev_mondo_cmp[3]=
 
           (|(dev_mondo3_head[8-1:0] ^
 
           (|(dev_mondo3_head[`TLU_ASI_QUE_WIDTH-1:0] ^
 
              dev_mondo3_tail[8-1:0]));
 
              dev_mondo3_tail[`TLU_ASI_QUE_WIDTH-1:0]));
 
assign tlu_resum_err_cmp[3] =
 
assign tlu_resum_err_cmp[3] =
 
           (|(resum_err3_head[8-1:0] ^
 
           (|(resum_err3_head[`TLU_ASI_QUE_WIDTH-1:0] ^
 
              resum_err3_tail[8-1:0]));
 
              resum_err3_tail[`TLU_ASI_QUE_WIDTH-1:0]));
 
 
 
 
 
// write to tail by supervisor
 
// write to tail by supervisor
 
// modified due to timing - moved the inst_vld qualification to tlu_tcl
 
// modified due to timing - moved the inst_vld qualification to tlu_tcl
 
assign qtail_write_m =
 
assign qtail_write_m =
 
           (nresum_err_tail_rw_m | resum_err_tail_rw_m  |
 
           (nresum_err_tail_rw_m | resum_err_tail_rw_m  |

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