OpenCores

Line 16...

// You should have received a copy of the GNU General Public

// You should have received a copy of the GNU General Public

// License along with this work; if not, write to the Free Software

// License along with this work; if not, write to the Free Software

// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.

// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.

//

//

// ========== Copyright Header End ============================================

// ========== Copyright Header End ============================================

`ifdef SIMPLY_RISC_TWEAKS

`define SIMPLY_RISC_SCANIN .si(0)

`else

`define SIMPLY_RISC_SCANIN .si()

`endif

///////////////////////////////////////////////////////////////////////

///////////////////////////////////////////////////////////////////////

/*

/*

//      Description:    MMU Control - I & D.

//      Description:    MMU Control - I & D.

*/

*/

////////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////////

// Global header file includes

// Global header file includes

////////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////////

// system level definition file which contains the /*

`include        "sys.h" // system level definition file which contains the

/* ========== Copyright Header Begin ==========================================

* OpenSPARC T1 Processor File: sys.h

* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.

* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.

* The above named program is free software; you can redistribute it and/or

* modify it under the terms of the GNU General Public

* License version 2 as published by the Free Software Foundation.

* The above named program is distributed in the hope that it will be

* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of

* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

* General Public License for more details.

* You should have received a copy of the GNU General Public

* License along with this work; if not, write to the Free Software

* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.

* ========== Copyright Header End ============================================

*/

// -*- verilog -*-

////////////////////////////////////////////////////////////////////////

/*

//

// Description:         Global header file that contain definitions that

//                      are common/shared at the systme level

*/

////////////////////////////////////////////////////////////////////////

//

// Setting the time scale

// If the timescale changes, JP_TIMESCALE may also have to change.

`timescale      1ps/1ps

//

// JBUS clock

// =========

//

// Afara Link Defines

// ==================

// Reliable Link

// Afara Link Objects

// Afara Link Object Format - Reliable Link

// Afara Link Object Format - Congestion

// Afara Link Object Format - Acknowledge

// Afara Link Object Format - Request

// Afara Link Object Format - Message

// Acknowledge Types

// Request Types

// Afara Link Frame

//

// UCB Packet Type

// ===============

//

//

// UCB Data Packet Format

// ======================

//

// Size encoding for the UCB_SIZE_HI/LO field

// 000 - byte

// 001 - half-word

// 010 - word

// 011 - double-word

// 111 - quad-word

//

// UCB Interrupt Packet Format

// ===========================

//

//`define UCB_THR_HI             9      // (6) cpu/thread ID shared with

//`define UCB_THR_LO             4             data packet format

//`define UCB_PKT_HI             3      // (4) packet type shared with

//`define UCB_PKT_LO             0      //     data packet format

//

// FCRAM Bus Widths

// ================

//

//

// ENET clock periods

// ==================

//

//

// JBus Bridge defines

// =================

//

//

// PCI Device Address Configuration

// ================================

//

                                        // time scale definition

                                        // time scale definition

////////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////////

// Local header file includes / local defines

// Local header file includes / local defines

////////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////////

Line 568...

Line 296...

output                  so ;

output                  so ;

/*AUTOWIRE*/

/*AUTOWIRE*/

// Beginning of automatic wires (for undeclared instantiated-module outputs)

// Beginning of automatic wires (for undeclared instantiated-module outputs)

`ifdef SIMPLY_RISC_TWEAKS

wire alt_space_e;

`endif

// End of automatics

// End of automatics

reg                     dmmu_invalidate_all_en_m ;

reg                     dmmu_invalidate_all_en_m ;

reg                     immu_invalidate_all_en_m ;

reg                     immu_invalidate_all_en_m ;

reg     dmmu_decode_asi58_e ;

reg     dmmu_decode_asi58_e ;

Line 729...

Line 460...

    wire       rst_l;

    wire       rst_l;

    dffrl_async rstff(.din (grst_l),

    dffrl_async rstff(.din (grst_l),

                      .q   (rst_l),

                      .q   (rst_l),

                      .clk (clk), .se(se), .si(), .so(),

                      .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so(),

                      .rst_l (arst_l));

                      .rst_l (arst_l));

//=========================================================================================

//=========================================================================================

//      Early Flush Generation

//      Early Flush Generation

Line 741...

Line 472...

wire    ifu_tlu_flush_w ;

wire    ifu_tlu_flush_w ;

dff  #(1) stg_w (

dff_s  #(1) stg_w (

        .din    (ifu_tlu_flush_m),

        .din    (ifu_tlu_flush_m),

        .q      (ifu_tlu_flush_w),

        .q      (ifu_tlu_flush_w),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

) ;

) ;

wire    local_flush_w ;

wire    local_flush_w ;

assign  local_flush_w =

assign  local_flush_w =

Line 761...

Line 492...

wire    flush_w_inst_vld_m ;

wire    flush_w_inst_vld_m ;

assign  flush_w_inst_vld_m =

assign  flush_w_inst_vld_m =

        ifu_tlu_inst_vld_m &

        ifu_tlu_inst_vld_m &

        ~(lsu_mmu_flush_pipe_w & (thrid_m[1:0] == thrid_g[1:0])) ; // really lsu_flush_pipe_w

        ~(lsu_mmu_flush_pipe_w & (thrid_m[1:0] == thrid_g[1:0])) ; // really lsu_flush_pipe_w

dff  stgw_ivld (

dff_s  stgw_ivld (

        .din    (flush_w_inst_vld_m),

        .din    (flush_w_inst_vld_m),

        .q      (inst_vld_g),

        .q      (inst_vld_g),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

// Bug 4183

// Bug 4183

wire    priority_squash_m, priority_squash_g ;

wire    priority_squash_m, priority_squash_g ;

assign  priority_squash_m =

assign  priority_squash_m =

ifu_mmu_trap_m | ffu_tlu_ill_inst_m | exu_lsu_priority_trap_m |  spu_tlu_rsrv_illgl_m ;

ifu_mmu_trap_m | ffu_tlu_ill_inst_m | exu_lsu_priority_trap_m |  spu_tlu_rsrv_illgl_m ;

wire    trp_vld_m,trp_vld_g ;

wire    trp_vld_m,trp_vld_g ;

assign  trp_vld_m = flush_w_inst_vld_m & ~priority_squash_m ;

assign  trp_vld_m = flush_w_inst_vld_m & ~priority_squash_m ;

dff  #(2) sqshstgw (

dff_s  #(2) sqshstgw (

        .din    ({priority_squash_m,trp_vld_m}),

        .din    ({priority_squash_m,trp_vld_m}),

        .q      ({priority_squash_g,trp_vld_g}),

        .q      ({priority_squash_g,trp_vld_g}),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

) ;

) ;

//=========================================================================================

//=========================================================================================

//      Staging

//      Staging

//=========================================================================================

//=========================================================================================

dff  #(2) stg_d (

dff_s  #(2) stg_d (

        .din    (ifu_lsu_thrid_s[1:0]),

        .din    (ifu_lsu_thrid_s[1:0]),

        .q      (thrid_d[1:0]),

        .q      (thrid_d[1:0]),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

dff  #(2) stg_e (

dff_s  #(2) stg_e (

        .din    (thrid_d[1:0]),

        .din    (thrid_d[1:0]),

        .q      (thrid_e[1:0]),

        .q      (thrid_e[1:0]),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

dff  #(5) stg_m (

dff_s  #(5) stg_m (

        .din    ({ifu_lsu_ld_inst_e,ifu_lsu_st_inst_e,

        .din    ({ifu_lsu_ld_inst_e,ifu_lsu_st_inst_e,

                thrid_e[1:0],ifu_lsu_alt_space_e}),

                thrid_e[1:0],ifu_lsu_alt_space_e}),

        .q      ({ld_inst_m,st_inst_m,thrid_m[1:0],alt_space_m}),

        .q      ({ld_inst_m,st_inst_m,thrid_m[1:0],alt_space_m}),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

dff  #(6) stg_g (

dff_s  #(6) stg_g (

        .din    ({ld_inst_m,st_inst_m,thrid_m[1:0],alt_space_m,ifu_tlu_immu_miss_m}),

        .din    ({ld_inst_m,st_inst_m,thrid_m[1:0],alt_space_m,ifu_tlu_immu_miss_m}),

        .q      ({ld_inst_unflushed,st_inst_unflushed,thrid_g[1:0],alt_space_g,immu_miss_g}),

        .q      ({ld_inst_unflushed,st_inst_unflushed,thrid_g[1:0],alt_space_g,immu_miss_g}),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

// reads are terminated for illegal va case.

// reads are terminated for illegal va case.

assign  ld_inst_g = ld_inst_unflushed & inst_vld_g & ~local_flush_w ;

assign  ld_inst_g = ld_inst_unflushed & inst_vld_g & ~local_flush_w ;

//assign        ld_inst_g = ld_inst_unflushed & inst_vld_g & ~(dmmu_sync_illgl_va_g | immu_sync_illgl_va_g) & ;

//assign        ld_inst_g = ld_inst_unflushed & inst_vld_g & ~(dmmu_sync_illgl_va_g | immu_sync_illgl_va_g) & ;

Line 838...

Line 569...

/*dff stgivld_g (

/*dff stgivld_g (

        .din    (tlu_inst_vld_m),

        .din    (tlu_inst_vld_m),

        .q      (inst_vld_g),

        .q      (inst_vld_g),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

        ); */

        ); */

//=========================================================================================

//=========================================================================================

//      ASI RD DP MUX SELECT

//      ASI RD DP MUX SELECT

//=========================================================================================

//=========================================================================================

Line 874...

Line 605...

// Extend flops to hold selects for MacroTest of MRA.

// Extend flops to hold selects for MacroTest of MRA.

wire [2:0] ldxa_l1mx1_sel_out ;

wire [2:0] ldxa_l1mx1_sel_out ;

dff #(3)   l1mx1s_stgd1(

dff_s #(3)   l1mx1s_stgd1(

        .din    (tlu_ldxa_l1mx1_sel[2:0]),

        .din    (tlu_ldxa_l1mx1_sel[2:0]),

        .q      (ldxa_l1mx1_sel_out[2:0]),

        .q      (ldxa_l1mx1_sel_out[2:0]),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),         .si (),          .so ()

        .se     (1'b0),         `SIMPLY_RISC_SCANIN,          .so ()

);

);

// scan protection.

// scan protection.

assign  ldxa_l1mx1_sel_d1[0] = ldxa_l1mx1_sel_out[0] ;

assign  ldxa_l1mx1_sel_d1[0] = ldxa_l1mx1_sel_out[0] ;

assign  ldxa_l1mx1_sel_d1[1] = ldxa_l1mx1_sel_out[1] & ~rst_tri_en ;

assign  ldxa_l1mx1_sel_d1[1] = ldxa_l1mx1_sel_out[1] & ~rst_tri_en ;

assign  ldxa_l1mx1_sel_d1[2] = ldxa_l1mx1_sel_out[2] & ~rst_tri_en ;

assign  ldxa_l1mx1_sel_d1[2] = ldxa_l1mx1_sel_out[2] & ~rst_tri_en ;

wire    sehold_out ;

wire    sehold_out ;

dff #(1)   seh_d1 (

dff_s #(1)   seh_d1 (

        .din    (sehold),

        .din    (sehold),

        .q      (sehold_out),

        .q      (sehold_out),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),         .si (),          .so ()

        .se     (1'b0),         `SIMPLY_RISC_SCANIN,          .so ()

);

);

assign  sehold_d1 = sehold_out & ~rst_tri_en ;

assign  sehold_d1 = sehold_out & ~rst_tri_en ;

// i/d tag-access

// i/d tag-access

Line 979...

Line 710...

assign  idside_nzctxt_accwr_early_m =

assign  idside_nzctxt_accwr_early_m =

        ((dmmu_nzctxt_cfg_en_m   | immu_nzctxt_cfg_en_m     |

        ((dmmu_nzctxt_cfg_en_m   | immu_nzctxt_cfg_en_m     |

        dmmu_nzctxt_ps0_tsb_en_m | immu_nzctxt_ps0_tsb_en_m |

        dmmu_nzctxt_ps0_tsb_en_m | immu_nzctxt_ps0_tsb_en_m |

        dmmu_nzctxt_ps1_tsb_en_m | immu_nzctxt_ps1_tsb_en_m) & st_inst_m) ; // tsb/cfg asi wr

        dmmu_nzctxt_ps1_tsb_en_m | immu_nzctxt_ps1_tsb_en_m) & st_inst_m) ; // tsb/cfg asi wr

dff ctacc_stgg (

dff_s ctacc_stgg (

        .din    (idside_nzctxt_accwr_early_m),

        .din    (idside_nzctxt_accwr_early_m),

        .q      (idside_nzctxt_accwr_early_g),

        .q      (idside_nzctxt_accwr_early_g),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

//wire  idside_nzctxt_access ;

//wire  idside_nzctxt_access ;

wire    idside_nzctxt_access_rd,idside_nzctxt_access_wr ;

wire    idside_nzctxt_access_rd,idside_nzctxt_access_wr ;

wire    st_wr_g ;

wire    st_wr_g ;

Line 1077...

Line 808...

assign  dtacc_ctxt_en[1] = thread1_sel_g & mra_dtag_acc_en & mra_wr_vld ;

assign  dtacc_ctxt_en[1] = thread1_sel_g & mra_dtag_acc_en & mra_wr_vld ;

assign  dtacc_ctxt_en[2] = thread2_sel_g & mra_dtag_acc_en & mra_wr_vld ;

assign  dtacc_ctxt_en[2] = thread2_sel_g & mra_dtag_acc_en & mra_wr_vld ;

assign  dtacc_ctxt_en[3] = thread3_sel_g & mra_dtag_acc_en & mra_wr_vld ;

assign  dtacc_ctxt_en[3] = thread3_sel_g & mra_dtag_acc_en & mra_wr_vld ;

// Thread0

// Thread0

dffe   itacc_ctxt0 (

dffe_s   itacc_ctxt0 (

        .din    (tag_access_nctxt_g), .q  (itacc_nctxt0),

        .din    (tag_access_nctxt_g), .q  (itacc_nctxt0),

        .en     (itacc_ctxt_en[0]),      .clk (clk),

        .en     (itacc_ctxt_en[0]),      .clk (clk),

        .se     (1'b0),         .si (),          .so ()

        .se     (1'b0),         `SIMPLY_RISC_SCANIN,          .so ()

);

);

dffe   dtacc_ctxt0 (

dffe_s   dtacc_ctxt0 (

        .din    (tag_access_nctxt_g), .q  (dtacc_nctxt0),

        .din    (tag_access_nctxt_g), .q  (dtacc_nctxt0),

        .en     (dtacc_ctxt_en[0]),      .clk (clk),

        .en     (dtacc_ctxt_en[0]),      .clk (clk),

        .se     (1'b0),         .si (),          .so ()

        .se     (1'b0),         `SIMPLY_RISC_SCANIN,          .so ()

);

);

// Thread1

// Thread1

dffe   itacc_ctxt1 (

dffe_s   itacc_ctxt1 (

        .din    (tag_access_nctxt_g), .q  (itacc_nctxt1),

        .din    (tag_access_nctxt_g), .q  (itacc_nctxt1),

        .en     (itacc_ctxt_en[1]),     .clk (clk),

        .en     (itacc_ctxt_en[1]),     .clk (clk),

        .se     (1'b0),         .si (),          .so ()

        .se     (1'b0),         `SIMPLY_RISC_SCANIN,          .so ()

);

);

dffe   dtacc_ctxt1 (

dffe_s   dtacc_ctxt1 (

        .din    (tag_access_nctxt_g), .q  (dtacc_nctxt1),

        .din    (tag_access_nctxt_g), .q  (dtacc_nctxt1),

        .en     (dtacc_ctxt_en[1]),     .clk (clk),

        .en     (dtacc_ctxt_en[1]),     .clk (clk),

        .se     (1'b0),         .si (),          .so ()

        .se     (1'b0),         `SIMPLY_RISC_SCANIN,          .so ()

);

);

// Thread2

// Thread2

dffe   itacc_ctxt2 (

dffe_s   itacc_ctxt2 (

        .din    (tag_access_nctxt_g), .q  (itacc_nctxt2),

        .din    (tag_access_nctxt_g), .q  (itacc_nctxt2),

        .en     (itacc_ctxt_en[2]),     .clk (clk),

        .en     (itacc_ctxt_en[2]),     .clk (clk),

        .se     (1'b0),         .si (),          .so ()

        .se     (1'b0),         `SIMPLY_RISC_SCANIN,          .so ()

);

);

dffe   dtacc_ctxt2 (

dffe_s   dtacc_ctxt2 (

        .din    (tag_access_nctxt_g), .q  (dtacc_nctxt2),

        .din    (tag_access_nctxt_g), .q  (dtacc_nctxt2),

        .en     (dtacc_ctxt_en[2]),     .clk (clk),

        .en     (dtacc_ctxt_en[2]),     .clk (clk),

        .se     (1'b0),         .si (),          .so ()

        .se     (1'b0),         `SIMPLY_RISC_SCANIN,          .so ()

);

);

// Thread3

// Thread3

dffe   itacc_ctxt3 (

dffe_s   itacc_ctxt3 (

        .din    (tag_access_nctxt_g), .q  (itacc_nctxt3),

        .din    (tag_access_nctxt_g), .q  (itacc_nctxt3),

        .en     (itacc_ctxt_en[3]),     .clk (clk),

        .en     (itacc_ctxt_en[3]),     .clk (clk),

        .se     (1'b0),         .si (),          .so ()

        .se     (1'b0),         `SIMPLY_RISC_SCANIN,          .so ()

);

);

dffe   dtacc_ctxt3 (

dffe_s   dtacc_ctxt3 (

        .din    (tag_access_nctxt_g), .q  (dtacc_nctxt3),

        .din    (tag_access_nctxt_g), .q  (dtacc_nctxt3),

        .en     (dtacc_ctxt_en[3]),     .clk (clk),

        .en     (dtacc_ctxt_en[3]),     .clk (clk),

        .se     (1'b0),         .si (),          .so ()

        .se     (1'b0),         `SIMPLY_RISC_SCANIN,          .so ()

);

);

// In-pipe Access

// In-pipe Access

assign  itacc_nctxt =

assign  itacc_nctxt =

        thread0_d ? itacc_nctxt0 :

        thread0_d ? itacc_nctxt0 :

Line 1195...

Line 926...

        (lsu_tlu_tlb_asi_state_m[7:0] == 8'h60) | // Bug 4901

        (lsu_tlu_tlb_asi_state_m[7:0] == 8'h60) | // Bug 4901

        (lsu_tlu_tlb_asi_state_m[7:0] == 8'h5D) |

        (lsu_tlu_tlb_asi_state_m[7:0] == 8'h5D) |

        (lsu_tlu_tlb_asi_state_m[7:0] == 8'h5E) |

        (lsu_tlu_tlb_asi_state_m[7:0] == 8'h5E) |

        (lsu_tlu_tlb_asi_state_m[7:0] == 8'h5F)) & tlb_ldst_inst_m ;

        (lsu_tlu_tlb_asi_state_m[7:0] == 8'h5F)) & tlb_ldst_inst_m ;

dff stgg_dasi (

dff_s stgg_dasi (

        .din    (dmmu_async_supported_asi_m),

        .din    (dmmu_async_supported_asi_m),

        .q      (dmmu_async_supported_asi),

        .q      (dmmu_async_supported_asi),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

assign  dmmu_async_illgl_va_g =

assign  dmmu_async_illgl_va_g =

        dmmu_async_supported_asi &

        dmmu_async_supported_asi &

        ~(dmmu_data_in_en |

        ~(dmmu_data_in_en |

Line 1231...

Line 962...

        (lsu_tlu_tlb_asi_state_m[7:0] == 8'h60) | // Bug 4901

        (lsu_tlu_tlb_asi_state_m[7:0] == 8'h60) | // Bug 4901

        (lsu_tlu_tlb_asi_state_m[7:0] == 8'h55) |

        (lsu_tlu_tlb_asi_state_m[7:0] == 8'h55) |

        (lsu_tlu_tlb_asi_state_m[7:0] == 8'h56) |

        (lsu_tlu_tlb_asi_state_m[7:0] == 8'h56) |

        (lsu_tlu_tlb_asi_state_m[7:0] == 8'h57)) & tlb_ldst_inst_m  ;

        (lsu_tlu_tlb_asi_state_m[7:0] == 8'h57)) & tlb_ldst_inst_m  ;

dff stgg_iasi (

dff_s stgg_iasi (

        .din    (immu_async_supported_asi_m),

        .din    (immu_async_supported_asi_m),

        .q      (immu_async_supported_asi),

        .q      (immu_async_supported_asi),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

assign  immu_async_illgl_va_g =

assign  immu_async_illgl_va_g =

        immu_async_supported_asi &

        immu_async_supported_asi &

        ~(immu_data_in_en |

        ~(immu_data_in_en |

Line 1255...

Line 986...

assign  thread1_d = ~thrid_d[1] &  thrid_d[0] ;

assign  thread1_d = ~thrid_d[1] &  thrid_d[0] ;

assign  thread2_d =  thrid_d[1] & ~thrid_d[0] ;

assign  thread2_d =  thrid_d[1] & ~thrid_d[0] ;

assign  thread3_d =  thrid_d[1] &  thrid_d[0] ;

assign  thread3_d =  thrid_d[1] &  thrid_d[0] ;

wire    [7:0]   asi_reg0_d1 ;

wire    [7:0]   asi_reg0_d1 ;

dff #(8) stgd1_asi0 (

dff_s #(8) stgd1_asi0 (

        .din    (lsu_asi_reg0[7:0]),

        .din    (lsu_asi_reg0[7:0]),

        .q      (asi_reg0_d1[7:0]),

        .q      (asi_reg0_d1[7:0]),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

wire    [7:0]   asi_reg1_d1 ;

wire    [7:0]   asi_reg1_d1 ;

dff #(8) stgd1_asi1 (

dff_s #(8) stgd1_asi1 (

        .din    (lsu_asi_reg1[7:0]),

        .din    (lsu_asi_reg1[7:0]),

        .q      (asi_reg1_d1[7:0]),

        .q      (asi_reg1_d1[7:0]),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

wire    [7:0]   asi_reg2_d1 ;

wire    [7:0]   asi_reg2_d1 ;

dff #(8) stgd1_asi2 (

dff_s #(8) stgd1_asi2 (

        .din    (lsu_asi_reg2[7:0]),

        .din    (lsu_asi_reg2[7:0]),

        .q      (asi_reg2_d1[7:0]),

        .q      (asi_reg2_d1[7:0]),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

wire    [7:0]   asi_reg3_d1 ;

wire    [7:0]   asi_reg3_d1 ;

dff #(8) stgd1_asi3 (

dff_s #(8) stgd1_asi3 (

        .din    (lsu_asi_reg3[7:0]),

        .din    (lsu_asi_reg3[7:0]),

        .q      (asi_reg3_d1[7:0]),

        .q      (asi_reg3_d1[7:0]),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

wire    [7:0]   asi_reg_state ;

wire    [7:0]   asi_reg_state ;

assign  asi_reg_state[7:0] =

assign  asi_reg_state[7:0] =

        (thread0_d ? asi_reg0_d1[7:0] :

        (thread0_d ? asi_reg0_d1[7:0] :

Line 1300...

Line 1031...

// Use of asi delayed by a cycle.

// Use of asi delayed by a cycle.

assign  asi_state_d[7:0] = imm_asi_vld_d ?

assign  asi_state_d[7:0] = imm_asi_vld_d ?

      ifu_lsu_imm_asi_d[7:0] : asi_reg_state[7:0] ;

      ifu_lsu_imm_asi_d[7:0] : asi_reg_state[7:0] ;

dff #(8) stgd1_asi (

dff_s #(8) stgd1_asi (

        .din    (asi_state_d[7:0]),

        .din    (asi_state_d[7:0]),

        .q      (asi_state_e[7:0]),

        .q      (asi_state_e[7:0]),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

// bit8 is unused.

// bit8 is unused.

dff #(8) stgd1_eva (

dff_s #(8) stgd1_eva (

        .din    (exu_mmu_early_va_e[7:0]),

        .din    (exu_mmu_early_va_e[7:0]),

        .q      (early_va_m[7:0]),

        .q      (early_va_m[7:0]),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

dff #(6) stgd1_mref (

dff_s #(6) stgd1_mref (

        .din    ({ifu_lsu_memref_d,thread0_d,thread1_d,thread2_d,thread3_d,ifu_tlu_alt_space_d}),

        .din    ({ifu_lsu_memref_d,thread0_d,thread1_d,thread2_d,thread3_d,ifu_tlu_alt_space_d}),

        .q      ({memref_e,thread0_e, thread1_e, thread2_e, thread3_e,alt_space_e}),

        .q      ({memref_e,thread0_e, thread1_e, thread2_e, thread3_e,alt_space_e}),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

dff #(1) stgm_mref (

dff_s #(1) stgm_mref (

        .din    (memref_e),

        .din    (memref_e),

        .q      (memref_m),

        .q      (memref_m),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

// qualification with memref_d to cut down on number of speculative reads

// qualification with memref_d to cut down on number of speculative reads

// decode can be shared with corresponding enables

// decode can be shared with corresponding enables

Line 1427...

Line 1158...

                 ({asi_state_e[7:0]} == {8'h3F}) & alt_space_e & memref_e ;

                 ({asi_state_e[7:0]} == {8'h3F}) & alt_space_e & memref_e ;

end

end

wire immu_64k_ptr_m,immu_8k_ptr_m,dmmu_direct_ptr_m,dmmu_64k_ptr_m,

wire immu_64k_ptr_m,immu_8k_ptr_m,dmmu_direct_ptr_m,dmmu_64k_ptr_m,

dmmu_8k_ptr_m ;

dmmu_8k_ptr_m ;

dff  #(19) fastasi_m (

dff_s  #(19) fastasi_m (

        .din    ({dmmu_8k_ptr_e,dmmu_64k_ptr_e,dmmu_direct_ptr_e,

        .din    ({dmmu_8k_ptr_e,dmmu_64k_ptr_e,dmmu_direct_ptr_e,

                dmmu_decode_asi58_e, immu_decode_asi50_e,

                dmmu_decode_asi58_e, immu_decode_asi50_e,

                dmmu_zctxt_ps0_tsb_e, dmmu_zctxt_ps1_tsb_e,

                dmmu_zctxt_ps0_tsb_e, dmmu_zctxt_ps1_tsb_e,

                dmmu_nzctxt_ps0_tsb_e, dmmu_nzctxt_ps1_tsb_e,

                dmmu_nzctxt_ps0_tsb_e, dmmu_nzctxt_ps1_tsb_e,

                dmmu_zctxt_cfg_e, dmmu_nzctxt_cfg_e,

                dmmu_zctxt_cfg_e, dmmu_nzctxt_cfg_e,

Line 1447...

Line 1178...

                immu_zctxt_ps0_tsb_m, immu_zctxt_ps1_tsb_m,

                immu_zctxt_ps0_tsb_m, immu_zctxt_ps1_tsb_m,

                immu_nzctxt_ps0_tsb_m, immu_nzctxt_ps1_tsb_m,

                immu_nzctxt_ps0_tsb_m, immu_nzctxt_ps1_tsb_m,

                immu_zctxt_cfg_m, immu_nzctxt_cfg_m,

                immu_zctxt_cfg_m, immu_nzctxt_cfg_m,

                immu_8k_ptr_m,immu_64k_ptr_m}),

                immu_8k_ptr_m,immu_64k_ptr_m}),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

assign  dmmu_tag_target_en_m = dmmu_decode_asi58_m & (early_va_m[7:0] == 8'h00) ;

assign  dmmu_tag_target_en_m = dmmu_decode_asi58_m & (early_va_m[7:0] == 8'h00) ;

assign  dmmu_tag_access_en_m = dmmu_decode_asi58_m & (early_va_m[7:0] == 8'h30) ;

assign  dmmu_tag_access_en_m = dmmu_decode_asi58_m & (early_va_m[7:0] == 8'h30) ;

assign  dmmu_sync_fsr_en_m = dmmu_decode_asi58_m & (early_va_m[7:0] == 8'h18) ;

assign  dmmu_sync_fsr_en_m = dmmu_decode_asi58_m & (early_va_m[7:0] == 8'h18) ;

Line 1473...

Line 1204...

assign  dmmu_sync_supported_asi_e =

assign  dmmu_sync_supported_asi_e =

        (dmmu_decode_asi58_e | dmmu_zctxt_ps0_tsb_e | dmmu_zctxt_ps1_tsb_e |

        (dmmu_decode_asi58_e | dmmu_zctxt_ps0_tsb_e | dmmu_zctxt_ps1_tsb_e |

        dmmu_nzctxt_ps0_tsb_e | dmmu_nzctxt_ps1_tsb_e | dmmu_zctxt_cfg_e |

        dmmu_nzctxt_ps0_tsb_e | dmmu_nzctxt_ps1_tsb_e | dmmu_zctxt_cfg_e |

        dmmu_nzctxt_cfg_e | dmmu_8k_ptr_e | dmmu_64k_ptr_e | dmmu_direct_ptr_e);

        dmmu_nzctxt_cfg_e | dmmu_8k_ptr_e | dmmu_64k_ptr_e | dmmu_direct_ptr_e);

dff stgm_dsynca (

dff_s stgm_dsynca (

        .din    (dmmu_sync_supported_asi_e),

        .din    (dmmu_sync_supported_asi_e),

        .q      (dmmu_sync_supported_asi_m),

        .q      (dmmu_sync_supported_asi_m),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

wire    dmmu_sync_illgl_va_m ;

wire    dmmu_sync_illgl_va_m ;

assign  dmmu_sync_illgl_va_m = dmmu_sync_supported_asi_m & ~(dmmu_tag_target_en_m |

assign  dmmu_sync_illgl_va_m = dmmu_sync_supported_asi_m & ~(dmmu_tag_target_en_m |

        dmmu_tag_access_en_m | dmmu_sync_fsr_en_m | dmmu_sync_far_en_m | dmmu_tsb_en_m |

        dmmu_tag_access_en_m | dmmu_sync_fsr_en_m | dmmu_sync_far_en_m | dmmu_tsb_en_m |

Line 1517...

Line 1248...

assign  immu_sync_supported_asi_e =

assign  immu_sync_supported_asi_e =

        (immu_decode_asi50_e | immu_zctxt_ps0_tsb_e | immu_zctxt_ps1_tsb_e |

        (immu_decode_asi50_e | immu_zctxt_ps0_tsb_e | immu_zctxt_ps1_tsb_e |

        immu_nzctxt_ps0_tsb_e | immu_nzctxt_ps1_tsb_e | immu_zctxt_cfg_e |

        immu_nzctxt_ps0_tsb_e | immu_nzctxt_ps1_tsb_e | immu_zctxt_cfg_e |

        immu_nzctxt_cfg_e | immu_8k_ptr_e | immu_64k_ptr_e);

        immu_nzctxt_cfg_e | immu_8k_ptr_e | immu_64k_ptr_e);

dff stgm_isynca (

dff_s stgm_isynca (

        .din    (immu_sync_supported_asi_e),

        .din    (immu_sync_supported_asi_e),

        .q      (immu_sync_supported_asi_m),

        .q      (immu_sync_supported_asi_m),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

wire    immu_sync_illgl_va_m ;

wire    immu_sync_illgl_va_m ;

assign  immu_sync_illgl_va_m = immu_sync_supported_asi_m & ~(immu_tag_target_en_m |

assign  immu_sync_illgl_va_m = immu_sync_supported_asi_m & ~(immu_tag_target_en_m |

        immu_tag_access_en_m | immu_sync_fsr_en_m | immu_tsb_en_m | immu_ctxt_cfg_en_m |

        immu_tag_access_en_m | immu_sync_fsr_en_m | immu_tsb_en_m | immu_ctxt_cfg_en_m |

        immu_8k_ptr_en_m | immu_64k_ptr_en_m);

        immu_8k_ptr_en_m | immu_64k_ptr_en_m);

dff #(2) stgg_illgl (

dff_s #(2) stgg_illgl (

        .din    ({immu_sync_illgl_va_m,dmmu_sync_illgl_va_m}),

        .din    ({immu_sync_illgl_va_m,dmmu_sync_illgl_va_m}),

        .q      ({immu_sync_illgl_va_g,dmmu_sync_illgl_va_g}),

        .q      ({immu_sync_illgl_va_g,dmmu_sync_illgl_va_g}),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

// Staged to g for writes

// Staged to g for writes

dff  #(17) fastasi_g (

dff_s  #(17) fastasi_g (

        .din    ({dmmu_tag_access_en_m,

        .din    ({dmmu_tag_access_en_m,

                dmmu_sync_fsr_en_m, dmmu_sync_far_en_m,

                dmmu_sync_fsr_en_m, dmmu_sync_far_en_m,

                dmmu_zctxt_ps0_tsb_en_m, dmmu_zctxt_ps1_tsb_en_m,

                dmmu_zctxt_ps0_tsb_en_m, dmmu_zctxt_ps1_tsb_en_m,

                dmmu_nzctxt_ps0_tsb_en_m, dmmu_nzctxt_ps1_tsb_en_m,

                dmmu_nzctxt_ps0_tsb_en_m, dmmu_nzctxt_ps1_tsb_en_m,

                dmmu_zctxt_cfg_en_m, dmmu_nzctxt_cfg_en_m,

                dmmu_zctxt_cfg_en_m, dmmu_nzctxt_cfg_en_m,

Line 1559...

Line 1290...

                immu_sync_fsr_en,

                immu_sync_fsr_en,

                immu_zctxt_ps0_tsb_en, immu_zctxt_ps1_tsb_en,

                immu_zctxt_ps0_tsb_en, immu_zctxt_ps1_tsb_en,

                immu_nzctxt_ps0_tsb_en, immu_nzctxt_ps1_tsb_en,

                immu_nzctxt_ps0_tsb_en, immu_nzctxt_ps1_tsb_en,

                immu_zctxt_cfg_en, immu_nzctxt_cfg_en}),

                immu_zctxt_cfg_en, immu_nzctxt_cfg_en}),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

//=========================================================================================

//=========================================================================================

//      MMU ASI Decode - D-Side

//      MMU ASI Decode - D-Side

//=========================================================================================

//=========================================================================================

Line 1604...

Line 1335...

// support information.

// support information.

wire lng_ltncy_en_d1 ;

wire lng_ltncy_en_d1 ;

assign  tlu_lng_ltncy_en_l = ~lng_ltncy_en_d1 | sehold ;

assign  tlu_lng_ltncy_en_l = ~lng_ltncy_en_d1 | sehold ;

wire    lng_ltncy_en ;

wire    lng_ltncy_en ;

dff stgd1_lltncyen (

dff_s stgd1_lltncyen (

        .din    (lng_ltncy_en),

        .din    (lng_ltncy_en),

        .q      (lng_ltncy_en_d1),

        .q      (lng_ltncy_en_d1),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

assign  lng_ltncy_en = (lsu_tlu_tlb_st_inst_m | lsu_tlu_tlb_ld_inst_m) ;

assign  lng_ltncy_en = (lsu_tlu_tlb_st_inst_m | lsu_tlu_tlb_ld_inst_m) ;

wire    lng_ltncy_rst ;

wire    lng_ltncy_rst ;

assign  lng_ltncy_rst =

assign  lng_ltncy_rst =

Line 1622...

Line 1353...

        dmra_lng_lat_rd | imra_lng_lat_rd | // lng-ltncy rds - delay until bubble available.

        dmra_lng_lat_rd | imra_lng_lat_rd | // lng-ltncy rds - delay until bubble available.

        ((tlb_ld_inst_unflushed | tlb_st_inst_unflushed) &  // rst w/o use if illgl-va

        ((tlb_ld_inst_unflushed | tlb_st_inst_unflushed) &  // rst w/o use if illgl-va

                        (dmmu_async_illgl_va_g | immu_async_illgl_va_g)) |

                        (dmmu_async_illgl_va_g | immu_async_illgl_va_g)) |

        ~rst_l ;

        ~rst_l ;

dffe  #(10) dtlbacc_stgg (

dffe_s  #(10) dtlbacc_stgg (

        .din    ({lsu_tlu_tlb_ldst_va_m[10:3], lsu_tlu_tlb_access_tid_m[1:0]}),

        .din    ({lsu_tlu_tlb_ldst_va_m[10:3], lsu_tlu_tlb_access_tid_m[1:0]}),

        .q      ({tlb_ldst_va_g[10:3],tlb_access_tid_g[1:0]}),

        .q      ({tlb_ldst_va_g[10:3],tlb_access_tid_g[1:0]}),

        .clk    (clk),

        .clk    (clk),

        .en     (lng_ltncy_en),

        .en     (lng_ltncy_en),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

dffre  #(7) dtlbaccr_stgg (

dffre_s  #(7) dtlbaccr_stgg (

        .din    ({dmmu_data_in_en_m,dmmu_data_access_en_m,dmmu_tag_read_en_m,

        .din    ({dmmu_data_in_en_m,dmmu_data_access_en_m,dmmu_tag_read_en_m,

                dmmu_demap_en_m,dmmu_invalidate_all_en_m,

                dmmu_demap_en_m,dmmu_invalidate_all_en_m,

                lsu_tlu_tlb_ld_inst_m,lsu_tlu_tlb_st_inst_m}),

                lsu_tlu_tlb_ld_inst_m,lsu_tlu_tlb_st_inst_m}),

        .q      ({dmmu_data_in_en,dmmu_data_access_en,dmmu_tag_read_en,

        .q      ({dmmu_data_in_en,dmmu_data_access_en,dmmu_tag_read_en,

                dmmu_demap_en,dmmu_invalidate_all_en,

                dmmu_demap_en,dmmu_invalidate_all_en,

                tlb_ld_inst_unflushed,tlb_st_inst_unflushed}),

                tlb_ld_inst_unflushed,tlb_st_inst_unflushed}),

        .clk    (clk),

        .clk    (clk),

        .rst    (lng_ltncy_rst),        .en     (lng_ltncy_en),

        .rst    (lng_ltncy_rst),        .en     (lng_ltncy_en),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

assign  tlb_st_inst_g = tlb_st_inst_unflushed & ~(dmmu_async_illgl_va_g | immu_async_illgl_va_g) ;

assign  tlb_st_inst_g = tlb_st_inst_unflushed & ~(dmmu_async_illgl_va_g | immu_async_illgl_va_g) ;

assign  tlb_ld_inst_g = tlb_ld_inst_unflushed & ~(dmmu_async_illgl_va_g | immu_async_illgl_va_g) ;

assign  tlb_ld_inst_g = tlb_ld_inst_unflushed & ~(dmmu_async_illgl_va_g | immu_async_illgl_va_g) ;

Line 1686...

Line 1417...

assign  dtlb_wr_vld_g = (dmmu_data_in_wr_en | dmmu_data_access_wr_en) & ~ifu_lsu_memref_d ;

assign  dtlb_wr_vld_g = (dmmu_data_in_wr_en | dmmu_data_access_wr_en) & ~ifu_lsu_memref_d ;

wire            dtlb_rw_index_vld_pend ;

wire            dtlb_rw_index_vld_pend ;

wire [5:0]       dtlb_rw_index_pend ;

wire [5:0]       dtlb_rw_index_pend ;

dffre  #(1) stgw2_dtlbctl (

dffre_s  #(1) stgw2_dtlbctl (

        .din    (dtlb_rw_index_vld_g),

        .din    (dtlb_rw_index_vld_g),

        .q      (dtlb_rw_index_vld_pend),

        .q      (dtlb_rw_index_vld_pend),

        .rst    (tlb_access_rst),       .en     (tlb_access_en),

        .rst    (tlb_access_rst),       .en     (tlb_access_en),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

dffre  #(6) stgw2_dtlbidx (

dffre_s  #(6) stgw2_dtlbidx (

        .din    (tlb_ldst_va_g[8:3]),

        .din    (tlb_ldst_va_g[8:3]),

        .q      (dtlb_rw_index_pend[5:0]),

        .q      (dtlb_rw_index_pend[5:0]),

        .rst    (tlb_access_rst),       .en     (tlb_access_en),

        .rst    (tlb_access_rst),       .en     (tlb_access_en),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

wire    tlb_rd_mode, tlb_rd_mode_d1 ;

wire    tlb_rd_mode, tlb_rd_mode_d1 ;

assign  tlb_rd_mode =

assign  tlb_rd_mode =

                tlu_itlb_tag_rd_g | tlu_itlb_data_rd_g |        // i-side read

                tlu_itlb_tag_rd_g | tlu_itlb_data_rd_g |        // i-side read

                tlu_dtlb_tag_rd_g | tlu_dtlb_data_rd_g ;        // d-side read

                tlu_dtlb_tag_rd_g | tlu_dtlb_data_rd_g ;        // d-side read

dff stgd1_rmode (

dff_s stgd1_rmode (

        .din    (tlb_rd_mode),

        .din    (tlb_rd_mode),

        .q      (tlb_rd_mode_d1),

        .q      (tlb_rd_mode_d1),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

wire    dtlb_done_d1 ;

wire    dtlb_done_d1 ;

dff stgd1_ddone (

dff_s stgd1_ddone (

        .din    (lsu_tlu_dtlb_done),

        .din    (lsu_tlu_dtlb_done),

        .q      (dtlb_done_d1),

        .q      (dtlb_done_d1),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

wire    itlb_done_d1 ;

wire    itlb_done_d1 ;

dff stgd1_idone (

dff_s stgd1_idone (

        .din    (ifu_tlu_itlb_done),

        .din    (ifu_tlu_itlb_done),

        .q      (itlb_done_d1),

        .q      (itlb_done_d1),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

// Advanced by a cycle.

// Advanced by a cycle.

assign  tlu_dtlb_rw_index_vld_g  = dtlb_rw_index_vld_g | dtlb_rw_index_vld_pend ;

assign  tlu_dtlb_rw_index_vld_g  = dtlb_rw_index_vld_g | dtlb_rw_index_vld_pend ;

//assign        tlu_dtlb_rw_index_vld_g  = dtlb_rw_index_vld_g | (dtlb_rw_index_vld_pend & ~dtlb_done_d1) ; //Bug3974

//assign        tlu_dtlb_rw_index_vld_g  = dtlb_rw_index_vld_g | (dtlb_rw_index_vld_pend & ~dtlb_done_d1) ; //Bug3974

Line 1767...

Line 1498...

wire            dmmu_inv_all_g, dmmu_inv_all_pend ;

wire            dmmu_inv_all_g, dmmu_inv_all_pend ;

assign  dmmu_inv_all_g = dmmu_invalidate_all_en & tlb_st_inst_g ;

assign  dmmu_inv_all_g = dmmu_invalidate_all_en & tlb_st_inst_g ;

// Demap/Invalidate

// Demap/Invalidate

dffre  #(5) stgw2_dtlbdmp (

dffre_s  #(5) stgw2_dtlbdmp (

        .din    ({ddemap_all,demap_pctxt,demap_sctxt,demap_nctxt,dmmu_inv_all_g}),

        .din    ({ddemap_all,demap_pctxt,demap_sctxt,demap_nctxt,dmmu_inv_all_g}),

        .q      ({dtlb_dmp_all_pend,dtlb_dmp_pctxt_pend,dtlb_dmp_sctxt_pend,

        .q      ({dtlb_dmp_all_pend,dtlb_dmp_pctxt_pend,dtlb_dmp_sctxt_pend,

                dtlb_dmp_nctxt_pend,dmmu_inv_all_pend }),

                dtlb_dmp_nctxt_pend,dmmu_inv_all_pend }),

        .rst    (tlb_access_rst),       .en     (tlb_access_en),

        .rst    (tlb_access_rst),       .en     (tlb_access_en),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

// Bug 3905 - rm from above flop.

// Bug 3905 - rm from above flop.

assign  idtlb_dmp_thrid_pend[1:0] = tlb_access_tid_g[1:0] ;

assign  idtlb_dmp_thrid_pend[1:0] = tlb_access_tid_g[1:0] ;

assign  ldst_asi_tid[1:0] =

assign  ldst_asi_tid[1:0] =

        (lsu_tlu_dtlb_done | dmmu_async_illgl_va_g | immu_async_illgl_va_g)  ?

        (lsu_tlu_dtlb_done | dmmu_async_illgl_va_g | immu_async_illgl_va_g)  ?

        idtlb_dmp_thrid_pend[1:0] : thrid_g[1:0] ;

        idtlb_dmp_thrid_pend[1:0] : thrid_g[1:0] ;

// Thread for tlb

// Thread for tlb

dff  #(4) stg_w2 (

dff_s  #(4) stg_w2 (

        .din    ({ldst_asi_tid[1:0],idtlb_dmp_thrid_pend[1:0]}),

        .din    ({ldst_asi_tid[1:0],idtlb_dmp_thrid_pend[1:0]}),

        .q      ({tlu_lsu_ldxa_tid_w2[1:0],tlu_lsu_stxa_ack_tid[1:0]}),

        .q      ({tlu_lsu_ldxa_tid_w2[1:0],tlu_lsu_stxa_ack_tid[1:0]}),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

assign  tlu_dtlb_invalidate_all_g = dmmu_inv_all_g | (dmmu_inv_all_pend & ~dtlb_done_d1) ;

assign  tlu_dtlb_invalidate_all_g = dmmu_inv_all_g | (dmmu_inv_all_pend & ~dtlb_done_d1) ;

//assign        tlu_dtlb_invalidate_all_g = dmmu_inv_all_g | (dmmu_inv_all_pend & ~lsu_tlu_dtlb_done) ;

//assign        tlu_dtlb_invalidate_all_g = dmmu_inv_all_g | (dmmu_inv_all_pend & ~lsu_tlu_dtlb_done) ;

Line 1804...

Line 1535...

assign  pre_dtlb_dmp_pctxt = (dtlb_dmp_pctxt_pend) & ~tlu_admp_key_sel ;

assign  pre_dtlb_dmp_pctxt = (dtlb_dmp_pctxt_pend) & ~tlu_admp_key_sel ;

assign  pre_dtlb_dmp_sctxt = (dtlb_dmp_sctxt_pend) & ~tlu_admp_key_sel ;

assign  pre_dtlb_dmp_sctxt = (dtlb_dmp_sctxt_pend) & ~tlu_admp_key_sel ;

assign  pre_dtlb_dmp_nctxt = (dtlb_dmp_nctxt_pend) & ~tlu_admp_key_sel ;

assign  pre_dtlb_dmp_nctxt = (dtlb_dmp_nctxt_pend) & ~tlu_admp_key_sel ;

assign  pre_dtlb_dmp_actxt = tlu_admp_key_sel ;

assign  pre_dtlb_dmp_actxt = tlu_admp_key_sel ;

dff  #(5) dmp_stgd1 (

dff_s  #(5) dmp_stgd1 (

        .din    ({pre_dtlb_dmp_all, pre_dtlb_dmp_pctxt,

        .din    ({pre_dtlb_dmp_all, pre_dtlb_dmp_pctxt,

                pre_dtlb_dmp_sctxt, pre_dtlb_dmp_nctxt, pre_dtlb_dmp_actxt}),

                pre_dtlb_dmp_sctxt, pre_dtlb_dmp_nctxt, pre_dtlb_dmp_actxt}),

        .q      ({tlu_dtlb_dmp_all_g,tlu_dtlb_dmp_pctxt_g,

        .q      ({tlu_dtlb_dmp_all_g,tlu_dtlb_dmp_pctxt_g,

                tlu_dtlb_dmp_sctxt_g,tlu_dtlb_dmp_nctxt_g,tlu_dtlb_dmp_actxt_g}),

                tlu_dtlb_dmp_sctxt_g,tlu_dtlb_dmp_nctxt_g,tlu_dtlb_dmp_actxt_g}),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

assign  tlu_idtlb_dmp_thrid_g = tlb_access_tid_g[1:0] | idtlb_dmp_thrid_pend[1:0] ;

assign  tlu_idtlb_dmp_thrid_g = tlb_access_tid_g[1:0] | idtlb_dmp_thrid_pend[1:0] ;

Line 1850...

Line 1581...

                 ({lsu_tlu_tlb_asi_state_m[7:0]} == {8'h57}) & tlb_ldst_inst_m ;

                 ({lsu_tlu_tlb_asi_state_m[7:0]} == {8'h57}) & tlb_ldst_inst_m ;

end

end

// Stage to g.

// Stage to g.

// Convert to dffre to resolve conflict between fast-asi and lng-ltncy reads.

// Convert to dffre to resolve conflict between fast-asi and lng-ltncy reads.

dffre #(5) itlbacc_stgg (

dffre_s #(5) itlbacc_stgg (

        .din    ({immu_data_in_en_m,immu_data_access_en_m,immu_tag_read_en_m,immu_demap_en_m,immu_invalidate_all_en_m}),

        .din    ({immu_data_in_en_m,immu_data_access_en_m,immu_tag_read_en_m,immu_demap_en_m,immu_invalidate_all_en_m}),

        .q      ({immu_data_in_en,immu_data_access_en,immu_tag_read_en,immu_demap_en,immu_invalidate_all_en}),

        .q      ({immu_data_in_en,immu_data_access_en,immu_tag_read_en,immu_demap_en,immu_invalidate_all_en}),

        .clk    (clk),

        .clk    (clk),

        .rst    (lng_ltncy_rst),        .en     (lng_ltncy_en),

        .rst    (lng_ltncy_rst),        .en     (lng_ltncy_en),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

assign  isfsr_asi_wr_en[0] = immu_sync_fsr_en & st_inst_g & thread0_sel_g ;

assign  isfsr_asi_wr_en[0] = immu_sync_fsr_en & st_inst_g & thread0_sel_g ;

assign  isfsr_asi_wr_en[1] = immu_sync_fsr_en & st_inst_g & thread1_sel_g ;

assign  isfsr_asi_wr_en[1] = immu_sync_fsr_en & st_inst_g & thread1_sel_g ;

Line 1885...

Line 1616...

// terminate write if tlb full and signal exception.

// terminate write if tlb full and signal exception.

assign  itlb_wr_vld_g = (immu_data_in_wr_en | immu_data_access_wr_en) & ~ifu_lsu_memref_d ;

assign  itlb_wr_vld_g = (immu_data_in_wr_en | immu_data_access_wr_en) & ~ifu_lsu_memref_d ;

wire    itlb_rw_index_vld_pend ;

wire    itlb_rw_index_vld_pend ;

dffre #(1)  stgw2_itlbctl (

dffre_s #(1)  stgw2_itlbctl (

        .din    (itlb_rw_index_vld_g),

        .din    (itlb_rw_index_vld_g),

        .q      (itlb_rw_index_vld_pend),

        .q      (itlb_rw_index_vld_pend),

        .rst    (tlb_access_rst),       .en     (tlb_access_en),

        .rst    (tlb_access_rst),       .en     (tlb_access_en),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

assign  tlu_itlb_rw_index_vld_g  = itlb_rw_index_vld_g | (itlb_rw_index_vld_pend & ~itlb_done_d1) ;

assign  tlu_itlb_rw_index_vld_g  = itlb_rw_index_vld_g | (itlb_rw_index_vld_pend & ~itlb_done_d1) ;

assign  tlu_itlb_rw_index_g[5:0] = tlu_dtlb_rw_index_g[5:0] ;

assign  tlu_itlb_rw_index_g[5:0] = tlu_dtlb_rw_index_g[5:0] ;

Line 1912...

Line 1643...

wire    immu_inv_all_g, immu_inv_all_pend ;

wire    immu_inv_all_g, immu_inv_all_pend ;

assign  immu_inv_all_g = immu_invalidate_all_en & tlb_st_inst_g ;

assign  immu_inv_all_g = immu_invalidate_all_en & tlb_st_inst_g ;

// Demap

// Demap

dffre  #(3) stgw2_itlbdmp (

dffre_s  #(3) stgw2_itlbdmp (

        .din    ({idemap_by_ctxt,idemap_all,immu_inv_all_g}),

        .din    ({idemap_by_ctxt,idemap_all,immu_inv_all_g}),

        .q      ({itlb_dmp_by_ctxt_pend, itlb_dmp_all_pend,immu_inv_all_pend}),

        .q      ({itlb_dmp_by_ctxt_pend, itlb_dmp_all_pend,immu_inv_all_pend}),

        .rst    (tlb_access_rst),       .en     (tlb_access_en),

        .rst    (tlb_access_rst),       .en     (tlb_access_en),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

wire    tlu_itlb_dmp_all_g = (idemap_all | itlb_dmp_all_pend) & ~tlu_admp_key_sel ;

wire    tlu_itlb_dmp_all_g = (idemap_all | itlb_dmp_all_pend) & ~tlu_admp_key_sel ;

assign  tlu_itlb_invalidate_all_g = immu_inv_all_g | (immu_inv_all_pend & ~itlb_done_d1) ;

assign  tlu_itlb_invalidate_all_g = immu_inv_all_g | (immu_inv_all_pend & ~itlb_done_d1) ;

assign  tlu_itlb_dmp_pctxt_g = tlu_dtlb_dmp_pctxt_g ;

assign  tlu_itlb_dmp_pctxt_g = tlu_dtlb_dmp_pctxt_g ;

// Timing Change - delay by 1-cycle to match vld.

// Timing Change - delay by 1-cycle to match vld.

wire    pre_itlb_dmp_actxt ;

wire    pre_itlb_dmp_actxt ;

assign  pre_itlb_dmp_actxt = tlu_admp_key_sel ;

assign  pre_itlb_dmp_actxt = tlu_admp_key_sel ;

dff  #(1) preidmp_d1 (

dff_s  #(1) preidmp_d1 (

        .din    (pre_itlb_dmp_actxt),

        .din    (pre_itlb_dmp_actxt),

        .q      (tlu_itlb_dmp_actxt_g),

        .q      (tlu_itlb_dmp_actxt_g),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

assign  tlu_itlb_dmp_nctxt_g = tlu_dtlb_dmp_nctxt_g ;

assign  tlu_itlb_dmp_nctxt_g = tlu_dtlb_dmp_nctxt_g ;

Line 1977...

Line 1708...

assign  tlb_access_en_l = ~tlb_access_en ;

assign  tlb_access_en_l = ~tlb_access_en ;

assign  tlb_access_rst = ~rst_l | ((lsu_tlu_dtlb_done | ifu_tlu_itlb_done) & ~(tlb_admp_mode | tlb_admp_mode_d1)) ;

assign  tlb_access_rst = ~rst_l | ((lsu_tlu_dtlb_done | ifu_tlu_itlb_done) & ~(tlb_admp_mode | tlb_admp_mode_d1)) ;

assign  tlb_access_rst_l = ~tlb_access_rst ;

assign  tlb_access_rst_l = ~tlb_access_rst ;

wire    tlb_access_en_l_d1 ;

wire    tlb_access_en_l_d1 ;

dff  #(1) stgd1_tlbacc (

dff_s  #(1) stgd1_tlbacc (

        .din    (tlb_access_en_l),

        .din    (tlb_access_en_l),

        .q      (tlb_access_en_l_d1),

        .q      (tlb_access_en_l_d1),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

assign  tlu_tlb_access_en_l_d1 = tlb_access_en_l_d1 | sehold ;

assign  tlu_tlb_access_en_l_d1 = tlb_access_en_l_d1 | sehold ;

assign  itlb_tag_rd_en = immu_tag_read_rd_en | immu_data_access_rd_en ;

assign  itlb_tag_rd_en = immu_tag_read_rd_en | immu_data_access_rd_en ;

assign  dtlb_tag_rd_en = dmmu_tag_read_rd_en | dmmu_data_access_rd_en ;

assign  dtlb_tag_rd_en = dmmu_tag_read_rd_en | dmmu_data_access_rd_en ;

dffre #(8)  tlb_access (

dffre_s #(8)  tlb_access (

        .din    ({itlb_wr_vld_g,immu_data_access_rd_en,itlb_tag_rd_en,

        .din    ({itlb_wr_vld_g,immu_data_access_rd_en,itlb_tag_rd_en,

                dtlb_wr_vld_g,dmmu_data_access_rd_en,dtlb_tag_rd_en,

                dtlb_wr_vld_g,dmmu_data_access_rd_en,dtlb_tag_rd_en,

                idemap_vld, ddemap_vld}),

                idemap_vld, ddemap_vld}),

        .q      ({itlb_wr_pend,itlb_data_rd_pend,itlb_tag_rd_pend,

        .q      ({itlb_wr_pend,itlb_data_rd_pend,itlb_tag_rd_pend,

                dtlb_wr_pend,dtlb_data_rd_pend,dtlb_tag_rd_pend,

                dtlb_wr_pend,dtlb_data_rd_pend,dtlb_tag_rd_pend,

                idemap_pend, ddemap_pend}),

                idemap_pend, ddemap_pend}),

        .rst    (tlb_access_rst),       .en     (tlb_access_en),

        .rst    (tlb_access_rst),       .en     (tlb_access_en),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

assign  tlu_dtlb_rd_done  = lsu_tlu_dtlb_done & (dtlb_data_rd_pend | dtlb_tag_rd_pend) ;

assign  tlu_dtlb_rd_done  = lsu_tlu_dtlb_done & (dtlb_data_rd_pend | dtlb_tag_rd_pend) ;

//assign  itlb_rd_done  = ifu_tlu_itlb_done & (itlb_data_rd_pend | itlb_tag_rd_pend) ;

//assign  itlb_rd_done  = ifu_tlu_itlb_done & (itlb_data_rd_pend | itlb_tag_rd_pend) ;

Line 2017...

Line 1748...

assign  tlu_itlb_wr_vld_g = pre_itlb_wr_vld_g ;

assign  tlu_itlb_wr_vld_g = pre_itlb_wr_vld_g ;

/*dff  #(1) iwvld_d1 (

/*dff  #(1) iwvld_d1 (

        .din    (pre_itlb_wr_vld_g),

        .din    (pre_itlb_wr_vld_g),

        .q      (tlu_itlb_wr_vld_g),

        .q      (tlu_itlb_wr_vld_g),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

        ); */

        ); */

assign  tlu_itlb_data_rd_g = immu_data_access_rd_en | (itlb_data_rd_pend & ~itlb_done_d1) ;

assign  tlu_itlb_data_rd_g = immu_data_access_rd_en | (itlb_data_rd_pend & ~itlb_done_d1) ;

assign  tlu_itlb_tag_rd_g = (immu_tag_read_rd_en | immu_data_access_rd_en) | (itlb_tag_rd_pend & ~itlb_done_d1) ;

assign  tlu_itlb_tag_rd_g = (immu_tag_read_rd_en | immu_data_access_rd_en) | (itlb_tag_rd_pend & ~itlb_done_d1) ;

assign  dtlb_wr_vld_unmsked = (dtlb_wr_vld_g | (dtlb_wr_pend & ~dtlb_done_d1)) ;

assign  dtlb_wr_vld_unmsked = (dtlb_wr_vld_g | (dtlb_wr_pend & ~dtlb_done_d1)) ;

Line 2045...

Line 1776...

                (idemap_pend & ~itlb_done_d1) |

                (idemap_pend & ~itlb_done_d1) |

                (itlb_wr_vld_unmsked & tlb_admp_mode) ;

                (itlb_wr_vld_unmsked & tlb_admp_mode) ;

// dmp_vld should be w2. kept as _g for now to avoid

// dmp_vld should be w2. kept as _g for now to avoid

// interface change.

// interface change.

wire    dtlb_dmp_vld_d1,itlb_dmp_vld_d1 ;

wire    dtlb_dmp_vld_d1,itlb_dmp_vld_d1 ;

dff  #(2) dmpvld_d1 (

dff_s  #(2) dmpvld_d1 (

        .din    ({dtlb_dmp_vld_g,itlb_dmp_vld_g}),

        .din    ({dtlb_dmp_vld_g,itlb_dmp_vld_g}),

        .q      ({dtlb_dmp_vld_d1,itlb_dmp_vld_d1}),

        .q      ({dtlb_dmp_vld_d1,itlb_dmp_vld_d1}),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

assign  tlu_dtlb_dmp_vld_g = dtlb_dmp_vld_d1 & ~dtlb_done_d1 ;

assign  tlu_dtlb_dmp_vld_g = dtlb_dmp_vld_d1 & ~dtlb_done_d1 ;

assign  tlu_itlb_dmp_vld_g = itlb_dmp_vld_d1 & ~itlb_done_d1 ;

assign  tlu_itlb_dmp_vld_g = itlb_dmp_vld_d1 & ~itlb_done_d1 ;

wire    stxa_ack ;

wire    stxa_ack ;

Line 2068...

Line 1799...

        (demap_sctxt & tlb_st_inst_g & (immu_demap_en & ~idemap_all)) | // Bug5053

        (demap_sctxt & tlb_st_inst_g & (immu_demap_en & ~idemap_all)) | // Bug5053

                                                // iside should not use sctxt

                                                // iside should not use sctxt

        // lng-latency store needs to signal cmplt to lsu even with illegal va

        // lng-latency store needs to signal cmplt to lsu even with illegal va

        (tlb_st_inst_unflushed & (dmmu_async_illgl_va_g | immu_async_illgl_va_g)) ;

        (tlb_st_inst_unflushed & (dmmu_async_illgl_va_g | immu_async_illgl_va_g)) ;

dff  #(1) stack_d1 (

dff_s  #(1) stack_d1 (

        .din    (stxa_ack),

        .din    (stxa_ack),

        .q      (tlu_lsu_stxa_ack),

        .q      (tlu_lsu_stxa_ack),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

//=========================================================================================

//=========================================================================================

//      AUTODEMAP

//      AUTODEMAP

//=========================================================================================

//=========================================================================================

Line 2092...

Line 1823...

                        & tlb_write_mode & ~tlb_admp_mode_d1) ;

                        & tlb_write_mode & ~tlb_admp_mode_d1) ;

assign  tlu_admp_key_sel = (dtlb_wr_vld_g | itlb_wr_vld_g) | tlb_admp_mode ;

assign  tlu_admp_key_sel = (dtlb_wr_vld_g | itlb_wr_vld_g) | tlb_admp_mode ;

// 1st Phase - Autodemap

// 1st Phase - Autodemap

dffre  #(1) dmp1_ff (

dffre_s  #(1) dmp1_ff (

        .din    (tlb_wr_vld_g),

        .din    (tlb_wr_vld_g),

        .q      (tlb_admp_mode),

        .q      (tlb_admp_mode),

        .rst    (tlb_admp_rst), .en     (tlb_admp_en),

        .rst    (tlb_admp_rst), .en     (tlb_admp_en),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

// this is temporary - IFU is spuriously sourcing extra done signal.

// this is temporary - IFU is spuriously sourcing extra done signal.

dff  #(1) admp_d1 (

dff_s  #(1) admp_d1 (

        .din    (tlb_admp_mode),

        .din    (tlb_admp_mode),

        .q      (tlb_admp_mode_d1),

        .q      (tlb_admp_mode_d1),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

// 2nd Phase - Follow-up with Write

// 2nd Phase - Follow-up with Write

dffre  #(1) dmp2_ff (

dffre_s  #(1) dmp2_ff (

        .din    (tlb_admp_rst),

        .din    (tlb_admp_rst),

        .q      (tlb_write_mode),

        .q      (tlb_write_mode),

        .rst    (tlb_wr_rst),   .en     (tlb_admp_rst),

        .rst    (tlb_wr_rst),   .en     (tlb_admp_rst),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

//=========================================================================================

//=========================================================================================

wire    tlu_ldxa_async_data_vld ;

wire    tlu_ldxa_async_data_vld ;

Line 2161...

Line 1892...

assign  tlu_ldxa_data_vld = tlu_ildxa_data_vld | tlu_dldxa_data_vld ;

assign  tlu_ldxa_data_vld = tlu_ildxa_data_vld | tlu_dldxa_data_vld ;

        // Flush needs to be removed.

        // Flush needs to be removed.

        assign  lsu_exu_ldxa_m = tlu_ldxa_data_vld & ~(dmmu_sync_illgl_va_m | immu_sync_illgl_va_m);

        assign  lsu_exu_ldxa_m = tlu_ldxa_data_vld & ~(dmmu_sync_illgl_va_m | immu_sync_illgl_va_m);

dff #(1) stg_asyncdvld (

dff_s #(1) stg_asyncdvld (

        .din    (tlu_ldxa_async_data_vld),

        .din    (tlu_ldxa_async_data_vld),

        .q      (tlu_lsu_ldxa_async_data_vld),

        .q      (tlu_lsu_ldxa_async_data_vld),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

//=========================================================================================

//=========================================================================================

//      SFSR/SFAR Control

//      SFSR/SFAR Control

//=========================================================================================

//=========================================================================================

Line 2198...

Line 1929...

// TSB Size Logic - Form 8 bits for 8k and 64k Ptr regs respectively.

// TSB Size Logic - Form 8 bits for 8k and 64k Ptr regs respectively.

// Macrotest support for logic in shadow of mra scan collar.

// Macrotest support for logic in shadow of mra scan collar.

// Scan only. Scan value valid in 2nd cycle of macrotest.

// Scan only. Scan value valid in 2nd cycle of macrotest.

wire    mtest_rdps0_sel ;

wire    mtest_rdps0_sel ;

dff  #(1) rps0d_d1 (

dff_s  #(1) rps0d_d1 (

        .din    (1'b0),

        .din    (1'b0),

        .q      (mtest_rdps0_sel),

        .q      (mtest_rdps0_sel),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

) ;

) ;

wire    tsb_rd_ps0_sel ;

wire    tsb_rd_ps0_sel ;

assign  tlu_tsb_rd_ps0_sel = tsb_rd_ps0_sel ;

assign  tlu_tsb_rd_ps0_sel = tsb_rd_ps0_sel ;

assign  tsb_rd_ps0_sel =

assign  tsb_rd_ps0_sel =

Line 2263...

Line 1994...

wire    tsb_split_d1 ;

wire    tsb_split_d1 ;

wire    [47:13] tsb_base_d1 ;

wire    [47:13] tsb_base_d1 ;

wire    ps1_d1 ;

wire    ps1_d1 ;

wire    [23:0]   va_d1 ;

wire    [23:0]   va_d1 ;

dff  #(4) tsbsize_stgd1 (

dff_s  #(4) tsbsize_stgd1 (

        .din    (tsb_size[3:0]),

        .din    (tsb_size[3:0]),

        .q      (tsb_size_d1[3:0]),

        .q      (tsb_size_d1[3:0]),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

) ;

) ;

dff  #(1) tsbsplit_stgd1 (

dff_s  #(1) tsbsplit_stgd1 (

        .din    (tsb_split),

        .din    (tsb_split),

        .q      (tsb_split_d1),

        .q      (tsb_split_d1),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

) ;

) ;

assign  tsb_base_d1[47:13] = tlu_tsb_base_w2_d1[47:13] ;

assign  tsb_base_d1[47:13] = tlu_tsb_base_w2_d1[47:13] ;

dff  #(1) ps1_stgd1 (

dff_s  #(1) ps1_stgd1 (

        .din    (ps1),

        .din    (ps1),

        .q      (ps1_d1),

        .q      (ps1_d1),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

) ;

) ;

dff  #(24) va_stgd1 (

dff_s  #(24) va_stgd1 (

        .din    (va[23:0]),

        .din    (va[23:0]),

        .q      (va_d1[23:0]),

        .q      (va_d1[23:0]),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

) ;

) ;

// These equations have to be optimized.

// These equations have to be optimized.

assign  ptr[28] = ((tsb_size_d1==4'd15) & tsb_split_d1) ? ps1_d1 : tsb_base_d1[28] ;

assign  ptr[28] = ((tsb_size_d1==4'd15) & tsb_split_d1) ? ps1_d1 : tsb_base_d1[28] ;

assign  ptr[27] = (tsb_size_d1==4'd15) ? va_d1[23] : ((tsb_size_d1==4'd14) & tsb_split_d1) ? ps1_d1 : tsb_base_d1[27] ;

assign  ptr[27] = (tsb_size_d1==4'd15) ? va_d1[23] : ((tsb_size_d1==4'd14) & tsb_split_d1) ? ps1_d1 : tsb_base_d1[27] ;

Line 2335...

Line 2066...

// write of tag-access ctxt needs to be setup in M for subsequent read of MRA in M.

// write of tag-access ctxt needs to be setup in M for subsequent read of MRA in M.

assign  tsb_page_size_g[2:0] = tsb_rd_ps0_sel ? tlu_ctxt_cfg_w2[2:0] : tlu_ctxt_cfg_w2[5:3] ;

assign  tsb_page_size_g[2:0] = tsb_rd_ps0_sel ? tlu_ctxt_cfg_w2[2:0] : tlu_ctxt_cfg_w2[5:3] ;

// Listening Flops for Macrotest of mra.

// Listening Flops for Macrotest of mra.

dff #(6) ctxtcfg_listen (

dff_s #(6) ctxtcfg_listen (

        .din    (tlu_ctxt_cfg_w2[5:0]),

        .din    (tlu_ctxt_cfg_w2[5:0]),

        .q      (),

        .q      (),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

//=========================================================================================

//=========================================================================================

Line 2372...

Line 2103...

                                (thread2_e & ~dptr2_pg64k_vld) |

                                (thread2_e & ~dptr2_pg64k_vld) |

                                (thread3_e & ~dptr3_pg64k_vld));

                                (thread3_e & ~dptr3_pg64k_vld));

wire    dptr_state_din ;

wire    dptr_state_din ;

        assign dptr_state_din = dacc_prot_ps1_match ;

        assign dptr_state_din = dacc_prot_ps1_match ;

dffre  #(1) dptrstate_0 (

dffre_s  #(1) dptrstate_0 (

        .din    (dptr_state_din),

        .din    (dptr_state_din),

        .q      (dptr0_pg64k_vld),

        .q      (dptr0_pg64k_vld),

        .rst    (~rst_l),       .en     (dptr0_pg64k_en),

        .rst    (~rst_l),       .en     (dptr0_pg64k_en),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

dffre  #(1) dptrstate_1 (

dffre_s  #(1) dptrstate_1 (

        .din    (dptr_state_din),

        .din    (dptr_state_din),

        .q      (dptr1_pg64k_vld),

        .q      (dptr1_pg64k_vld),

        .rst    (~rst_l),       .en     (dptr1_pg64k_en),

        .rst    (~rst_l),       .en     (dptr1_pg64k_en),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

dffre  #(1) dptrstate_2 (

dffre_s  #(1) dptrstate_2 (

        .din    (dptr_state_din),

        .din    (dptr_state_din),

        .q      (dptr2_pg64k_vld),

        .q      (dptr2_pg64k_vld),

        .rst    (~rst_l),       .en     (dptr2_pg64k_en),

        .rst    (~rst_l),       .en     (dptr2_pg64k_en),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

dffre  #(1) dptrstate_3 (

dffre_s  #(1) dptrstate_3 (

        .din    (dptr_state_din),

        .din    (dptr_state_din),

        .q      (dptr3_pg64k_vld),

        .q      (dptr3_pg64k_vld),

        .rst    (~rst_l),       .en     (dptr3_pg64k_en),

        .rst    (~rst_l),       .en     (dptr3_pg64k_en),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

//=========================================================================================

//=========================================================================================

//      PS1 PAGE SIZE FOR DMMU

//      PS1 PAGE SIZE FOR DMMU

//=========================================================================================

//=========================================================================================

Line 2429...

Line 2160...

assign  dnzctxt_cfg_wr_en[1] = dmmu_nzctxt_cfg_en & st_inst_g & thread1_sel_g ;

assign  dnzctxt_cfg_wr_en[1] = dmmu_nzctxt_cfg_en & st_inst_g & thread1_sel_g ;

assign  dnzctxt_cfg_wr_en[0] = dmmu_nzctxt_cfg_en & st_inst_g & thread0_sel_g ;

assign  dnzctxt_cfg_wr_en[0] = dmmu_nzctxt_cfg_en & st_inst_g & thread0_sel_g ;

// Thread0

// Thread0

// Zero-Ctxt Cfg PS1

// Zero-Ctxt Cfg PS1

dffe #(3)   zctxtps1_0 (

dffe_s #(3)   zctxtps1_0 (

        .din    (lsu_tlu_st_rs3_data_b12t0_g[10:8]),

        .din    (lsu_tlu_st_rs3_data_b12t0_g[10:8]),

        .q      (zctxt_cfg0_ps1[2:0]),

        .q      (zctxt_cfg0_ps1[2:0]),

        .en     (dzctxt_cfg_wr_en[0]),   .clk (clk),

        .en     (dzctxt_cfg_wr_en[0]),   .clk (clk),

        .se     (1'b0),         .si (),          .so ()

        .se     (1'b0),         `SIMPLY_RISC_SCANIN,          .so ()

);

);

// Non-Zero-Ctxt Cfg PS1

// Non-Zero-Ctxt Cfg PS1

dffe #(3)   nzctxtps1_0 (

dffe_s #(3)   nzctxtps1_0 (

        .din    (lsu_tlu_st_rs3_data_b12t0_g[10:8]),

        .din    (lsu_tlu_st_rs3_data_b12t0_g[10:8]),

        .q      (nzctxt_cfg0_ps1[2:0]),

        .q      (nzctxt_cfg0_ps1[2:0]),

        .en     (dnzctxt_cfg_wr_en[0]),  .clk (clk),

        .en     (dnzctxt_cfg_wr_en[0]),  .clk (clk),

        .se     (1'b0),         .si (),          .so ()

        .se     (1'b0),         `SIMPLY_RISC_SCANIN,          .so ()

);

);

// Thread1

// Thread1

// Zero-Ctxt Cfg PS1

// Zero-Ctxt Cfg PS1

dffe #(3)   zctxtps1_1 (

dffe_s #(3)   zctxtps1_1 (

        .din    (lsu_tlu_st_rs3_data_b12t0_g[10:8]),

        .din    (lsu_tlu_st_rs3_data_b12t0_g[10:8]),

        .q      (zctxt_cfg1_ps1[2:0]),

        .q      (zctxt_cfg1_ps1[2:0]),

        .en     (dzctxt_cfg_wr_en[1]),  .clk (clk),

        .en     (dzctxt_cfg_wr_en[1]),  .clk (clk),

        .se     (1'b0),         .si (),          .so ()

        .se     (1'b0),         `SIMPLY_RISC_SCANIN,          .so ()

);

);

// Non-Zero-Ctxt Cfg PS1

// Non-Zero-Ctxt Cfg PS1

dffe #(3)   nzctxtps1_1 (

dffe_s #(3)   nzctxtps1_1 (

        .din    (lsu_tlu_st_rs3_data_b12t0_g[10:8]),

        .din    (lsu_tlu_st_rs3_data_b12t0_g[10:8]),

        .q      (nzctxt_cfg1_ps1[2:0]),

        .q      (nzctxt_cfg1_ps1[2:0]),

        .en     (dnzctxt_cfg_wr_en[1]),         .clk (clk),

        .en     (dnzctxt_cfg_wr_en[1]),         .clk (clk),

        .se     (1'b0),         .si (),          .so ()

        .se     (1'b0),         `SIMPLY_RISC_SCANIN,          .so ()

);

);

// Thread2

// Thread2

// Zero-Ctxt Cfg PS1

// Zero-Ctxt Cfg PS1

dffe #(3)   zctxtps1_2 (

dffe_s #(3)   zctxtps1_2 (

        .din    (lsu_tlu_st_rs3_data_b12t0_g[10:8]),

        .din    (lsu_tlu_st_rs3_data_b12t0_g[10:8]),

        .q      (zctxt_cfg2_ps1[2:0]),

        .q      (zctxt_cfg2_ps1[2:0]),

        .en     (dzctxt_cfg_wr_en[2]),  .clk (clk),

        .en     (dzctxt_cfg_wr_en[2]),  .clk (clk),

        .se     (1'b0),         .si (),          .so ()

        .se     (1'b0),         `SIMPLY_RISC_SCANIN,          .so ()

);

);

// Non-Zero-Ctxt Cfg PS1

// Non-Zero-Ctxt Cfg PS1

dffe #(3)   nzctxtps1_2 (

dffe_s #(3)   nzctxtps1_2 (

        .din    (lsu_tlu_st_rs3_data_b12t0_g[10:8]),

        .din    (lsu_tlu_st_rs3_data_b12t0_g[10:8]),

        .q      (nzctxt_cfg2_ps1[2:0]),

        .q      (nzctxt_cfg2_ps1[2:0]),

        .en     (dnzctxt_cfg_wr_en[2]),         .clk (clk),

        .en     (dnzctxt_cfg_wr_en[2]),         .clk (clk),

        .se     (1'b0),         .si (),          .so ()

        .se     (1'b0),         `SIMPLY_RISC_SCANIN,          .so ()

);

);

// Thread3

// Thread3

// Zero-Ctxt Cfg PS1

// Zero-Ctxt Cfg PS1

dffe #(3)   zctxtps1_3 (

dffe_s #(3)   zctxtps1_3 (

        .din    (lsu_tlu_st_rs3_data_b12t0_g[10:8]),

        .din    (lsu_tlu_st_rs3_data_b12t0_g[10:8]),

        .q      (zctxt_cfg3_ps1[2:0]),

        .q      (zctxt_cfg3_ps1[2:0]),

        .en     (dzctxt_cfg_wr_en[3]),  .clk (clk),

        .en     (dzctxt_cfg_wr_en[3]),  .clk (clk),

        .se     (1'b0),         .si (),          .so ()

        .se     (1'b0),         `SIMPLY_RISC_SCANIN,          .so ()

);

);

// Non-Zero-Ctxt Cfg PS1

// Non-Zero-Ctxt Cfg PS1

dffe #(3)   nzctxtps1_3 (

dffe_s #(3)   nzctxtps1_3 (

        .din    (lsu_tlu_st_rs3_data_b12t0_g[10:8]),

        .din    (lsu_tlu_st_rs3_data_b12t0_g[10:8]),

        .q      (nzctxt_cfg3_ps1[2:0]),

        .q      (nzctxt_cfg3_ps1[2:0]),

        .en     (dnzctxt_cfg_wr_en[3]),         .clk (clk),

        .en     (dnzctxt_cfg_wr_en[3]),         .clk (clk),

        .se     (1'b0),         .si (),          .so ()

        .se     (1'b0),         `SIMPLY_RISC_SCANIN,          .so ()

);

);

wire [2:0] zctxt_cfg_ps1,nzctxt_cfg_ps1 ;

wire [2:0] zctxt_cfg_ps1,nzctxt_cfg_ps1 ;

Line 2510...

Line 2241...

        thread0_sel_g ? nzctxt_cfg0_ps1[2:0] :

        thread0_sel_g ? nzctxt_cfg0_ps1[2:0] :

                thread1_sel_g ? nzctxt_cfg1_ps1[2:0] :

                thread1_sel_g ? nzctxt_cfg1_ps1[2:0] :

                        thread2_sel_g ? nzctxt_cfg2_ps1[2:0] :

                        thread2_sel_g ? nzctxt_cfg2_ps1[2:0] :

                                                nzctxt_cfg3_ps1[2:0] ;

                                                nzctxt_cfg3_ps1[2:0] ;

wire    nucleus_ctxt_g ;

wire    nucleus_ctxt_g ;

dff nctxt_stgg(

dff_s nctxt_stgg(

        .din    (lsu_tlu_nucleus_ctxt_m),

        .din    (lsu_tlu_nucleus_ctxt_m),

        .q      (nucleus_ctxt_g),

        .q      (nucleus_ctxt_g),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

wire    [2:0]    ctxt_cfg_ps1 ;

wire    [2:0]    ctxt_cfg_ps1 ;

assign  ctxt_cfg_ps1[2:0] =

assign  ctxt_cfg_ps1[2:0] =

        nucleus_ctxt_g ? zctxt_cfg_ps1[2:0] : nzctxt_cfg_ps1[2:0] ;

        nucleus_ctxt_g ? zctxt_cfg_ps1[2:0] : nzctxt_cfg_ps1[2:0] ;

Line 2534...

Line 2265...

assign thread_tl_zero_e =

assign thread_tl_zero_e =

        thread0_e ? tlu_lsu_tl_zero[0] :

        thread0_e ? tlu_lsu_tl_zero[0] :

                thread1_e ? tlu_lsu_tl_zero[1] :

                thread1_e ? tlu_lsu_tl_zero[1] :

                        thread2_e ? tlu_lsu_tl_zero[2] : tlu_lsu_tl_zero[3];

                        thread2_e ? tlu_lsu_tl_zero[2] : tlu_lsu_tl_zero[3];

dff tlz_stgm(

dff_s tlz_stgm(

        .din    (thread_tl_zero_e),

        .din    (thread_tl_zero_e),

        .q      (thread_tl_zero_m),

        .q      (thread_tl_zero_m),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

// Generate selects for ctxt to be written to tag_access

// Generate selects for ctxt to be written to tag_access

// iside trap meant to cover immu_miss and inst_access_excp

// iside trap meant to cover immu_miss and inst_access_excp

// modified for hypervisor support

// modified for hypervisor support

Line 2553...

Line 2284...

        (thread0_e & tlu_lsu_pstate_am[0]) |

        (thread0_e & tlu_lsu_pstate_am[0]) |

        (thread1_e & tlu_lsu_pstate_am[1]) |

        (thread1_e & tlu_lsu_pstate_am[1]) |

        (thread2_e & tlu_lsu_pstate_am[2]) |

        (thread2_e & tlu_lsu_pstate_am[2]) |

        (thread3_e & tlu_lsu_pstate_am[3]);

        (thread3_e & tlu_lsu_pstate_am[3]);

dff pam_stgm(

dff_s pam_stgm(

        .din    (pstate_am_e),

        .din    (pstate_am_e),

        .q      (pstate_am_m),

        .q      (pstate_am_m),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

wire    immu_va_oor_brnchetc_m ;

wire    immu_va_oor_brnchetc_m ;

assign  immu_va_oor_brnchetc_m

assign  immu_va_oor_brnchetc_m

        = exu_tlu_va_oor_m & ~pstate_am_m & ~memref_m;

        = exu_tlu_va_oor_m & ~pstate_am_m & ~memref_m;

Line 2632...

Line 2363...

assign  err_inj_ack[0] = tlb_wr_vld & d_tag_invrt_par ;

assign  err_inj_ack[0] = tlb_wr_vld & d_tag_invrt_par ;

assign  err_inj_ack[1] = tlb_wr_vld & d_data_invrt_par ;

assign  err_inj_ack[1] = tlb_wr_vld & d_data_invrt_par ;

assign  err_inj_ack[2] = tlb_wr_vld & i_tag_invrt_par ;

assign  err_inj_ack[2] = tlb_wr_vld & i_tag_invrt_par ;

assign  err_inj_ack[3] = tlb_wr_vld & i_data_invrt_par ;

assign  err_inj_ack[3] = tlb_wr_vld & i_data_invrt_par ;

dff #(4) err_inj (

dff_s #(4) err_inj (

        .din    (err_inj_ack[3:0]),

        .din    (err_inj_ack[3:0]),

        .q      (lsu_ifu_inj_ack[3:0]),

        .q      (lsu_ifu_inj_ack[3:0]),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

endmodule

endmodule

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[/] [s1_core/] [trunk/] [hdl/] [rtl/] [sparc_core/] [tlu_mmu_ctl.v] - Diff between revs 105 and 113