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Line 16... Line 16... 
// You should have received a copy of the GNU General Public
 
// You should have received a copy of the GNU General Public
 
// License along with this work; if not, write to the Free Software
 
// License along with this work; if not, write to the Free Software
 
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
 
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
 
// 
// 
// ========== Copyright Header End ============================================
 
// ========== Copyright Header End ============================================
 
 
 
`ifdef SIMPLY_RISC_TWEAKS
 
 
 
`define SIMPLY_RISC_SCANIN .si(0)
 
 
 
`else
 
 
 
`define SIMPLY_RISC_SCANIN .si()
 
 
 
`endif
 
////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////
 
/*
 
/*
 
//      Description:    Trap Control Logic
 
//      Description:    Trap Control Logic
 
*/
 
*/
 
 
 
 
 
////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////
 
// Local header file includes / local defines
 
// Local header file includes / local defines
 
////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////
 
/*
 
`include "tlu.h"
 
/* ========== Copyright Header Begin ==========================================
 
 
 
*
 
 
 
* OpenSPARC T1 Processor File: tlu.h
 
 
 
* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
 
 
 
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
 
 
 
*
 
 
 
* The above named program is free software; you can redistribute it and/or
 
 
 
* modify it under the terms of the GNU General Public
 
 
 
* License version 2 as published by the Free Software Foundation.
 
 
 
*
 
 
 
* The above named program is distributed in the hope that it will be
 
 
 
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
 
 
 
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 
 
 
* General Public License for more details.
 
 
 
*
 
 
 
* You should have received a copy of the GNU General Public
 
 
 
* License along with this work; if not, write to the Free Software
 
 
 
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
 
 
 
*
 
 
 
* ========== Copyright Header End ============================================
 
 
 
*/
 
 
 
// ifu trap types
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// modified for hypervisor support
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
// modified due to bug 2588
 
 
 
// `define      TSA_PSTATE_VRANGE2_LO 16 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// added due to Niagara SRAMs methodology
 
 
 
// The following defines have been replaced due
 
 
 
// the memory macro replacement from:
 
 
 
// bw_r_rf32x144 -> 2x bw_r_rf32x80
 
 
 
/*
 
 
 
`define TSA_MEM_WIDTH     144
 
 
 
`define TSA_HTSTATE_HI    142 //  3 bits
 
 
 
`define TSA_HTSTATE_LO    140
 
 
 
`define TSA_TPC_HI        138 // 47 bits
 
 
 
`define TSA_TPC_LO         92
 
 
 
`define TSA_TNPC_HI        90 // 47 bits
 
 
 
`define TSA_TNPC_LO        44
 
 
 
`define TSA_TSTATE_HI      40 // 29 bits
 
 
 
`define TSA_TSTATE_LO      12
 
 
 
`define TSA_TTYPE_HI        8 //  9 bits
 
 
 
`define TSA_TTYPE_LO        0
 
 
 
`define TSA_MEM_CWP_LO     12
 
 
 
`define TSA_MEM_CWP_HI     14
 
 
 
`define TSA_MEM_PSTATE_LO  15
 
 
 
`define TSA_MEM_PSTATE_HI  22
 
 
 
`define TSA_MEM_ASI_LO     23
 
 
 
`define TSA_MEM_ASI_HI     30
 
 
 
`define TSA_MEM_CCR_LO     31
 
 
 
`define TSA_MEM_CCR_HI     38
 
 
 
`define TSA_MEM_GL_LO      39
 
 
 
`define TSA_MEM_GL_HI      40
 
 
 
*/
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// HPSTATE position definitions within wsr
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// TSTATE postition definitions within wsr
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// modified due to bug 2588
 
 
 
 
 
 
 
 
 
 
 
// added for bug 2584 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// tick_cmp and stick_cmp definitions
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// PIB WRAP
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// HPSTATE postition definitions
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// HTBA definitions
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// TBA definitions
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// added for the hypervisor support
 
 
 
 
 
 
 
 
 
 
 
// modified due to bug 2588
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// compressed PSTATE WSR definitions
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// ASI_QUEUE for hypervisor
 
 
 
// Queues are: CPU_MONODO
 
 
 
//             DEV_MONODO
 
 
 
//             RESUMABLE_ERROR
 
 
 
//             NON_RESUMABLE_ERROR
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// for address range checking
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// Niagara scratch-pads
 
 
 
// VA address of 0x20 and 0x28 are exclusive to hypervisor
 
 
 
// 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// range checking 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// PIB related definitions
 
 
 
// Bit definition for events
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// 
 
 
// PIB related definitions
 
 
 
// PCR and PIC address definitions
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// 
 
 
// PCR bit definitions
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// PIC definitions
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// PIC  mask bit position definitions
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// added define from sparc_tlu_int.v 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// shadow scan related definitions 
 
 
 
 
 
 
// modified due to logic redistribution
 
 
 
// `define TCL_SSCAN_WIDTH 12 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// `define TCL_SSCAN_LO 51 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// 
 
 
// position definitions - TDP
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// 
 
 
// position definitions - TCL
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// 
 
 
// To speedup POR for verification purposes
 
 
 
 
 
 
 
 
 
 
 
module tlu_tcl (/*AUTOARG*/
 
module tlu_tcl (/*AUTOARG*/
 
   // Outputs
 
   // Outputs
 
   tlu_ifu_trappc_vld_w1, tlu_ifu_trapnpc_vld_w1, tlu_ifu_trap_tid_w1,
 
   tlu_ifu_trappc_vld_w1, tlu_ifu_trapnpc_vld_w1, tlu_ifu_trap_tid_w1,
 
   tlu_trap_hpstate_enb, tsa_wr_tpl, tsa_rd_tid, tsa_rd_tpl, tsa_rd_en,
 
   tlu_trap_hpstate_enb, tsa_wr_tpl, tsa_rd_tid, tsa_rd_tpl, tsa_rd_en,
Line 488... Line 95... 
   );
 
   );
 
 
 
 
 
/*AUTOINPUT*/
 
/*AUTOINPUT*/
 
// Beginning of automatic inputs (from unused autoinst inputs)
 
// Beginning of automatic inputs (from unused autoinst inputs)
 
// End of automatics
 
// End of automatics
 
input [7-1:0] ifu_tlu_sraddr_d;      // addr of sr(st/pr)
 
input [`TLU_ASR_ADDR_WIDTH-1:0] ifu_tlu_sraddr_d;      // addr of sr(st/pr)
 
input       ifu_tlu_rsr_inst_d;    // valid rd sr(st/pr)
 
input       ifu_tlu_rsr_inst_d;    // valid rd sr(st/pr)
 
// input       ifu_tlu_wsr_inst_d;    // valid wr sr(st/pr)
 
// input       ifu_tlu_wsr_inst_d;    // valid wr sr(st/pr)
 
input       lsu_tlu_wsr_inst_e;    // valid wr sr(st/pr)
 
input       lsu_tlu_wsr_inst_e;    // valid wr sr(st/pr)
 
input           tlu_wsr_data_b63_w;    // b63 of wsr data
 
input           tlu_wsr_data_b63_w;    // b63 of wsr data
 
// input        tlu_wsr_data_b16_w;    // b16 of wsr data
 
// input        tlu_wsr_data_b16_w;    // b16 of wsr data
Line 559... Line 166... 
 
 
 
 
input           ifu_tlu_rstint_m;       // reset interrupt
 
input           ifu_tlu_rstint_m;       // reset interrupt
 
input           ifu_tlu_hwint_m;        // hw interrupt
 
input           ifu_tlu_hwint_m;        // hw interrupt
 
input           ifu_tlu_swint_m;        // sw interrupt
 
input           ifu_tlu_swint_m;        // sw interrupt
 
input [5:0]      int_tlu_rstid_m;        // reset type
 
input [5:0]      int_tlu_rstid_m;        // reset type
 
input [4-1:0] tlu_int_pstate_ie;      // interrupt enable
 
input [`TLU_THRD_NUM-1:0] tlu_int_pstate_ie;      // interrupt enable
 
input [4-1:0] tlu_int_redmode;        // redmode
 
input [`TLU_THRD_NUM-1:0] tlu_int_redmode;        // redmode
 
// input  [`TLU_THRD_NUM-1:0]   const_cpuid;
 
// input  [`TLU_THRD_NUM-1:0]   const_cpuid;
 
 
 
 
 
input [4-1:0] tlu_sftint_id;
 
input [`TLU_THRD_NUM-1:0] tlu_sftint_id;
 
input [4-1:0] pich_wrap_flg;
 
input [`TLU_THRD_NUM-1:0] pich_wrap_flg;
 
input [4-1:0] pich_onebelow_flg;
 
input [`TLU_THRD_NUM-1:0] pich_onebelow_flg;
 
input [4-1:0] pich_twobelow_flg;
 
input [`TLU_THRD_NUM-1:0] pich_twobelow_flg;
 
input [4-1:0] pib_picl_wrap;
 
input [`TLU_THRD_NUM-1:0] pib_picl_wrap;
 
// modified for bug 5436: Niagara 2.0
 
// modified for bug 5436: Niagara 2.0
 
input [4-1:0] tlu_pcr_ut;
 
input [`TLU_THRD_NUM-1:0] tlu_pcr_ut;
 
input [4-1:0] tlu_pcr_st;
 
input [`TLU_THRD_NUM-1:0] tlu_pcr_st;
 
// input tlu_pic_wrap_e, tlu_pcr_ut_e, tlu_pcr_st_e;
 
// input tlu_pic_wrap_e, tlu_pcr_ut_e, tlu_pcr_st_e;
 
input tlu_pic_wrap_e;
 
input tlu_pic_wrap_e;
 
 
 
 
 
// input                tlu_tick_match; // match between tick and tick-cmp 
// input                tlu_tick_match; // match between tick and tick-cmp 
// input                tlu_stick_match;        // match between tick and stick-cmp 
// input                tlu_stick_match;        // match between tick and stick-cmp 
// input  [`TLU_THRD_NUM-1:0] pib_pic_wrap; // overflow for the pic registers - lvl15 int 
// input  [`TLU_THRD_NUM-1:0] pib_pic_wrap; // overflow for the pic registers - lvl15 int 
// modified for timing support
 
// modified for timing support
 
// input  [`TLU_THRD_NUM-1:0] pib_priv_act_trap; // access priv violation of the pics 
// input  [`TLU_THRD_NUM-1:0] pib_priv_act_trap; // access priv violation of the pics 
input  [4-1:0] pib_priv_act_trap_m; // access priv violation of the pics 
input  [`TLU_THRD_NUM-1:0] pib_priv_act_trap_m; // access priv violation of the pics 
 
 
 
 
input           lsu_tlu_misalign_addr_ldst_atm_m;// misaligned addr - ld,st,atomic 
input           lsu_tlu_misalign_addr_ldst_atm_m;// misaligned addr - ld,st,atomic 
input           exu_tlu_misalign_addr_jmpl_rtn_m;// misaligned addr - jmpl or return addr
 
input           exu_tlu_misalign_addr_jmpl_rtn_m;// misaligned addr - jmpl or return addr
 
// input                lsu_tlu_priv_violtn_g;          // privileged violation trap
 
// input                lsu_tlu_priv_violtn_g;          // privileged violation trap
 
input           lsu_tlu_priv_action_g;          // privileged action trap
 
input           lsu_tlu_priv_action_g;          // privileged action trap
Line 605... Line 212... 
input       tlu_htstate_rw_d;
 
input       tlu_htstate_rw_d;
 
input       tlu_htstate_rw_g;
 
input       tlu_htstate_rw_g;
 
input       tlu_htickcmp_rw_e;
 
input       tlu_htickcmp_rw_e;
 
// input       tlu_gl_rw_g;
 
// input       tlu_gl_rw_g;
 
input       tlu_gl_rw_m;
 
input       tlu_gl_rw_m;
 
input [4-1:0] tlu_hpstate_priv;
 
input [`TLU_THRD_NUM-1:0] tlu_hpstate_priv;
 
input [4-1:0] tlu_hpstate_enb;
 
input [`TLU_THRD_NUM-1:0] tlu_hpstate_enb;
 
input [4-1:0] tlu_hpstate_tlz;
 
input [`TLU_THRD_NUM-1:0] tlu_hpstate_tlz;
 
input [4-1:0] tlu_cpu_mondo_cmp;
 
input [`TLU_THRD_NUM-1:0] tlu_cpu_mondo_cmp;
 
input [4-1:0] tlu_dev_mondo_cmp;
 
input [`TLU_THRD_NUM-1:0] tlu_dev_mondo_cmp;
 
input [4-1:0] tlu_resum_err_cmp;
 
input [`TLU_THRD_NUM-1:0] tlu_resum_err_cmp;
 
input [4-1:0] tlu_hintp;
 
input [`TLU_THRD_NUM-1:0] tlu_hintp;
 
// input [48:0] ifu_tlu_pc_m;
 
// input [48:0] ifu_tlu_pc_m;
 
input [48:0] ifu_tlu_npc_m;
 
input [48:0] ifu_tlu_npc_m;
 
// input [33:0] tlu_partial_trap_pc_w1;
 
// input [33:0] tlu_partial_trap_pc_w1;
 
// modified for bug 3017
 
// modified for bug 3017
 
// logic moved to tlu_misctl
 
// logic moved to tlu_misctl
Line 624... Line 231... 
// added for timing
 
// added for timing
 
input [4:0] tlu_hyperv_rdpr_sel;
 
input [4:0] tlu_hyperv_rdpr_sel;
 
input [1:0]      tlu_tckctr_in;
 
input [1:0]      tlu_tckctr_in;
 
input           rclk; // clock
 
input           rclk; // clock
 
// sscan tid
 
// sscan tid
 
input [4-1:0] ctu_sscan_tid;
 
input [`TLU_THRD_NUM-1:0] ctu_sscan_tid;
 
//
 
//
 
// modified to abide to the niagara reset methodology
 
// modified to abide to the niagara reset methodology
 
input           grst_l;                         // global reset - active log
 
input           grst_l;                         // global reset - active log
 
input           arst_l;                         // global reset - active log
 
input           arst_l;                         // global reset - active log
 
input           rst_tri_en;                     // global reset - active log
 
input           rst_tri_en;                     // global reset - active log
Line 641... Line 248... 
output           tlu_ifu_trappc_vld_w1; // trap pc or pc on retry.
 
output           tlu_ifu_trappc_vld_w1; // trap pc or pc on retry.
 
output           tlu_ifu_trapnpc_vld_w1;// trap pc or pc on retry.
 
output           tlu_ifu_trapnpc_vld_w1;// trap pc or pc on retry.
 
output [1:0] tlu_ifu_trap_tid_w1;        // thread id.
 
output [1:0] tlu_ifu_trap_tid_w1;        // thread id.
 
output       tlu_trap_hpstate_enb;
 
output       tlu_trap_hpstate_enb;
 
output       tlu_restore_pc_sel_w1;
 
output       tlu_restore_pc_sel_w1;
 
output [4-1:0] pib_pich_wrap;
 
output [`TLU_THRD_NUM-1:0] pib_pich_wrap;
 
output tlu_tcc_inst_w;
 
output tlu_tcc_inst_w;
 
 
 
 
 
output [2:0] tsa_wr_tpl;         // trap level for wr.
 
output [2:0] tsa_wr_tpl;         // trap level for wr.
 
output [1:0] tsa_rd_tid;         // thread id for wr.
 
output [1:0] tsa_rd_tid;         // thread id for wr.
 
output [2:0] tsa_rd_tpl;         // trap level for rd.
 
output [2:0] tsa_rd_tpl;         // trap level for rd.
Line 683... Line 290... 
output [2:0] tlu_true_pc_sel_w;
 
output [2:0] tlu_true_pc_sel_w;
 
// output       tlu_retry_inst_m;  // valid retry inst
 
// output       tlu_retry_inst_m;  // valid retry inst
 
// output       tlu_done_inst_m;   // valid done inst
 
// output       tlu_done_inst_m;   // valid done inst
 
// output       tlu_dnrtry_inst_m_l; // valid done/retry inst - g
 
// output       tlu_dnrtry_inst_m_l; // valid done/retry inst - g
 
output       tlu_tick_en_l;     // tick reg write enable
 
output       tlu_tick_en_l;     // tick reg write enable
 
output [4-1:0]  tlu_tickcmp_en_l;  // tick compare reg write enable
 
output [`TLU_THRD_NUM-1:0]  tlu_tickcmp_en_l;  // tick compare reg write enable
 
output [4-1:0]  tlu_stickcmp_en_l; // stick compare reg write enable
 
output [`TLU_THRD_NUM-1:0]  tlu_stickcmp_en_l; // stick compare reg write enable
 
output [4-1:0]  tlu_htickcmp_en_l; // update htickcmp register 
output [`TLU_THRD_NUM-1:0]  tlu_htickcmp_en_l; // update htickcmp register 
output [4-1:0]  tlu_tba_en_l;      // tba reg write enable
 
output [`TLU_THRD_NUM-1:0]  tlu_tba_en_l;      // tba reg write enable
 
output [4-1:0]  tlu_thrd_wsel_w2;   // thread requiring tsa write.
 
output [`TLU_THRD_NUM-1:0]  tlu_thrd_wsel_w2;   // thread requiring tsa write.
 
output [4-1:0]  tlu_thread_wsel_g; // thread for instruction fetched 
output [`TLU_THRD_NUM-1:0]  tlu_thread_wsel_g; // thread for instruction fetched 
output [9-1:0] tlu_final_ttype_w2;  // selected ttype - w2
 
output [`TSA_TTYPE_WIDTH-1:0] tlu_final_ttype_w2;  // selected ttype - w2
 
// output   tlu_async_trap_taken_g; // async trap taken
 
// output   tlu_async_trap_taken_g; // async trap taken
 
output [4-1:0]  tlu_thread_inst_vld_g; // valid inst for a thread
 
output [`TLU_THRD_NUM-1:0]  tlu_thread_inst_vld_g; // valid inst for a thread
 
// output [`TLU_THRD_NUM-1:0]  tlu_thread_inst_vld_w2; // valid inst for a thread
 
// output [`TLU_THRD_NUM-1:0]  tlu_thread_inst_vld_w2; // valid inst for a thread
 
// output [`TLU_THRD_NUM-1:0]  tlu_update_pc_l_m; // update pc or npc for a thread
 
// output [`TLU_THRD_NUM-1:0]  tlu_update_pc_l_m; // update pc or npc for a thread
 
output [4-1:0]  tlu_update_pc_l_w; // update pc or npc for a thread
 
output [`TLU_THRD_NUM-1:0]  tlu_update_pc_l_w; // update pc or npc for a thread
 
// output [`TLU_THRD_NUM-1:0]  tlu_thrd_rsel_g; // thread requiring tsa read
 
// output [`TLU_THRD_NUM-1:0]  tlu_thrd_rsel_g; // thread requiring tsa read
 
// modified for bug 1767
 
// modified for bug 1767
 
// output               tlu_select_tle; // tle/cle value on trap 
// output               tlu_select_tle; // tle/cle value on trap 
// output [1:0]   tlu_select_mmodel;    // mem. model on trap
 
// output [1:0]   tlu_select_mmodel;    // mem. model on trap
 
output          tlu_select_redmode;     // redmode setting on trap
 
output          tlu_select_redmode;     // redmode setting on trap
Line 733... Line 340... 
// output moved to tlu_misctl
 
// output moved to tlu_misctl
 
// output [2:0] tlu_exu_cwp_m;
 
// output [2:0] tlu_exu_cwp_m;
 
// output [7:0] tlu_exu_ccr_m;
 
// output [7:0] tlu_exu_ccr_m;
 
// output [7:0] tlu_lsu_asi_m;          // asi from stack
 
// output [7:0] tlu_lsu_asi_m;          // asi from stack
 
// added for bug3499
 
// added for bug3499
 
output [4-1:0] tlu_trap_cwp_en;
 
output [`TLU_THRD_NUM-1:0] tlu_trap_cwp_en;
 
 
 
 
 
output       tlu_lsu_asi_update_m; // update asi
 
output       tlu_lsu_asi_update_m; // update asi
 
output [1:0] tlu_lsu_tid_m;              // thread for asi update
 
output [1:0] tlu_lsu_tid_m;              // thread for asi update
 
 
 
 
 
// output        tlu_assist_boot_rst_g; // use rstvaddr all zeroes
 
// output        tlu_assist_boot_rst_g; // use rstvaddr all zeroes
Line 753... Line 360... 
output           tdp_select_tba_w2;     // use tba
 
output           tdp_select_tba_w2;     // use tba
 
//
 
//
 
output           tlu_set_sftint_l_g;    // set sftint
 
output           tlu_set_sftint_l_g;    // set sftint
 
output           tlu_clr_sftint_l_g;    // clr sftint
 
output           tlu_clr_sftint_l_g;    // clr sftint
 
output           tlu_wr_sftint_l_g;     // wr to sftin (asr 16)
 
output           tlu_wr_sftint_l_g;     // wr to sftin (asr 16)
 
output [4-1:0] tlu_sftint_en_l_g; // wr en sftint regs.
 
output [`TLU_THRD_NUM-1:0] tlu_sftint_en_l_g; // wr en sftint regs.
 
output [4-1:0] tlu_sftint_mx_sel; // mux sel sftint regs.
 
output [`TLU_THRD_NUM-1:0] tlu_sftint_mx_sel; // mux sel sftint regs.
 
//
 
//
 
// removed due to sftint recode
 
// removed due to sftint recode
 
// output       [3:0]   tlu_sftint_lvl14_int;   // level 14 sft interrupt
 
// output       [3:0]   tlu_sftint_lvl14_int;   // level 14 sft interrupt
 
 
 
 
 
output [3:0] tlu_sftint_penc_sel;        // select appr. thread for pr. encd.
 
output [3:0] tlu_sftint_penc_sel;        // select appr. thread for pr. encd.
Line 786... Line 393... 
output [1:0] tlu_rdpr_mx4_sel;
 
output [1:0] tlu_rdpr_mx4_sel;
 
output [2:0] tlu_rdpr_mx5_sel;
 
output [2:0] tlu_rdpr_mx5_sel;
 
output [2:0] tlu_rdpr_mx6_sel;
 
output [2:0] tlu_rdpr_mx6_sel;
 
output [3:0] tlu_rdpr_mx7_sel;
 
output [3:0] tlu_rdpr_mx7_sel;
 
//
 
//
 
output [9-1:0] tlu_final_offset_w1;
 
output [`TSA_TTYPE_WIDTH-1:0] tlu_final_offset_w1;
 
// output   [3:0]   tlu_lsu_redmode;            // redmode
 
// output   [3:0]   tlu_lsu_redmode;            // redmode
 
// output [3:0] tlu_lsu_redmode_rst;
 
// output [3:0] tlu_lsu_redmode_rst;
 
// output [`TLU_THRD_NUM-1:0] tlu_lsu_async_ack_w2;
 
// output [`TLU_THRD_NUM-1:0] tlu_lsu_async_ack_w2;
 
output [3:0] tlu_lsu_redmode_rst_d1;
 
output [3:0] tlu_lsu_redmode_rst_d1;
 
output [7:0] lsu_tlu_rsr_data_mod_e;
 
output [7:0] lsu_tlu_rsr_data_mod_e;
Line 798... Line 405... 
//
 
//
 
// added for hypervisor support
 
// added for hypervisor support
 
// modified for timing
 
// modified for timing
 
// output tlu_thrd0_traps, tlu_thrd1_traps;
 
// output tlu_thrd0_traps, tlu_thrd1_traps;
 
// output tlu_thrd2_traps, tlu_thrd3_traps;
 
// output tlu_thrd2_traps, tlu_thrd3_traps;
 
output [4-1:0] tlu_thrd_traps_w2;
 
output [`TLU_THRD_NUM-1:0] tlu_thrd_traps_w2;
 
output tlu_dnrtry0_inst_g, tlu_dnrtry1_inst_g;
 
output tlu_dnrtry0_inst_g, tlu_dnrtry1_inst_g;
 
output tlu_dnrtry2_inst_g, tlu_dnrtry3_inst_g;
 
output tlu_dnrtry2_inst_g, tlu_dnrtry3_inst_g;
 
// output tlu_ibrkpt_trap_g; 
// output tlu_ibrkpt_trap_g; 
output tlu_ibrkpt_trap_w2;
 
output tlu_ibrkpt_trap_w2;
 
output tlu_tick_ctl_din;
 
output tlu_tick_ctl_din;
 
output [4-1:0] tlu_por_rstint_g;
 
output [`TLU_THRD_NUM-1:0] tlu_por_rstint_g;
 
output [4-1:0] tlu_hintp_vld;  // From tcl of tlu_tcl.v
 
output [`TLU_THRD_NUM-1:0] tlu_hintp_vld;  // From tcl of tlu_tcl.v
 
output [4-1:0] tlu_rerr_vld;  // From tcl of tlu_tcl.v
 
output [`TLU_THRD_NUM-1:0] tlu_rerr_vld;  // From tcl of tlu_tcl.v
 
// modified for bug 3017
 
// modified for bug 3017
 
// moved to tlu_misctl
 
// moved to tlu_misctl
 
output [48:0] ifu_npc_w; //ifu_pc_w, 
output [48:0] ifu_npc_w; //ifu_pc_w, 
// 
// 
// shadow scan data from tcl tl and ttype
 
// shadow scan data from tcl tl and ttype
 
output [3-1:0] tlu_sscan_tcl_data;
 
output [`TCL_SSCAN_WIDTH-1:0] tlu_sscan_tcl_data;
 
 
 
 
 
//
 
//
 
// added to abide to the niagara reset methodology
 
// added to abide to the niagara reset methodology
 
output tlu_rst;     // local unit reset - active high
 
output tlu_rst;     // local unit reset - active high
 
// output tlu_rst_l;    // local unit reset - active low
 
// output tlu_rst_l;    // local unit reset - active low
Line 853... Line 460... 
// wire tlu_wr_tsa_inst_g; // write state inst
 
// wire tlu_wr_tsa_inst_g; // write state inst
 
wire tlu_self_boot_rst_g, tlu_self_boot_rst_w2;
 
wire tlu_self_boot_rst_g, tlu_self_boot_rst_w2;
 
wire dnrtry_inst_g;
 
wire dnrtry_inst_g;
 
wire dnrtry0_inst_g, dnrtry1_inst_g;
 
wire dnrtry0_inst_g, dnrtry1_inst_g;
 
wire dnrtry2_inst_g, dnrtry3_inst_g;
 
wire dnrtry2_inst_g, dnrtry3_inst_g;
 
wire [4-1:0] dnrtry_inst_w2;
 
wire [`TLU_THRD_NUM-1:0] dnrtry_inst_w2;
 
wire thrd0_traps,thrd1_traps;
 
wire thrd0_traps,thrd1_traps;
 
wire thrd2_traps,thrd3_traps;
 
wire thrd2_traps,thrd3_traps;
 
// wire [`TLU_THRD_NUM-1:0] async_trap_ack_g;
 
// wire [`TLU_THRD_NUM-1:0] async_trap_ack_g;
 
// wire [`TLU_THRD_NUM-1:0] async_trap_ack_w2;
 
// wire [`TLU_THRD_NUM-1:0] async_trap_ack_w2;
 
wire [2:0]       trp_lvl0,trp_lvl0_new;
 
wire [2:0]       trp_lvl0,trp_lvl0_new;
Line 872... Line 479... 
// wire tlu_pic_onebelow_e, tlu_pic_twobelow_e; 
// wire tlu_pic_onebelow_e, tlu_pic_twobelow_e; 
// experiment
 
// experiment
 
wire pich_wrap_flg_m, tlu_pich_wrap_flg_m; // pich_wrap_flg_e, 
wire pich_wrap_flg_m, tlu_pich_wrap_flg_m; // pich_wrap_flg_e, 
wire tlu_picl_wrap_flg_m; // pich_wrap_flg_e, 
wire tlu_picl_wrap_flg_m; // pich_wrap_flg_e, 
// modified for bug 5436 - Niagara 2.0
 
// modified for bug 5436 - Niagara 2.0
 
wire [4-1:0] pic_cnt_en;
 
wire [`TLU_THRD_NUM-1:0] pic_cnt_en;
 
wire pic_cnt_en_e, pic_cnt_en_m, pic_cnt_en_w, pic_cnt_en_w2;
 
wire pic_cnt_en_e, pic_cnt_en_m, pic_cnt_en_w, pic_cnt_en_w2;
 
// wire pic_trap_en_e; 
// wire pic_trap_en_e; 
//wire pcr_ut_e, pcr_st_e; 
//wire pcr_ut_e, pcr_st_e; 
// wire [`TLU_THRD_NUM-1:0] pich_exu_wrap_e;
 
// wire [`TLU_THRD_NUM-1:0] pich_exu_wrap_e;
 
// wire pic_hpstate_enb_e, pic_hpstate_priv_e, pic_pstate_priv_e; 
// wire pic_hpstate_enb_e, pic_hpstate_priv_e, pic_pstate_priv_e; 
//
 
//
 
wire [4-1:0] tlz_thread_set, tlz_thread_data;
 
wire [`TLU_THRD_NUM-1:0] tlz_thread_set, tlz_thread_data;
 
wire [4-1:0] tlz_thread;
 
wire [`TLU_THRD_NUM-1:0] tlz_thread;
 
wire [4-1:0] tlz_trap_m, tlz_exu_trap_m;
 
wire [`TLU_THRD_NUM-1:0] tlz_trap_m, tlz_exu_trap_m;
 
wire [4-1:0] tlz_trap_nq_g, tlz_trap_g;
 
wire [`TLU_THRD_NUM-1:0] tlz_trap_nq_g, tlz_trap_g;
 
wire [4-1:0] ifu_thrd_flush_w;
 
wire [`TLU_THRD_NUM-1:0] ifu_thrd_flush_w;
 
wire [4-1:0] tlu_none_priv;
 
wire [`TLU_THRD_NUM-1:0] tlu_none_priv;
 
wire cpu_mondo_trap_g, dev_mondo_trap_g;
 
wire cpu_mondo_trap_g, dev_mondo_trap_g;
 
wire cpu_mondo_trap_w2, dev_mondo_trap_w2;
 
wire cpu_mondo_trap_w2, dev_mondo_trap_w2;
 
wire [4-1:0] tlu_cpu_mondo_trap;
 
wire [`TLU_THRD_NUM-1:0] tlu_cpu_mondo_trap;
 
wire [4-1:0] tlu_dev_mondo_trap;
 
wire [`TLU_THRD_NUM-1:0] tlu_dev_mondo_trap;
 
wire [4-1:0] tlu_resum_err_trap;
 
wire [`TLU_THRD_NUM-1:0] tlu_resum_err_trap;
 
wire [4-1:0] tlu_hyper_lite;
 
wire [`TLU_THRD_NUM-1:0] tlu_hyper_lite;
 
wire [3:0] local_rdpr_mx6_sel;
 
wire [3:0] local_rdpr_mx6_sel;
 
wire [3:0] local_rdpr_mx5_sel;
 
wire [3:0] local_rdpr_mx5_sel;
 
wire [2:0] local_rdpr_mx4_sel;
 
wire [2:0] local_rdpr_mx4_sel;
 
wire [2:0] local_rdpr_mx3_sel;
 
wire [2:0] local_rdpr_mx3_sel;
 
wire [3:0] local_rdpr_mx2_sel;
 
wire [3:0] local_rdpr_mx2_sel;
Line 931... Line 538... 
wire thread0_stg_m, thread1_stg_m, thread2_stg_m, thread3_stg_m;
 
wire thread0_stg_m, thread1_stg_m, thread2_stg_m, thread3_stg_m;
 
wire thread0_stg_m_buf, thread1_stg_m_buf, thread2_stg_m_buf, thread3_stg_m_buf;
 
wire thread0_stg_m_buf, thread1_stg_m_buf, thread2_stg_m_buf, thread3_stg_m_buf;
 
wire thread0_rsel_g, thread1_rsel_g, thread2_rsel_g, thread3_rsel_g;
 
wire thread0_rsel_g, thread1_rsel_g, thread2_rsel_g, thread3_rsel_g;
 
wire thread0_rsel_e, thread1_rsel_e, thread2_rsel_e, thread3_rsel_e;
 
wire thread0_rsel_e, thread1_rsel_e, thread2_rsel_e, thread3_rsel_e;
 
wire inst_vld_w2, inst_vld_g, inst_vld_m, inst_vld_nf_g;
 
wire inst_vld_w2, inst_vld_g, inst_vld_m, inst_vld_nf_g;
 
wire [4-1:0] thread_inst_vld_g;
 
wire [`TLU_THRD_NUM-1:0] thread_inst_vld_g;
 
wire [4-1:0] thread_inst_vld_w2;
 
wire [`TLU_THRD_NUM-1:0] thread_inst_vld_w2;
 
// wire tlu_inst_vld_m; // qualified inst vld
 
// wire tlu_inst_vld_m; // qualified inst vld
 
wire exu_ttype_vld_g, ifu_ttype_vld_g, exu_ue_trap_g;
 
wire exu_ttype_vld_g, ifu_ttype_vld_g, exu_ue_trap_g;
 
wire [8:0]       exu_ttype_g, ifu_ttype_tmp_g, ifu_ttype_g;
 
wire [8:0]       exu_ttype_g, ifu_ttype_tmp_g, ifu_ttype_g;
 
wire [8:0]       exu_spill_ttype;
 
wire [8:0]       exu_spill_ttype;
 
// added for timing fix
 
// added for timing fix
Line 954... Line 561... 
// wire    lsu_ill_inst_g ;      // illegal instruction trap from lsu 
// wire    lsu_ill_inst_g ;      // illegal instruction trap from lsu 
// wire [`TLU_THRD_NUM-1:0] lsu_defr_thrd_g; 
// wire [`TLU_THRD_NUM-1:0] lsu_defr_thrd_g; 
wire    lsu_defr_trap_g, lsu_defr_trap_w2 ;     // deferred trap from lsu 
wire    lsu_defr_trap_g, lsu_defr_trap_w2 ;     // deferred trap from lsu 
wire    local_lsu_async_ttype_vld_w; // deferred trap from lsu 
wire    local_lsu_async_ttype_vld_w; // deferred trap from lsu 
// wire    local_lsu_defr_trp_taken_g; // deferred trap from lsu 
// wire    local_lsu_defr_trp_taken_g; // deferred trap from lsu 
wire [4-1:0] lsu_defr_trp_taken_w2;
 
wire [`TLU_THRD_NUM-1:0] lsu_defr_trp_taken_w2;
 
// wire    lsu_tlu_defr_trp_taken_w2 ;  // deferred trap from lsu - signled in g for w2
 
// wire    lsu_tlu_defr_trp_taken_w2 ;  // deferred trap from lsu - signled in g for w2
 
                                     // trap need to sync up with lsu_tlu_async_ttype_vld_g  
                                     // trap need to sync up with lsu_tlu_async_ttype_vld_g  
wire    htrap_ill_inst_m ;      // illegal instruction trap from htrap 
wire    htrap_ill_inst_m ;      // illegal instruction trap from htrap 
wire    htrap_ill_inst_uf_g ;   // illegal instruction trap from htrap - unflushed
 
wire    htrap_ill_inst_uf_g ;   // illegal instruction trap from htrap - unflushed
 
wire    htrap_ill_inst_g ;      // illegal instruction trap from htrap 
wire    htrap_ill_inst_g ;      // illegal instruction trap from htrap 
 
 
 
 
wire    [7-1:0] sraddr;
 
wire    [`TLU_ASR_ADDR_WIDTH-1:0] sraddr;
 
wire    [7-1:0] sraddr2;
 
wire    [`TLU_ASR_ADDR_WIDTH-1:0] sraddr2;
 
// modified due to timing
 
// modified due to timing
 
// wire         wsr_inst_d;
 
// wire         wsr_inst_d;
 
wire        asr_hyperp, asr_priv;
 
wire        asr_hyperp, asr_priv;
 
wire            tpc_rw_d, tnpc_rw_d, tstate_rw_d, ttype_rw_d;
 
wire            tpc_rw_d, tnpc_rw_d, tstate_rw_d, ttype_rw_d;
 
wire            tick_rw_d, tickcmp_rw_d, tick_npriv_r_d;
 
wire            tick_rw_d, tickcmp_rw_d, tick_npriv_r_d;
Line 991... Line 598... 
wire immu_miss_g;
 
wire immu_miss_g;
 
wire trap_taken_g, trap_taken_w2;
 
wire trap_taken_g, trap_taken_w2;
 
wire [1:0] trap_tid_g;
 
wire [1:0] trap_tid_g;
 
// wire [1:0] tsa_wr_tid_g;
 
// wire [1:0] tsa_wr_tid_g;
 
wire [1:0] pend_trap_tid_g, pend_trap_tid_w2;
 
wire [1:0] pend_trap_tid_g, pend_trap_tid_w2;
 
wire [9-1:0] final_ttype_w2;
 
wire [`TSA_TTYPE_WIDTH-1:0] final_ttype_w2;
 
wire [9-1:0] tba_ttype_w1;
 
wire [`TSA_TTYPE_WIDTH-1:0] tba_ttype_w1;
 
wire [9-1:0] final_offset_w1;
 
wire [`TSA_TTYPE_WIDTH-1:0] final_offset_w1;
 
wire tsa_rd_vld;
 
wire tsa_rd_vld;
 
// modified for bug 3017
 
// modified for bug 3017
 
// logic moved to tlu_misctl
 
// logic moved to tlu_misctl
 
// wire [48:0] normal_trap_pc_w1, normal_trap_npc_w1; 
// wire [48:0] normal_trap_pc_w1, normal_trap_npc_w1; 
// wire [48:0] trap_pc_w1, trap_npc_w1; 
// wire [48:0] trap_pc_w1, trap_npc_w1; 
// wire [48:0] trap_pc_w2, trap_npc_w2; 
// wire [48:0] trap_pc_w2, trap_npc_w2; 
// wire tsa_rd_vld_e, tsa_rd_vld_m;
 
// wire tsa_rd_vld_e, tsa_rd_vld_m;
 
wire [4-1:0] sscan_tid_sel;
 
wire [`TLU_THRD_NUM-1:0] sscan_tid_sel;
 
// logic moved to tlu_misctl
 
// logic moved to tlu_misctl
 
/*
 
/*
 
wire [`TLU_THRD_NUM-1:0] sscan_ttype_en;
 
wire [`TLU_THRD_NUM-1:0] sscan_ttype_en;
 
wire [`TLU_THRD_NUM-1:0] sscan_tt_rd_sel;
 
wire [`TLU_THRD_NUM-1:0] sscan_tt_rd_sel;
 
wire [`TLU_THRD_NUM-1:0] sscan_tt_wr_sel;
 
wire [`TLU_THRD_NUM-1:0] sscan_tt_wr_sel;
Line 1017... Line 624... 
wire [`TSA_TTYPE_WIDTH-1:0] sscan_tt1_din;
 
wire [`TSA_TTYPE_WIDTH-1:0] sscan_tt1_din;
 
wire [`TSA_TTYPE_WIDTH-1:0] sscan_tt2_din;
 
wire [`TSA_TTYPE_WIDTH-1:0] sscan_tt2_din;
 
wire [`TSA_TTYPE_WIDTH-1:0] sscan_tt3_din;
 
wire [`TSA_TTYPE_WIDTH-1:0] sscan_tt3_din;
 
wire [`TSA_TTYPE_WIDTH-1:0] tsa_rdata_ttype_m;
 
wire [`TSA_TTYPE_WIDTH-1:0] tsa_rdata_ttype_m;
 
*/
 
*/
 
wire [3-1:0] tcl_sscan_test_data;
 
wire [`TCL_SSCAN_WIDTH-1:0] tcl_sscan_test_data;
 
wire tba_ttype_sel_w2;
 
wire tba_ttype_sel_w2;
 
wire [3:0] final_ttype_sel_g, final_ttype_sel_w2;
 
wire [3:0] final_ttype_sel_g, final_ttype_sel_w2;
 
// modified due to one-hot mux bug
 
// modified due to one-hot mux bug
 
wire [1:0] final_offset_en_g, final_offset_en_w1;
 
wire [1:0] final_offset_en_g, final_offset_en_w1;
 
wire [2:0] final_offset_sel_w1;
 
wire [2:0] final_offset_sel_w1;
Line 1034... Line 641... 
// added for timing fix
 
// added for timing fix
 
wire            sync_trap_taken_m ;
 
wire            sync_trap_taken_m ;
 
wire            ifu_ttype_early_vld_m ;
 
wire            ifu_ttype_early_vld_m ;
 
// wire  [3:0]   tickcmp_int;       // interrupt caused by tick_ticktmp 
// wire  [3:0]   tickcmp_int;       // interrupt caused by tick_ticktmp 
wire       fp_trap_thrd0,fp_trap_thrd1,fp_trap_thrd2,fp_trap_thrd3;
 
wire       fp_trap_thrd0,fp_trap_thrd1,fp_trap_thrd2,fp_trap_thrd3;
 
wire [9-1:0] ffu_async_ttype;
 
wire [`TSA_TTYPE_WIDTH-1:0] ffu_async_ttype;
 
wire       spill_thrd0,spill_thrd1,spill_thrd2,spill_thrd3;
 
wire       spill_thrd0,spill_thrd1,spill_thrd2,spill_thrd3;
 
wire [4-1:0] trap_cwp_enb;
 
wire [`TLU_THRD_NUM-1:0] trap_cwp_enb;
 
wire [4-1:0] lsu_async_vld_en_g, lsu_async_vld_en_w2;
 
wire [`TLU_THRD_NUM-1:0] lsu_async_vld_en_g, lsu_async_vld_en_w2;
 
wire       dmmu_async_thrd0, dmmu_async_thrd1;
 
wire       dmmu_async_thrd0, dmmu_async_thrd1;
 
wire       dmmu_async_thrd2, dmmu_async_thrd3;
 
wire       dmmu_async_thrd2, dmmu_async_thrd3;
 
wire [9-1:0] dmmu_async_ttype;
 
wire [`TSA_TTYPE_WIDTH-1:0] dmmu_async_ttype;
 
wire       pend_to_thrd0_en, pend_to_thrd1_en;
 
wire       pend_to_thrd0_en, pend_to_thrd1_en;
 
wire       pend_to_thrd2_en, pend_to_thrd3_en;
 
wire       pend_to_thrd2_en, pend_to_thrd3_en;
 
wire       pend_to_thrd0_reset, pend_to_thrd1_reset;
 
wire       pend_to_thrd0_reset, pend_to_thrd1_reset;
 
wire       pend_to_thrd2_reset, pend_to_thrd3_reset;
 
wire       pend_to_thrd2_reset, pend_to_thrd3_reset;
 
wire tlu_pich_cnt_hld;
 
wire tlu_pich_cnt_hld;
 
wire [4-1:0] pich_cnt_hld_rst_g;
 
wire [`TLU_THRD_NUM-1:0] pich_cnt_hld_rst_g;
 
wire [4-1:0] pich_cnt_hld_rst_w2;
 
wire [`TLU_THRD_NUM-1:0] pich_cnt_hld_rst_w2;
 
wire [4-1:0] pend_pich_cnt_hld;
 
wire [`TLU_THRD_NUM-1:0] pend_pich_cnt_hld;
 
wire [4-1:0] pend_pich_cnt_hld_q;
 
wire [`TLU_THRD_NUM-1:0] pend_pich_cnt_hld_q;
 
wire [4-1:0] pend_pich_cnt_hld_noqual;
 
wire [`TLU_THRD_NUM-1:0] pend_pich_cnt_hld_noqual;
 
wire [4-1:0] pend_pich_cnt_hld_early;
 
wire [`TLU_THRD_NUM-1:0] pend_pich_cnt_hld_early;
 
wire [4-1:0] pend_pich_cnt_adj;
 
wire [`TLU_THRD_NUM-1:0] pend_pich_cnt_adj;
 
wire [4-1:0] cwp_en_thrd_reset;
 
wire [`TLU_THRD_NUM-1:0] cwp_en_thrd_reset;
 
// wire    pend_to_thrd0_taken, pend_to_thrd1_taken;
 
// wire    pend_to_thrd0_taken, pend_to_thrd1_taken;
 
// wire    pend_to_thrd2_taken, pend_to_thrd3_taken;
 
// wire    pend_to_thrd2_taken, pend_to_thrd3_taken;
 
wire [9-1:0] pend_ttype0,pend_ttype1,pend_ttype2,pend_ttype3;
 
wire [`TSA_TTYPE_WIDTH-1:0] pend_ttype0,pend_ttype1,pend_ttype2,pend_ttype3;
 
wire       pending_trap0,pending_trap1,pending_trap2,pending_trap3;
 
wire       pending_trap0,pending_trap1,pending_trap2,pending_trap3;
 
wire [9-1:0] pending_ttype0,pending_ttype1,pending_ttype2,pending_ttype3;
 
wire [`TSA_TTYPE_WIDTH-1:0] pending_ttype0,pending_ttype1,pending_ttype2,pending_ttype3;
 
wire [9-1:0] pending_ttype, pending_ttype_w2;
 
wire [`TSA_TTYPE_WIDTH-1:0] pending_ttype, pending_ttype_w2;
 
//
 
//
 
// Added for bug 1575
 
// Added for bug 1575
 
wire agp_tid_sel;
 
wire agp_tid_sel;
 
// modified due to timing
 
// modified due to timing
 
// wire update_pstate0_g,update_pstate1_g;
 
// wire update_pstate0_g,update_pstate1_g;
 
// wire update_pstate2_g,update_pstate3_g;
 
// wire update_pstate2_g,update_pstate3_g;
 
// wire [`TLU_THRD_NUM-1:0] update_pstate_g;,
 
// wire [`TLU_THRD_NUM-1:0] update_pstate_g;,
 
wire [4-1:0] update_pstate_w2;
 
wire [`TLU_THRD_NUM-1:0] update_pstate_w2;
 
wire thrd0_traps_w2, thrd1_traps_w2;
 
wire thrd0_traps_w2, thrd1_traps_w2;
 
wire thrd2_traps_w2, thrd3_traps_w2;
 
wire thrd2_traps_w2, thrd3_traps_w2;
 
wire ifu_ttype_vld_tmp_g;
 
wire ifu_ttype_vld_tmp_g;
 
//
 
//
 
// added for timing, move qualification from ifu to tlu
 
// added for timing, move qualification from ifu to tlu
Line 1099... Line 706... 
// wire [3:0] rst_hwdr_ttype_sel;
 
// wire [3:0] rst_hwdr_ttype_sel;
 
wire rst_hwdr_ttype_sel_w2;
 
wire rst_hwdr_ttype_sel_w2;
 
wire       onehot_pending_ttype_sel;
 
wire       onehot_pending_ttype_sel;
 
wire       early_priv_traps_g, exu_hyper_traps_g;
 
wire       early_priv_traps_g, exu_hyper_traps_g;
 
wire       exu_pib_priv_act_trap_m;
 
wire       exu_pib_priv_act_trap_m;
 
wire [4-1:0] pib_wrap_m;
 
wire [`TLU_THRD_NUM-1:0] pib_wrap_m;
 
wire [4-1:0] pib_pich_wrap_m;
 
wire [`TLU_THRD_NUM-1:0] pib_pich_wrap_m;
 
wire pib_wrap_trap_nq_g, pib_wrap_trap_g, pib_wrap_trap_m;
 
wire pib_wrap_trap_nq_g, pib_wrap_trap_g, pib_wrap_trap_m;
 
wire [4-1:0] pib_trap_en;
 
wire [`TLU_THRD_NUM-1:0] pib_trap_en;
 
wire [4-1:0] picl_wrap_pend;
 
wire [`TLU_THRD_NUM-1:0] picl_wrap_pend;
 
//
 
//
 
// added for timing; moved qualification from IFU to TLU
 
// added for timing; moved qualification from IFU to TLU
 
wire       ifu_rstint_m,ifu_hwint_m,ifu_swint_m; // swint_nq_g;
 
wire       ifu_rstint_m,ifu_hwint_m,ifu_swint_m; // swint_nq_g;
 
wire       sftint_penc_update;
 
wire       sftint_penc_update;
 
wire       sftint_user_update_g, sftint_user_update_w2;
 
wire       sftint_user_update_g, sftint_user_update_w2;
Line 1118... Line 725... 
wire    rstint_taken,hwint_taken,swint_taken;
 
wire    rstint_taken,hwint_taken,swint_taken;
 
// wire swint_thrd0_taken, swint_thrd1_taken;
 
// wire swint_thrd0_taken, swint_thrd1_taken;
 
// wire swint_thrd2_taken, swint_thrd3_taken;
 
// wire swint_thrd2_taken, swint_thrd3_taken;
 
wire    sirint_taken;
 
wire    sirint_taken;
 
// wire [`TLU_THRD_NUM-2:0] swint_thrd_g;
 
// wire [`TLU_THRD_NUM-2:0] swint_thrd_g;
 
wire [4-2:0] sftint_penc_thrd;
 
wire [`TLU_THRD_NUM-2:0] sftint_penc_thrd;
 
wire    por_rstint_g, xir_rstint_g;
 
wire    por_rstint_g, xir_rstint_g;
 
wire    por_rstint0_g, por_rstint1_g;
 
wire    por_rstint0_g, por_rstint1_g;
 
wire    por_rstint2_g, por_rstint3_g;
 
wire    por_rstint2_g, por_rstint3_g;
 
wire    por_rstint_w2;
 
wire    por_rstint_w2;
 
wire    por_rstint0_w2, por_rstint1_w2;
 
wire    por_rstint0_w2, por_rstint1_w2;
 
wire    por_rstint2_w2, por_rstint3_w2;
 
wire    por_rstint2_w2, por_rstint3_w2;
 
wire    trp_lvl0_at_maxtl,trp_lvl1_at_maxtl;
 
wire    trp_lvl0_at_maxtl,trp_lvl1_at_maxtl;
 
wire    trp_lvl2_at_maxtl,trp_lvl3_at_maxtl;
 
wire    trp_lvl2_at_maxtl,trp_lvl3_at_maxtl;
 
wire    internal_wdr;
 
wire    internal_wdr;
 
wire [4-1:0] internal_wdr_trap;
 
wire [`TLU_THRD_NUM-1:0] internal_wdr_trap;
 
// added for hypervispor support
 
// added for hypervispor support
 
wire [4-1:0] pil_cmp_en;
 
wire [`TLU_THRD_NUM-1:0] pil_cmp_en;
 
wire [4-1:0] sftint_only_vld;
 
wire [`TLU_THRD_NUM-1:0] sftint_only_vld;
 
wire [4-1:0] tlu_int_sftint_pend;
 
wire [`TLU_THRD_NUM-1:0] tlu_int_sftint_pend;
 
wire [4-1:0] sftint_pend_wait;
 
wire [`TLU_THRD_NUM-1:0] sftint_pend_wait;
 
wire [4-1:0] sftint_wait_rst;
 
wire [`TLU_THRD_NUM-1:0] sftint_wait_rst;
 
//
 
//
 
wire [3:0] true_pil0, true_pil1;
 
wire [3:0] true_pil0, true_pil1;
 
wire [3:0] true_pil2, true_pil3;
 
wire [3:0] true_pil2, true_pil3;
 
wire pil0_en,pil1_en,pil2_en,pil3_en;
 
wire pil0_en,pil1_en,pil2_en,pil3_en;
 
wire set_sftint_d, clr_sftint_d, sftint_rg_rw_d;
 
wire set_sftint_d, clr_sftint_d, sftint_rg_rw_d;
Line 1181... Line 788... 
// wire [6:0]   dsfsr_ftype_g, dsfsr_pe_ftype_g;
 
// wire [6:0]   dsfsr_ftype_g, dsfsr_pe_ftype_g;
 
wire dsfsr_side_effect_g;
 
wire dsfsr_side_effect_g;
 
wire dsfsr_trp_wr_g;
 
wire dsfsr_trp_wr_g;
 
*/
 
*/
 
wire [1:0] isfsr_ctxt_g;
 
wire [1:0] isfsr_ctxt_g;
 
wire [4-1:0] tick_en;
 
wire [`TLU_THRD_NUM-1:0] tick_en;
 
wire local_sync_trap_m, local_sync_trap_g;
 
wire local_sync_trap_m, local_sync_trap_g;
 
wire dside_sync_trap_g, early_dside_trap_g;
 
wire dside_sync_trap_g, early_dside_trap_g;
 
wire true_hscpd_dacc_excpt_m;
 
wire true_hscpd_dacc_excpt_m;
 
wire true_qtail_dacc_excpt_m;
 
wire true_qtail_dacc_excpt_m;
 
// wire lsu_higher_priority;
 
// wire lsu_higher_priority;
 
// wire dside_higher_priority;
 
// wire dside_higher_priority;
 
wire [9-1:0] local_sync_ttype_g;
 
wire [`TSA_TTYPE_WIDTH-1:0] local_sync_ttype_g;
 
wire local_higher_ttype_flg;
 
wire local_higher_ttype_flg;
 
// wire [`TSA_TTYPE_WIDTH-1:0]  dside_sync_ttype_pre_g;
 
// wire [`TSA_TTYPE_WIDTH-1:0]  dside_sync_ttype_pre_g;
 
// wire [`TSA_TTYPE_WIDTH-1:0]  dside_sync_ttype_g;
 
// wire [`TSA_TTYPE_WIDTH-1:0]  dside_sync_ttype_g;
 
wire [9-1:0]     early_sync_ttype_g, early_sync_ttype_w2;
 
wire [`TSA_TTYPE_WIDTH-1:0]      early_sync_ttype_g, early_sync_ttype_w2;
 
wire [9-1:0]     adj_lsu_ttype_w2;
 
wire [`TSA_TTYPE_WIDTH-1:0]      adj_lsu_ttype_w2;
 
wire [9-1:0]     lsu_tlu_ttype_w2;
 
wire [`TSA_TTYPE_WIDTH-1:0]      lsu_tlu_ttype_w2;
 
// wire [`TSA_TTYPE_WIDTH-3:0]  lsu_tlu_async_ttype_w2;
 
// wire [`TSA_TTYPE_WIDTH-3:0]  lsu_tlu_async_ttype_w2;
 
// wire [`TSA_TTYPE_WIDTH-3:0]  rst_ttype_g; 
// wire [`TSA_TTYPE_WIDTH-3:0]  rst_ttype_g; 
wire [9-3:0]     rst_hwint_ttype_g, rst_hwint_ttype_w2;
 
wire [`TSA_TTYPE_WIDTH-3:0]      rst_hwint_ttype_g, rst_hwint_ttype_w2;
 
wire [9-3:0]     rst_ttype_w2, rst_hwdr_ttype_w2;
 
wire [`TSA_TTYPE_WIDTH-3:0]      rst_ttype_w2, rst_hwdr_ttype_w2;
 
wire [9-1:0]     early_ttype_g;
 
wire [`TSA_TTYPE_WIDTH-1:0]      early_ttype_g;
 
wire trp_lvl0_at_maxtlless1,trp_lvl1_at_maxtlless1;
 
wire trp_lvl0_at_maxtlless1,trp_lvl1_at_maxtlless1;
 
wire trp_lvl2_at_maxtlless1,trp_lvl3_at_maxtlless1;
 
wire trp_lvl2_at_maxtlless1,trp_lvl3_at_maxtlless1;
 
wire trp_lvl_at_maxtlless1;
 
wire trp_lvl_at_maxtlless1;
 
wire [4-1:0] tpl_maxless1;
 
wire [`TLU_THRD_NUM-1:0] tpl_maxless1;
 
wire redmode_insertion, redmode_insertion_w2;
 
wire redmode_insertion, redmode_insertion_w2;
 
wire [4-1:0] tlu_lsu_redmode_rst;
 
wire [`TLU_THRD_NUM-1:0] tlu_lsu_redmode_rst;
 
wire trap_to_redmode;
 
wire trap_to_redmode;
 
wire pending_thrd_event_taken;
 
wire pending_thrd_event_taken;
 
// added or modified for timing
 
// added or modified for timing
 
wire [4-2:0]  thrd_rsel_g;
 
wire [`TLU_THRD_NUM-2:0]  thrd_rsel_g;
 
wire [4-2:0]  thrd_rsel_w2;
 
wire [`TLU_THRD_NUM-2:0]  thrd_rsel_w2;
 
wire va_oor_inst_acc_excp_g; // qualified va_oor_jl_ret trap 
wire va_oor_inst_acc_excp_g; // qualified va_oor_jl_ret trap 
wire va_oor_data_acc_excp_g, va_oor_data_acc_excp_w2; // qualified exu_tlu_va_oor_m trap 
wire va_oor_data_acc_excp_g, va_oor_data_acc_excp_w2; // qualified exu_tlu_va_oor_m trap 
wire sir_inst_g;
 
wire sir_inst_g;
 
wire [4-1:0]     pending_trap_sel;
 
wire [`TLU_THRD_NUM-1:0] pending_trap_sel;
 
//
 
//
 
// modified to support lsu_deferred traps; modified for timing
 
// modified to support lsu_deferred traps; modified for timing
 
wire reset_sel_g, reset_sel_w2;
 
wire reset_sel_g, reset_sel_w2;
 
wire [2:0] reset_id_g;
 
wire [2:0] reset_id_g;
 
wire tick_npt0,tick_npt1,tick_npt2,tick_npt3;
 
wire tick_npt0,tick_npt1,tick_npt2,tick_npt3;
Line 1250... Line 857... 
wire [1:0] early_trap_tid_g;
 
wire [1:0] early_trap_tid_g;
 
wire [1:0] true_trap_tid_w2;
 
wire [1:0] true_trap_tid_w2;
 
wire trp_lvl_zero;
 
wire trp_lvl_zero;
 
wire misalign_addr_jmpl_rtn_g,misalign_addr_ldst_atm_g;
 
wire misalign_addr_jmpl_rtn_g,misalign_addr_ldst_atm_g;
 
wire tt_init_en;
 
wire tt_init_en;
 
wire [4-1:0] tt_init_rst;
 
wire [`TLU_THRD_NUM-1:0] tt_init_rst;
 
wire [4-1:0] tt_unwritten;
 
wire [`TLU_THRD_NUM-1:0] tt_unwritten;
 
wire ttype_written;
 
wire ttype_written;
 
wire ttype_unwritten_sel;
 
wire ttype_unwritten_sel;
 
wire reset_d1;
 
wire reset_d1;
 
wire thread_tl_zero;
 
wire thread_tl_zero;
 
// wire iside_trap;
 
// wire iside_trap;
Line 1265... Line 872... 
// wire hyper_wdr_trap;
 
// wire hyper_wdr_trap;
 
wire hyper_wdr_early_trap_g, hyper_wdr_early_trap_w2, hyper_wdr_trap_w2;
 
wire hyper_wdr_early_trap_g, hyper_wdr_early_trap_w2, hyper_wdr_trap_w2;
 
wire tlu_priv_traps_w2;
 
wire tlu_priv_traps_w2;
 
wire [2:0] tlu_early_priv_element_g;
 
wire [2:0] tlu_early_priv_element_g;
 
wire [2:0] tlu_early_priv_element_w2;
 
wire [2:0] tlu_early_priv_element_w2;
 
wire [4-1:0] trp_lvl_gte_maxstl;
 
wire [`TLU_THRD_NUM-1:0] trp_lvl_gte_maxstl;
 
wire [4-1:0] trp_lvl_at_maxstl;
 
wire [`TLU_THRD_NUM-1:0] trp_lvl_at_maxstl;
 
 
 
 
 
// This section was modified to abide to the Niagara synthesis methodology
 
// This section was modified to abide to the Niagara synthesis methodology
 
//
 
//
 
//reg   tpc_rw_e, tpc_rw_m, tpc_rw_g;
 
//reg   tpc_rw_e, tpc_rw_m, tpc_rw_g;
 
//reg   tnpc_rw_e, tnpc_rw_m, tnpc_rw_g;
 
//reg   tnpc_rw_e, tnpc_rw_m, tnpc_rw_g;
Line 1329... Line 936... 
    .din  (grst_l),
 
    .din  (grst_l),
 
    .clk  (clk),
 
    .clk  (clk),
 
    .rst_l(arst_l),
 
    .rst_l(arst_l),
 
    .q    (local_rst_l),
 
    .q    (local_rst_l),
 
    .se   (se),
 
    .se   (se),
 
    .si   (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so   ()
 
    .so   ()
 
);
 
);
 
 
 
 
 
assign tlu_rst = ~tlu_rst_l;
 
assign tlu_rst = ~tlu_rst_l;
 
assign local_rst = ~tlu_rst_l;
 
assign local_rst = ~tlu_rst_l;
Line 1429... Line 1036... 
assign  tlu_htickcmp_en_l[1] =  ~((htickcmp_rw_g & wsr_inst_g & thread1_wsel_g));
 
assign  tlu_htickcmp_en_l[1] =  ~((htickcmp_rw_g & wsr_inst_g & thread1_wsel_g));
 
assign  tlu_htickcmp_en_l[2] =  ~((htickcmp_rw_g & wsr_inst_g & thread2_wsel_g));
 
assign  tlu_htickcmp_en_l[2] =  ~((htickcmp_rw_g & wsr_inst_g & thread2_wsel_g));
 
assign  tlu_htickcmp_en_l[3] =  ~((htickcmp_rw_g & wsr_inst_g & thread3_wsel_g));
 
assign  tlu_htickcmp_en_l[3] =  ~((htickcmp_rw_g & wsr_inst_g & thread3_wsel_g));
 
 
 
 
 
// modified for bug 1266 and 1264
 
// modified for bug 1266 and 1264
 
dff dff_stgg_va_oor_jl_ret_g (
 
dff_s dff_stgg_va_oor_jl_ret_g (
 
    .din (exu_tlu_va_oor_jl_ret_m),
 
    .din (exu_tlu_va_oor_jl_ret_m),
 
        .q   (va_oor_jl_ret_g),
 
        .q   (va_oor_jl_ret_g),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
// This may have to be changed as all lsu traps may not use mmu globals 
// This may have to be changed as all lsu traps may not use mmu globals 
// ffu traps may have to be factored in once round-robin selection in place.
 
// ffu traps may have to be factored in once round-robin selection in place.
Line 1457... Line 1064... 
assign va_oor_data_acc_excp_g =
 
assign va_oor_data_acc_excp_g =
 
       (dmmu_va_oor_g & inst_vld_g) & ~(exu_ttype_vld_g | ifu_ttype_vld_g |
 
       (dmmu_va_oor_g & inst_vld_g) & ~(exu_ttype_vld_g | ifu_ttype_vld_g |
 
        lsu_tlu_priv_action_g | misalign_addr_ldst_atm_g | lsu_tlu_wtchpt_trp_g);
 
        lsu_tlu_priv_action_g | misalign_addr_ldst_atm_g | lsu_tlu_wtchpt_trp_g);
 
//
 
//
 
// added for timing 
// added for timing 
dffr dffr_va_oor_data_acc_excp_w2 (
 
dffr_s dffr_va_oor_data_acc_excp_w2 (
 
    .din (va_oor_data_acc_excp_g),
 
    .din (va_oor_data_acc_excp_g),
 
    .q   (va_oor_data_acc_excp_w2),
 
    .q   (va_oor_data_acc_excp_w2),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
//
 
//
 
// exu should qualify with priv bit. Assume ttype vld is asserted.
 
// exu should qualify with priv bit. Assume ttype vld is asserted.
 
dff #(1) dff_stgg_sir_g (
 
dff_s #(1) dff_stgg_sir_g (
 
    .din (ifu_tlu_sir_inst_m),
 
    .din (ifu_tlu_sir_inst_m),
 
        .q   (sir_inst_g),
 
        .q   (sir_inst_g),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
assign  pstate_rmode[3:0] = tlu_int_redmode[3:0];
 
assign  pstate_rmode[3:0] = tlu_int_redmode[3:0];
 
 
 
 
Line 1515... Line 1122... 
              tpl_maxless1[2] | internal_wdr_trap[2] | local_rst ;
 
              tpl_maxless1[2] | internal_wdr_trap[2] | local_rst ;
 
assign  tlu_lsu_redmode_rst[3]  =
 
assign  tlu_lsu_redmode_rst[3]  =
 
                ((rstint_taken |  sirint_taken) & thread3_rsel_g) |
 
                ((rstint_taken |  sirint_taken) & thread3_rsel_g) |
 
              tpl_maxless1[3] | internal_wdr_trap[3] | local_rst ;
 
              tpl_maxless1[3] | internal_wdr_trap[3] | local_rst ;
 
 
 
 
 
dff #(4) dff_tlu_lsu_redmode_rst_d1 (
 
dff_s #(`TLU_THRD_NUM) dff_tlu_lsu_redmode_rst_d1 (
 
    .din (tlu_lsu_redmode_rst[4-1:0]),
 
    .din (tlu_lsu_redmode_rst[`TLU_THRD_NUM-1:0]),
 
        .q   (tlu_lsu_redmode_rst_d1[4-1:0]),
 
        .q   (tlu_lsu_redmode_rst_d1[`TLU_THRD_NUM-1:0]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
assign  redmode_insertion =
 
assign  redmode_insertion =
 
        local_rst | rstint_taken | trap_to_redmode | internal_wdr | sirint_taken;
 
        local_rst | rstint_taken | trap_to_redmode | internal_wdr | sirint_taken;
 
//      sir_inst_g;                                     // sigm inst in priv mode
 
//      sir_inst_g;                                     // sigm inst in priv mode
 
//
 
//
 
// added for timing
 
// added for timing
 
dff dff_redmode_insertion_w2 (
 
dff_s dff_redmode_insertion_w2 (
 
    .din (redmode_insertion),
 
    .din (redmode_insertion),
 
        .q   (redmode_insertion_w2),
 
        .q   (redmode_insertion_w2),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
assign  tlu_select_redmode =  redmode_insertion_w2;
 
assign  tlu_select_redmode =  redmode_insertion_w2;
 
 
 
 
 
// added for bug 2808
 
// added for bug 2808
 
assign ibrkpt_trap_m =
 
assign ibrkpt_trap_m =
 
           (ifu_tlu_ttype_m[8:0]== 9'h076) & ifu_tlu_ttype_vld_m;
 
           (ifu_tlu_ttype_m[8:0]== 9'h076) & ifu_tlu_ttype_vld_m;
 
 
 
 
 
dffr dffr_ibrkpt_trap_g (
 
dffr_s dffr_ibrkpt_trap_g (
 
   .din (ibrkpt_trap_m),
 
   .din (ibrkpt_trap_m),
 
   .q   (ibrkpt_trap_g),
 
   .q   (ibrkpt_trap_g),
 
   .rst (local_rst),
 
   .rst (local_rst),
 
   .clk (clk),
 
   .clk (clk),
 
   .se  (se),
 
   .se  (se),
 
   .si  (),
 
   `SIMPLY_RISC_SCANIN,
 
   .so  ()
 
   .so  ()
 
);
 
);
 
 
 
 
 
dffr dffr_ibrkpt_trap_w2 (
 
dffr_s dffr_ibrkpt_trap_w2 (
 
   .din (ibrkpt_trap_g),
 
   .din (ibrkpt_trap_g),
 
   .q   (ibrkpt_trap_w2),
 
   .q   (ibrkpt_trap_w2),
 
   .rst (local_rst),
 
   .rst (local_rst),
 
   .clk (clk),
 
   .clk (clk),
 
   .se  (se),
 
   .se  (se),
 
   .si  (),
 
   `SIMPLY_RISC_SCANIN,
 
   .so  ()
 
   .so  ()
 
);
 
);
 
 
 
 
 
// assign tlu_ibrkpt_trap_g = ibrkpt_trap_g;
 
// assign tlu_ibrkpt_trap_g = ibrkpt_trap_g;
 
assign tlu_ibrkpt_trap_w2 = ibrkpt_trap_w2;
 
assign tlu_ibrkpt_trap_w2 = ibrkpt_trap_w2;
Line 1591... Line 1198... 
assign  tlu_pstate_din_sel3[1]  = (pstate_rw_w2 & wsr_inst_w2) & ~rst_tri_en &
 
assign  tlu_pstate_din_sel3[1]  = (pstate_rw_w2 & wsr_inst_w2) & ~rst_tri_en &
 
                                 ~tlu_pstate_din_sel3[0] & thread3_wsel_w2;
 
                                 ~tlu_pstate_din_sel3[0] & thread3_wsel_w2;
 
 
 
 
 
assign  restore_pc_sel_g = (dnrtry_inst_g & cwp_fastcmplt_g) | cwp_cmplt_g;
 
assign  restore_pc_sel_g = (dnrtry_inst_g & cwp_fastcmplt_g) | cwp_cmplt_g;
 
//
 
//
 
dffr dffr_restore_pc_sel_w1 (
 
dffr_s dffr_restore_pc_sel_w1 (
 
   .din (restore_pc_sel_g),
 
   .din (restore_pc_sel_g),
 
   .q   (restore_pc_sel_w1),
 
   .q   (restore_pc_sel_w1),
 
   .rst (local_rst),
 
   .rst (local_rst),
 
   .clk (clk),
 
   .clk (clk),
 
   .se  (se),
 
   .se  (se),
 
   .si  (),
 
   `SIMPLY_RISC_SCANIN,
 
   .so  ()
 
   .so  ()
 
);
 
);
 
 
 
 
 
assign  tlu_restore_pc_sel_w1 = restore_pc_sel_w1;
 
assign  tlu_restore_pc_sel_w1 = restore_pc_sel_w1;
 
//
 
//
Line 1626... Line 1233... 
assign  tlu_update_pc_l_w[1] =  ~(inst_vld_g & thread1_rsel_g);
 
assign  tlu_update_pc_l_w[1] =  ~(inst_vld_g & thread1_rsel_g);
 
assign  tlu_update_pc_l_w[2] =  ~(inst_vld_g & thread2_rsel_g);
 
assign  tlu_update_pc_l_w[2] =  ~(inst_vld_g & thread2_rsel_g);
 
assign  tlu_update_pc_l_w[3] =  ~(inst_vld_g & thread3_rsel_g);
 
assign  tlu_update_pc_l_w[3] =  ~(inst_vld_g & thread3_rsel_g);
 
//
 
//
 
// modified for timing 
// modified for timing 
assign tlu_thrd_wsel_w2[4-1:0] =
 
assign tlu_thrd_wsel_w2[`TLU_THRD_NUM-1:0] =
 
           {thread3_wtrp_w2, thread2_wtrp_w2, thread1_wtrp_w2, thread0_wtrp_w2};
 
           {thread3_wtrp_w2, thread2_wtrp_w2, thread1_wtrp_w2, thread0_wtrp_w2};
 
 
 
 
 
//wire  pending_thrd_event_taken_w2;
 
//wire  pending_thrd_event_taken_w2;
 
assign  pending_thrd_event_taken =
 
assign  pending_thrd_event_taken =
 
        pending_thrd0_event_taken | pending_thrd1_event_taken |
 
        pending_thrd0_event_taken | pending_thrd1_event_taken |
Line 1644... Line 1251... 
 
 
 
 
assign  thrd_rsel_g[0] =         (thread0_rsel_g & ~pending_thrd_event_taken) | pending_thrd0_event_taken;
 
assign  thrd_rsel_g[0] =         (thread0_rsel_g & ~pending_thrd_event_taken) | pending_thrd0_event_taken;
 
assign  thrd_rsel_g[1] =        (thread1_rsel_g & ~pending_thrd_event_taken) | pending_thrd1_event_taken;
 
assign  thrd_rsel_g[1] =        (thread1_rsel_g & ~pending_thrd_event_taken) | pending_thrd1_event_taken;
 
assign  thrd_rsel_g[2] =        (thread2_rsel_g & ~pending_thrd_event_taken) | pending_thrd2_event_taken;
 
assign  thrd_rsel_g[2] =        (thread2_rsel_g & ~pending_thrd_event_taken) | pending_thrd2_event_taken;
 
 
 
 
 
dff #(4-1) dff_thrd_rsel_w2 (
 
dff_s #(`TLU_THRD_NUM-1) dff_thrd_rsel_w2 (
 
    .din (thrd_rsel_g[4-2:0]),
 
    .din (thrd_rsel_g[`TLU_THRD_NUM-2:0]),
 
    .q   (thrd_rsel_w2[4-2:0]),
 
    .q   (thrd_rsel_w2[`TLU_THRD_NUM-2:0]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
//
 
//
 
// modified for the tsa_wdata bug (tlu_tdp)
 
// modified for the tsa_wdata bug (tlu_tdp)
 
//
 
//
Line 1773... Line 1380... 
// constructing the mux select for rdpr 7 in tdp
 
// constructing the mux select for rdpr 7 in tdp
 
//
 
//
 
 
 
 
 
//=========================================================================================
 
//=========================================================================================
 
 
 
 
 
dff #(2) dff_stgdntry_m (
 
dff_s #(2) dff_stgdntry_m (
 
    .din ({done_inst_e,retry_inst_e}),
 
    .din ({done_inst_e,retry_inst_e}),
 
        .q   ({done_inst_m_tmp,retry_inst_m_tmp}),
 
        .q   ({done_inst_m_tmp,retry_inst_m_tmp}),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
wire    trap_on_dnrtry_m;
 
wire    trap_on_dnrtry_m;
 
// priv opcode, illegal inst trap on done/retry.
 
// priv opcode, illegal inst trap on done/retry.
Line 1829... Line 1436... 
assign cwp_no_change_m = ~|(cwp_xor_m[2:0]);
 
assign cwp_no_change_m = ~|(cwp_xor_m[2:0]);
 
*/
 
*/
 
assign cwp_fastcmplt_m =
 
assign cwp_fastcmplt_m =
 
           tlu_exu_cwpccr_update_m & tlu_cwp_no_change_m;
 
           tlu_exu_cwpccr_update_m & tlu_cwp_no_change_m;
 
 
 
 
 
dffr dffr_cwp_fastcmplt_uq_g (
 
dffr_s dffr_cwp_fastcmplt_uq_g (
 
    .din (cwp_fastcmplt_m),
 
    .din (cwp_fastcmplt_m),
 
        .q   (cwp_fastcmplt_uq_g),
 
        .q   (cwp_fastcmplt_uq_g),
 
    .clk (clk),
 
    .clk (clk),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
// assign       tlu_exu_cwpccr_update_m = done_inst_m | retry_inst_m;
 
// assign       tlu_exu_cwpccr_update_m = done_inst_m | retry_inst_m;
 
assign  tlu_exu_cwpccr_update_m = exu_done_inst_m | exu_retry_inst_m;
 
assign  tlu_exu_cwpccr_update_m = exu_done_inst_m | exu_retry_inst_m;
Line 1858... Line 1465... 
// modified for timing and bug4658 
// modified for timing and bug4658 
// modified for timing and added the omitted tlz trap qualification
 
// modified for timing and added the omitted tlz trap qualification
 
 
 
 
 
assign  true_pc_sel_m[0] =
 
assign  true_pc_sel_m[0] =
 
            retry_inst_m_tmp & ~ifu_tlu_trap_m & ifu_tlu_inst_vld_m &
 
            retry_inst_m_tmp & ~ifu_tlu_trap_m & ifu_tlu_inst_vld_m &
 
            ~(pib_wrap_trap_m | (|tlz_trap_m[4-1:0]));
 
            ~(pib_wrap_trap_m | (|tlz_trap_m[`TLU_THRD_NUM-1:0]));
 
assign  true_pc_sel_m[1]  =
 
assign  true_pc_sel_m[1]  =
 
            done_inst_m_tmp  & ~ifu_tlu_trap_m & ifu_tlu_inst_vld_m &
 
            done_inst_m_tmp  & ~ifu_tlu_trap_m & ifu_tlu_inst_vld_m &
 
            ~(pib_wrap_trap_m | (|tlz_trap_m[4-1:0])) ;
 
            ~(pib_wrap_trap_m | (|tlz_trap_m[`TLU_THRD_NUM-1:0])) ;
 
 
 
 
 
assign  true_pc_sel_m[2]  = ~(|true_pc_sel_m[1:0]);
 
assign  true_pc_sel_m[2]  = ~(|true_pc_sel_m[1:0]);
 
 
 
 
 
dffr #(3) dff_true_pc_sel_w (
 
dffr_s #(3) dff_true_pc_sel_w (
 
    .din (true_pc_sel_m[2:0]),
 
    .din (true_pc_sel_m[2:0]),
 
    .q   (true_pc_sel_w[2:0]),
 
    .q   (true_pc_sel_w[2:0]),
 
    .clk (clk),
 
    .clk (clk),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff #(49) dff_ifu_npc_w (
 
dff_s #(49) dff_ifu_npc_w (
 
    .din (ifu_tlu_npc_m[48:0]),
 
    .din (ifu_tlu_npc_m[48:0]),
 
    .q   (ifu_npc_w[48:0]),
 
    .q   (ifu_npc_w[48:0]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
assign tlu_true_pc_sel_w[2:0] = true_pc_sel_w[2:0];
 
assign tlu_true_pc_sel_w[2:0] = true_pc_sel_w[2:0];
 
 
 
 
 
dff #(2) dff_stgdntry_g (
 
dff_s #(2) dff_stgdntry_g (
 
    .din ({done_inst_m,retry_inst_m}),
 
    .din ({done_inst_m,retry_inst_m}),
 
        .q   ({done_inst_g_tmp,retry_inst_g_tmp}),
 
        .q   ({done_inst_g_tmp,retry_inst_g_tmp}),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
assign  done_inst_g = done_inst_g_tmp & inst_vld_g;
 
assign  done_inst_g = done_inst_g_tmp & inst_vld_g;
 
assign  retry_inst_g = retry_inst_g_tmp & inst_vld_g;
 
assign  retry_inst_g = retry_inst_g_tmp & inst_vld_g;
Line 1921... Line 1528... 
assign  dnrtry3_inst_g = (done_inst_g | retry_inst_g) &
 
assign  dnrtry3_inst_g = (done_inst_g | retry_inst_g) &
 
                        ~(inst_ifu_flush2_w | local_early_flush_pipe_w) &
 
                        ~(inst_ifu_flush2_w | local_early_flush_pipe_w) &
 
                          thread3_rsel_g;
 
                          thread3_rsel_g;
 
//
 
//
 
// added for timing
 
// added for timing
 
dffr #(4) dffr_dnrtry_inst_w2 (
 
dffr_s #(`TLU_THRD_NUM) dffr_dnrtry_inst_w2 (
 
    .din ({dnrtry3_inst_g,dnrtry2_inst_g,dnrtry1_inst_g,dnrtry0_inst_g}),
 
    .din ({dnrtry3_inst_g,dnrtry2_inst_g,dnrtry1_inst_g,dnrtry0_inst_g}),
 
    .q   (dnrtry_inst_w2[4-1:0]),
 
    .q   (dnrtry_inst_w2[`TLU_THRD_NUM-1:0]),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
assign  tlu_dnrtry0_inst_g = dnrtry0_inst_g;
 
assign  tlu_dnrtry0_inst_g = dnrtry0_inst_g;
 
assign  tlu_dnrtry1_inst_g = dnrtry1_inst_g;
 
assign  tlu_dnrtry1_inst_g = dnrtry1_inst_g;
Line 1942... Line 1549... 
// modified for timing
 
// modified for timing
 
// assign       dnrtry_inst_g = (done_inst_g | retry_inst_g) & ~tlu_flush_pipe_w;
 
// assign       dnrtry_inst_g = (done_inst_g | retry_inst_g) & ~tlu_flush_pipe_w;
 
// 
// 
assign  dnrtry_inst_g = (done_inst_g | retry_inst_g) &
 
assign  dnrtry_inst_g = (done_inst_g | retry_inst_g) &
 
                       ~(inst_ifu_flush_w | local_early_flush_pipe_w);
 
                       ~(inst_ifu_flush_w | local_early_flush_pipe_w);
 
dff #(2) dff_stgdntry_e (
 
dff_s #(2) dff_stgdntry_e (
 
    .din ({ifu_tlu_done_inst_d,ifu_tlu_retry_inst_d}),
 
    .din ({ifu_tlu_done_inst_d,ifu_tlu_retry_inst_d}),
 
        .q   ({done_inst_e,retry_inst_e}),
 
        .q   ({done_inst_e,retry_inst_e}),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
assign  thrid_d[1:0] = ifu_tlu_thrid_d[1:0];
 
assign  thrid_d[1:0] = ifu_tlu_thrid_d[1:0];
 
 
 
 
Line 1960... Line 1567... 
assign  thread2_rsel_d =  thrid_d[1] & ~thrid_d[0];
 
assign  thread2_rsel_d =  thrid_d[1] & ~thrid_d[0];
 
assign  thread3_rsel_d =  thrid_d[1] &  thrid_d[0];
 
assign  thread3_rsel_d =  thrid_d[1] &  thrid_d[0];
 
 
 
 
 
//
 
//
 
// modified due to rte failure 
// modified due to rte failure 
dff #(2) dff_thrid_e (
 
dff_s #(2) dff_thrid_e (
 
    .din (thrid_d[1:0]),
 
    .din (thrid_d[1:0]),
 
        .q   (thrid_e[1:0]),
 
        .q   (thrid_e[1:0]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff #(2) dff_thrid_m (
 
dff_s #(2) dff_thrid_m (
 
    .din (thrid_e[1:0]),
 
    .din (thrid_e[1:0]),
 
    .q   (thrid_m[1:0]),
 
    .q   (thrid_m[1:0]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff #(2) dff_thrid_g (
 
dff_s #(2) dff_thrid_g (
 
    .din (thrid_m[1:0]),
 
    .din (thrid_m[1:0]),
 
    .q   (thrid_g[1:0]),
 
    .q   (thrid_g[1:0]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
assign  thread0_rsel_e = ~(|thrid_e[1:0]);
 
assign  thread0_rsel_e = ~(|thrid_e[1:0]);
 
assign  thread1_rsel_e = ~thrid_e[1] &  thrid_e[0];
 
assign  thread1_rsel_e = ~thrid_e[1] &  thrid_e[0];
Line 1998... Line 1605... 
assign  tlu_thrd_rsel_e[1] = thread1_rsel_e;
 
assign  tlu_thrd_rsel_e[1] = thread1_rsel_e;
 
assign  tlu_thrd_rsel_e[2] = thread2_rsel_e;
 
assign  tlu_thrd_rsel_e[2] = thread2_rsel_e;
 
assign  tlu_thrd_rsel_e[3] = thread3_rsel_e;
 
assign  tlu_thrd_rsel_e[3] = thread3_rsel_e;
 
//
 
//
 
// added for timing
 
// added for timing
 
dff #(4) dff_thread_stg_m (
 
dff_s #(`TLU_THRD_NUM) dff_thread_stg_m (
 
    .din ({thread3_rsel_e, thread2_rsel_e, thread1_rsel_e, thread0_rsel_e}),
 
    .din ({thread3_rsel_e, thread2_rsel_e, thread1_rsel_e, thread0_rsel_e}),
 
    .q   ({thread3_stg_m, thread2_stg_m, thread1_stg_m, thread0_stg_m}),
 
    .q   ({thread3_stg_m, thread2_stg_m, thread1_stg_m, thread0_stg_m}),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
assign thread0_stg_m_buf = thread0_stg_m;
 
assign thread0_stg_m_buf = thread0_stg_m;
 
assign thread1_stg_m_buf = thread1_stg_m;
 
assign thread1_stg_m_buf = thread1_stg_m;
Line 2022... Line 1629... 
assign  thread0_rsel_dec_g = ~(|thrid_g[1:0]);
 
assign  thread0_rsel_dec_g = ~(|thrid_g[1:0]);
 
assign  thread1_rsel_dec_g = ~thrid_g[1] &  thrid_g[0];
 
assign  thread1_rsel_dec_g = ~thrid_g[1] &  thrid_g[0];
 
assign  thread2_rsel_dec_g =  thrid_g[1] & ~thrid_g[0];
 
assign  thread2_rsel_dec_g =  thrid_g[1] & ~thrid_g[0];
 
assign  thread3_rsel_dec_g =  (&thrid_g[1:0]);
 
assign  thread3_rsel_dec_g =  (&thrid_g[1:0]);
 
 
 
 
 
dff #(4) dff_thread_rsel_g (
 
dff_s #(`TLU_THRD_NUM) dff_thread_rsel_g (
 
    .din ({thread3_rsel_m, thread2_rsel_m, thread1_rsel_m, thread0_rsel_m}),
 
    .din ({thread3_rsel_m, thread2_rsel_m, thread1_rsel_m, thread0_rsel_m}),
 
    .q   ({thread3_rsel_g, thread2_rsel_g, thread1_rsel_g, thread0_rsel_g}),
 
    .q   ({thread3_rsel_g, thread2_rsel_g, thread1_rsel_g, thread0_rsel_g}),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff #(4) dff_thread_wsel_g (
 
dff_s #(`TLU_THRD_NUM) dff_thread_wsel_g (
 
    .din ({thread3_rsel_m, thread2_rsel_m, thread1_rsel_m, thread0_rsel_m}),
 
    .din ({thread3_rsel_m, thread2_rsel_m, thread1_rsel_m, thread0_rsel_m}),
 
    .q   ({thread3_wsel_g, thread2_wsel_g, thread1_wsel_g, thread0_wsel_g}),
 
    .q   ({thread3_wsel_g, thread2_wsel_g, thread1_wsel_g, thread0_wsel_g}),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
// timing -fix: load redistribution
 
// timing -fix: load redistribution
 
/*
 
/*
 
assign  thread0_rsel_g = thread0_rsel_dec_g;
 
assign  thread0_rsel_g = thread0_rsel_dec_g;
Line 2048... Line 1655... 
assign  thread2_rsel_g = thread2_rsel_dec_g;
 
assign  thread2_rsel_g = thread2_rsel_dec_g;
 
assign  thread3_rsel_g = thread3_rsel_dec_g;
 
assign  thread3_rsel_g = thread3_rsel_dec_g;
 
*/
 
*/
 
// 
// 
 
 
 
 
dff #(2) dff_stgdntry_w2 (
 
dff_s #(2) dff_stgdntry_w2 (
 
    .din ({done_inst_g,retry_inst_g}),
 
    .din ({done_inst_g,retry_inst_g}),
 
        .q   ({done_inst_w2,retry_inst_w2}),
 
        .q   ({done_inst_w2,retry_inst_w2}),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
//
 
//
 
// modified for bug 4561
 
// modified for bug 4561
 
assign inst_vld_m =
 
assign inst_vld_m =
Line 2073... Line 1680... 
 
 
 
 
assign tlu_inst_vld_nq_m =
 
assign tlu_inst_vld_nq_m =
 
           ifu_tlu_inst_vld_m & ~((thrid_g[1:0] == tlu_exu_tid_m[1:0]) &
 
           ifu_tlu_inst_vld_m & ~((thrid_g[1:0] == tlu_exu_tid_m[1:0]) &
 
           tlu_flush_all_w);
 
           tlu_flush_all_w);
 
 
 
 
 
dff dff_stgivld_g (
 
dff_s dff_stgivld_g (
 
    .din (inst_vld_m),
 
    .din (inst_vld_m),
 
    .q   (inst_vld_nf_g),
 
    .q   (inst_vld_nf_g),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
//
 
//
 
// modified for timing
 
// modified for timing
 
/*
 
/*
 
dffr dffr_inst_ifu_flush_w (
 
dffr_s dffr_inst_ifu_flush_w (
 
    .din (ifu_tlu_flush_m),
 
    .din (ifu_tlu_flush_m),
 
        .q   (inst_ifu_flush_w),
 
        .q   (inst_ifu_flush_w),
 
    .clk (clk),
 
    .clk (clk),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
*/
 
*/
 
assign inst_ifu_flush_w  = ifu_tlu_flush_fd_w;
 
assign inst_ifu_flush_w  = ifu_tlu_flush_fd_w;
 
assign inst_ifu_flush2_w = ifu_tlu_flush_fd_w;
 
assign inst_ifu_flush2_w = ifu_tlu_flush_fd_w;
Line 2104... Line 1711... 
       inst_vld_nf_g & ~(inst_ifu_flush_w | lsu_tlu_defr_trp_taken_g);
 
       inst_vld_nf_g & ~(inst_ifu_flush_w | lsu_tlu_defr_trp_taken_g);
 
       // modified for bug 4561
 
       // modified for bug 4561
 
       // inst_vld_nf_g & ~(inst_ifu_flush_w | lsu_tlu_defr_trp_taken_g | 
       // inst_vld_nf_g & ~(inst_ifu_flush_w | lsu_tlu_defr_trp_taken_g | 
       // ((thrid_w2[1:0] == thrid_g[1:0]) & lsu_defr_trap_g));
 
       // ((thrid_w2[1:0] == thrid_g[1:0]) & lsu_defr_trap_g));
 
 
 
 
 
dff dff_stgivld_w2 (
 
dff_s dff_stgivld_w2 (
 
    .din (inst_vld_g),
 
    .din (inst_vld_g),
 
        .q   (inst_vld_w2),
 
        .q   (inst_vld_w2),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
//
 
//
 
// modified due to timing
 
// modified due to timing
 
// assign       cwp_fastcmplt_g = cwp_fastcmplt_w & inst_vld_g;
 
// assign       cwp_fastcmplt_g = cwp_fastcmplt_w & inst_vld_g;
 
assign  cwp_fastcmplt_g = cwp_fastcmplt_uq_g & inst_vld_g;
 
assign  cwp_fastcmplt_g = cwp_fastcmplt_uq_g & inst_vld_g;
 
 
 
 
 
dff dff_stgfcmplt_w2 (
 
dff_s dff_stgfcmplt_w2 (
 
    .din (cwp_fastcmplt_g),
 
    .din (cwp_fastcmplt_g),
 
        .q   (cwp_fastcmplt_w2),
 
        .q   (cwp_fastcmplt_w2),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
// The stage name assignment may have to be changed !!
 
// The stage name assignment may have to be changed !!
 
// done/retry qualified with inst_vld as it could be flushed.
 
// done/retry qualified with inst_vld as it could be flushed.
Line 2159... Line 1766... 
assign  true_trap_tid_g[1:0] =
 
assign  true_trap_tid_g[1:0] =
 
             // (lsu_defr_trap_g) ? thrid_w2[1:0]  : 
             // (lsu_defr_trap_g) ? thrid_w2[1:0]  : 
             (dside_sync_trap_g | lsu_defr_trap_g) ? thrid_g[1:0] :
 
             (dside_sync_trap_g | lsu_defr_trap_g) ? thrid_g[1:0] :
 
              early_trap_tid_g[1:0];
 
              early_trap_tid_g[1:0];
 
 
 
 
 
dff #(2) dff_true_trap_tid_w2 (
 
dff_s #(2) dff_true_trap_tid_w2 (
 
    .din (true_trap_tid_g[1:0]),
 
    .din (true_trap_tid_g[1:0]),
 
    .q   (true_trap_tid_w2[1:0]),
 
    .q   (true_trap_tid_w2[1:0]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
assign tlu_ifu_trap_tid_w1[1:0] = true_trap_tid_w2[1:0];
 
assign tlu_ifu_trap_tid_w1[1:0] = true_trap_tid_w2[1:0];
 
 
 
 
 
// determine the mode of operation for the trapped thread
 
// determine the mode of operation for the trapped thread
Line 2204... Line 1811... 
assign  tlu_lsu_priv_trap_m =
 
assign  tlu_lsu_priv_trap_m =
 
               (true_hscpd_dacc_excpt_m | true_qtail_dacc_excpt_m);
 
               (true_hscpd_dacc_excpt_m | true_qtail_dacc_excpt_m);
 
//
 
//
 
/*
 
/*
 
// added for timing
 
// added for timing
 
dffr dffr_tlu_lsu_priv_trap_w  (
 
dffr_s dffr_tlu_lsu_priv_trap_w  (
 
    .din (tlu_lsu_priv_trap_m),
 
    .din (tlu_lsu_priv_trap_m),
 
    .q   (tlu_lsu_priv_trap_w),
 
    .q   (tlu_lsu_priv_trap_w),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
//
 
//
 
*/
 
*/
 
// added for timing 
// added for timing
Line 2234... Line 1841... 
            (thread2_stg_m_buf & tlu_hpstate_enb[2] &  ~tlu_hpstate_priv[2] &
 
            (thread2_stg_m_buf & tlu_hpstate_enb[2] &  ~tlu_hpstate_priv[2] &
 
             tlu_pstate_priv_buf[2])  |
 
             tlu_pstate_priv_buf[2])  |
 
            (thread3_stg_m_buf & tlu_hpstate_enb[3] &  ~tlu_hpstate_priv[3] &
 
            (thread3_stg_m_buf & tlu_hpstate_enb[3] &  ~tlu_hpstate_priv[3] &
 
             tlu_pstate_priv_buf[3])) & tlu_qtail_dacc_excpt_m;
 
             tlu_pstate_priv_buf[3])) & tlu_qtail_dacc_excpt_m;
 
 
 
 
 
dffr dffr_local_sync_trap_g  (
 
dffr_s dffr_local_sync_trap_g  (
 
    .din (local_sync_trap_m),
 
    .din (local_sync_trap_m),
 
    .q   (local_sync_trap_g),
 
    .q   (local_sync_trap_g),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
//=========================================================================================
 
//=========================================================================================
 
//      Queuing traps
 
//      Queuing traps
Line 2271... Line 1878... 
assign ifu_thrd_flush_w[2] = inst_ifu_flush2_w & thread2_rsel_dec_g;
 
assign ifu_thrd_flush_w[2] = inst_ifu_flush2_w & thread2_rsel_dec_g;
 
assign ifu_thrd_flush_w[3] = inst_ifu_flush2_w & thread3_rsel_dec_g;
 
assign ifu_thrd_flush_w[3] = inst_ifu_flush2_w & thread3_rsel_dec_g;
 
 
 
 
 
 
 
 
 
// INTERRUPT
 
// INTERRUPT
 
dff #(9) dff_stgint_g (
 
dff_s #(9) dff_stgint_g (
 
   .din ({ifu_rstint_m,ifu_hwint_m,ifu_swint_m,int_tlu_rstid_m[5:0]}),
 
   .din ({ifu_rstint_m,ifu_hwint_m,ifu_swint_m,int_tlu_rstid_m[5:0]}),
 
   .q   ({rstint_g,hwint_g,swint_g,rstid_g[5:0]}),
 
   .q   ({rstint_g,hwint_g,swint_g,rstid_g[5:0]}),
 
   .clk (clk),
 
   .clk (clk),
 
   .se  (se),
 
   .se  (se),
 
   .si  (),
 
   `SIMPLY_RISC_SCANIN,
 
   .so  ()
 
   .so  ()
 
);
 
);
 
 
 
 
 
// Determine type of reset. Type of reset determines what state gets updated.
 
// Determine type of reset. Type of reset determines what state gets updated.
 
// This is the same as wrm reset !!! Can we then turn off writes to TNPC, TPC ???
 
// This is the same as wrm reset !!! Can we then turn off writes to TNPC, TPC ???
Line 2291... Line 1898... 
assign  por_rstint3_g = por_rstint_g & thread3_rsel_g;
 
assign  por_rstint3_g = por_rstint_g & thread3_rsel_g;
 
// 
// 
// added for bug 4749 
// added for bug 4749 
assign  xir_rstint_g = ((rstid_g[5:0] == 6'h03) & rstint_g);
 
assign  xir_rstint_g = ((rstid_g[5:0] == 6'h03) & rstint_g);
 
 
 
 
 
dff dff_por_rstint_w2 (
 
dff_s dff_por_rstint_w2 (
 
    .din (por_rstint_g),
 
    .din (por_rstint_g),
 
        .q   (por_rstint_w2),
 
        .q   (por_rstint_w2),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
assign  por_rstint0_w2 = por_rstint_w2 & thread0_wsel_w2;
 
assign  por_rstint0_w2 = por_rstint_w2 & thread0_wsel_w2;
 
assign  por_rstint1_w2 = por_rstint_w2 & thread1_wsel_w2;
 
assign  por_rstint1_w2 = por_rstint_w2 & thread1_wsel_w2;
Line 2320... Line 1927... 
//
 
//
 
// modified for bug 5127
 
// modified for bug 5127
 
// assign       sirint_taken = sir_inst_g & inst_vld_g; 
// assign       sirint_taken = sir_inst_g & inst_vld_g; 
assign  sirint_taken =
 
assign  sirint_taken =
 
            sir_inst_g & inst_vld_g  & ~(pib_wrap_trap_nq_g |
 
            sir_inst_g & inst_vld_g  & ~(pib_wrap_trap_nq_g |
 
            lsu_tlu_defr_trp_taken_g | (|tlz_trap_g[4-1:0]));
 
            lsu_tlu_defr_trp_taken_g | (|tlz_trap_g[`TLU_THRD_NUM-1:0]));
 
 
 
 
 
assign  swint_taken = swint_g & inst_vld_g;
 
assign  swint_taken = swint_g & inst_vld_g;
 
 
 
 
 
/*
 
/*
 
assign  swint_thrd0_taken = swint_taken & thread0_rsel_g & tlu_int_pstate_ie[0];
 
assign  swint_thrd0_taken = swint_taken & thread0_rsel_g & tlu_int_pstate_ie[0];
Line 2340... Line 1947... 
                                swint_thrd3_taken ? sftint3_id[3:0] :
 
                                swint_thrd3_taken ? sftint3_id[3:0] :
 
                                        4'bxxxx;
 
                                        4'bxxxx;
 
*/
 
*/
 
//
 
//
 
//added for timing 
//added for timing 
dffr #(4) dffr_tlu_cpu_mondo_trap (
 
dffr_s #(`TLU_THRD_NUM) dffr_tlu_cpu_mondo_trap (
 
    .din (tlu_cpu_mondo_cmp[4-1:0]),
 
    .din (tlu_cpu_mondo_cmp[`TLU_THRD_NUM-1:0]),
 
    .q   (tlu_cpu_mondo_trap[4-1:0]),
 
    .q   (tlu_cpu_mondo_trap[`TLU_THRD_NUM-1:0]),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
//
 
//
 
dffr #(4) dffr_tlu_dev_mondo_trap (
 
dffr_s #(`TLU_THRD_NUM) dffr_tlu_dev_mondo_trap (
 
    .din (tlu_dev_mondo_cmp[4-1:0]),
 
    .din (tlu_dev_mondo_cmp[`TLU_THRD_NUM-1:0]),
 
    .q   (tlu_dev_mondo_trap[4-1:0]),
 
    .q   (tlu_dev_mondo_trap[`TLU_THRD_NUM-1:0]),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dffr #(4) dffr_tlu_resum_err_trap (
 
dffr_s #(`TLU_THRD_NUM) dffr_tlu_resum_err_trap (
 
    .din (tlu_resum_err_cmp[4-1:0]),
 
    .din (tlu_resum_err_cmp[`TLU_THRD_NUM-1:0]),
 
    .q   (tlu_resum_err_trap[4-1:0]),
 
    .q   (tlu_resum_err_trap[`TLU_THRD_NUM-1:0]),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
//
 
//
 
assign cpu_mondo_trap_g =
 
assign cpu_mondo_trap_g =
 
       (thread0_wsel_g)? tlu_cpu_mondo_trap[0]:
 
       (thread0_wsel_g)? tlu_cpu_mondo_trap[0]:
Line 2388... Line 1995... 
       (thread0_wsel_w2)? sftint0_id[3:0]:
 
       (thread0_wsel_w2)? sftint0_id[3:0]:
 
       (thread1_wsel_w2)? sftint1_id[3:0]:
 
       (thread1_wsel_w2)? sftint1_id[3:0]:
 
       (thread2_wsel_w2)? sftint2_id[3:0]:
 
       (thread2_wsel_w2)? sftint2_id[3:0]:
 
        sftint3_id[3:0];
 
        sftint3_id[3:0];
 
 
 
 
 
dffr dffr_cpu_mondo_trap_w2 (
 
dffr_s dffr_cpu_mondo_trap_w2 (
 
    .din (cpu_mondo_trap_g),
 
    .din (cpu_mondo_trap_g),
 
    .q   (cpu_mondo_trap_w2),
 
    .q   (cpu_mondo_trap_w2),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dffr dffr_dev_mondo_trap_w2 (
 
dffr_s dffr_dev_mondo_trap_w2 (
 
    .din (dev_mondo_trap_g),
 
    .din (dev_mondo_trap_g),
 
    .q   (dev_mondo_trap_w2),
 
    .q   (dev_mondo_trap_w2),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
assign final_swint_id_w2[6:0] =
 
assign final_swint_id_w2[6:0] =
 
       (cpu_mondo_trap_w2)? 7'h7c :
 
       (cpu_mondo_trap_w2)? `CPU_MONDO_TRAP :
 
       (dev_mondo_trap_w2)? 7'h7d :
 
       (dev_mondo_trap_w2)? `DEV_MONDO_TRAP :
 
        {3'b100, sftint_id_w2[3:0]};
 
        {3'b100, sftint_id_w2[3:0]};
 
 
 
 
 
// recoded for timing for bug 5117
 
// recoded for timing for bug 5117
 
/*
 
/*
 
assign final_swint0_id[6:0] =
 
assign final_swint0_id[6:0] =
Line 2479... Line 2086... 
//
 
//
 
// modified for bug 4640 and bug5127 
// modified for bug 4640 and bug5127 
assign  tlu_self_boot_rst_g =
 
assign  tlu_self_boot_rst_g =
 
              rstint_g | internal_wdr | (sir_inst_g &
 
              rstint_g | internal_wdr | (sir_inst_g &
 
              ~(lsu_defr_trap_g | pib_wrap_trap_g |
 
              ~(lsu_defr_trap_g | pib_wrap_trap_g |
 
               (|tlz_trap_g[4-1:0]))) | trap_to_redmode;
 
               (|tlz_trap_g[`TLU_THRD_NUM-1:0]))) | trap_to_redmode;
 
              // (rstint_g | internal_wdr | (sir_inst_g & ~lsu_defr_trap_g) |
 
              // (rstint_g | internal_wdr | (sir_inst_g & ~lsu_defr_trap_g) |
 
 
 
 
 
//
 
//
 
// added for timing; moved qualification from IFU to TLU
 
// added for timing; moved qualification from IFU to TLU
 
// modified for bug 4561
 
// modified for bug 4561
Line 2496... Line 2103... 
            ~((thrid_g[1:0] == tlu_exu_tid_m[1:0]) & tlu_flush_pipe_w) &
 
            ~((thrid_g[1:0] == tlu_exu_tid_m[1:0]) & tlu_flush_pipe_w) &
 
            ~((thrid_w2[1:0] == tlu_exu_tid_m[1:0]) & lsu_defr_trap_g);
 
            ~((thrid_w2[1:0] == tlu_exu_tid_m[1:0]) & lsu_defr_trap_g);
 
*/
 
*/
 
 
 
 
 
// REGULAR TRAP
 
// REGULAR TRAP
 
dff #(20) dff_stgeftt_g (
 
dff_s #(20) dff_stgeftt_g (
 
    .din ({exu_tlu_ttype_m[8:0],exu_tlu_ttype_vld_m,ifu_tlu_ttype_m[8:0],ifu_ttype_vld_m}),
 
    .din ({exu_tlu_ttype_m[8:0],exu_tlu_ttype_vld_m,ifu_tlu_ttype_m[8:0],ifu_ttype_vld_m}),
 
    .q   ({exu_ttype_g[8:0],exu_ttype_vld_g,ifu_ttype_tmp_g[8:0],ifu_ttype_vld_tmp_g}),
 
    .q   ({exu_ttype_g[8:0],exu_ttype_vld_g,ifu_ttype_tmp_g[8:0],ifu_ttype_vld_tmp_g}),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
// added for bug 1293
 
// added for bug 1293
 
// added spu_tlu_rsrv_illgl_m2 to account for the new illeg_instr from spu
 
// added spu_tlu_rsrv_illgl_m2 to account for the new illeg_instr from spu
Line 2548... Line 2155... 
 
 
 
 
assign htrap_ill_inst_m =
 
assign htrap_ill_inst_m =
 
    (exu_tlu_ttype_vld_m &  exu_tlu_ttype_m[8] &
 
    (exu_tlu_ttype_vld_m &  exu_tlu_ttype_m[8] &
 
     exu_tlu_ttype_m[7]) &  tlu_none_priv_m;
 
     exu_tlu_ttype_m[7]) &  tlu_none_priv_m;
 
 
 
 
 
dffr dffr_htrap_ill_inst_uf_g (
 
dffr_s dffr_htrap_ill_inst_uf_g (
 
   .din (htrap_ill_inst_m),
 
   .din (htrap_ill_inst_m),
 
   .q   (htrap_ill_inst_uf_g),
 
   .q   (htrap_ill_inst_uf_g),
 
   .rst (local_rst),
 
   .rst (local_rst),
 
   .clk (clk),
 
   .clk (clk),
 
   .se  (se),
 
   .se  (se),
 
   .si  (),
 
   `SIMPLY_RISC_SCANIN,
 
   .so  ()
 
   .so  ()
 
);
 
);
 
 
 
 
 
assign htrap_ill_inst_g = htrap_ill_inst_uf_g & ~inst_ifu_flush_w;
 
assign htrap_ill_inst_g = htrap_ill_inst_uf_g & ~inst_ifu_flush_w;
 
// 
// 
// added for timing fix
 
// added for timing fix
 
assign spu_ill_inst_m = spu_tlu_rsrv_illgl_m & inst_vld_m;
 
assign spu_ill_inst_m = spu_tlu_rsrv_illgl_m & inst_vld_m;
 
 
 
 
 
dffr dffr_spu_ill_inst_uf_g (
 
dffr_s dffr_spu_ill_inst_uf_g (
 
   .din (spu_ill_inst_m),
 
   .din (spu_ill_inst_m),
 
   // modified for bug 2133
 
   // modified for bug 2133
 
   // .q   (spu_ill_inst_g),
 
   // .q   (spu_ill_inst_g),
 
   .q   (spu_ill_inst_uf_g),
 
   .q   (spu_ill_inst_uf_g),
 
   .rst (local_rst),
 
   .rst (local_rst),
 
   .clk (clk),
 
   .clk (clk),
 
   .se  (se),
 
   .se  (se),
 
   .si  (),
 
   `SIMPLY_RISC_SCANIN,
 
   .so  ()
 
   .so  ()
 
);
 
);
 
 
 
 
 
 
 
 
 
// 
//
Line 2657... Line 2264... 
assign pib_trap_en[1] = tlu_int_pstate_ie[1] & (true_pil1[3:0] < 4'hf);
 
assign pib_trap_en[1] = tlu_int_pstate_ie[1] & (true_pil1[3:0] < 4'hf);
 
assign pib_trap_en[2] = tlu_int_pstate_ie[2] & (true_pil2[3:0] < 4'hf);
 
assign pib_trap_en[2] = tlu_int_pstate_ie[2] & (true_pil2[3:0] < 4'hf);
 
assign pib_trap_en[3] = tlu_int_pstate_ie[3] & (true_pil3[3:0] < 4'hf);
 
assign pib_trap_en[3] = tlu_int_pstate_ie[3] & (true_pil3[3:0] < 4'hf);
 
//
 
//
 
// added for bug 5017
 
// added for bug 5017
 
dffr dffr_picl_wrap_pend_0 (
 
dffr_s dffr_picl_wrap_pend_0 (
 
    .din (pib_picl_wrap[0]),
 
    .din (pib_picl_wrap[0]),
 
    .q   (picl_wrap_pend[0]),
 
    .q   (picl_wrap_pend[0]),
 
    .rst (local_rst | (thread_inst_vld_w2[0] & ~pib_picl_wrap[0] & ~tlu_full_flush_pipe_w2)),
 
    .rst (local_rst | (thread_inst_vld_w2[0] & ~pib_picl_wrap[0] & ~tlu_full_flush_pipe_w2)),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
dffr dffr_picl_wrap_pend_1 (
 
dffr_s dffr_picl_wrap_pend_1 (
 
    .din (pib_picl_wrap[1]),
 
    .din (pib_picl_wrap[1]),
 
    .q   (picl_wrap_pend[1]),
 
    .q   (picl_wrap_pend[1]),
 
    .rst (local_rst | (thread_inst_vld_w2[1] & ~pib_picl_wrap[1] & ~tlu_full_flush_pipe_w2)),
 
    .rst (local_rst | (thread_inst_vld_w2[1] & ~pib_picl_wrap[1] & ~tlu_full_flush_pipe_w2)),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
dffr dffr_picl_wrap_pend_2 (
 
dffr_s dffr_picl_wrap_pend_2 (
 
    .din (pib_picl_wrap[2]),
 
    .din (pib_picl_wrap[2]),
 
    .q   (picl_wrap_pend[2]),
 
    .q   (picl_wrap_pend[2]),
 
    .rst (local_rst | (thread_inst_vld_w2[2] & ~pib_picl_wrap[2] & ~tlu_full_flush_pipe_w2)),
 
    .rst (local_rst | (thread_inst_vld_w2[2] & ~pib_picl_wrap[2] & ~tlu_full_flush_pipe_w2)),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
dffr dffr_picl_wrap_pend_3 (
 
dffr_s dffr_picl_wrap_pend_3 (
 
    .din (pib_picl_wrap[3]),
 
    .din (pib_picl_wrap[3]),
 
    .q   (picl_wrap_pend[3]),
 
    .q   (picl_wrap_pend[3]),
 
    .rst (local_rst | (thread_inst_vld_w2[3] & ~pib_picl_wrap[3] & ~tlu_full_flush_pipe_w2)),
 
    .rst (local_rst | (thread_inst_vld_w2[3] & ~pib_picl_wrap[3] & ~tlu_full_flush_pipe_w2)),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
assign tlu_picl_wrap_flg_m =
 
assign tlu_picl_wrap_flg_m =
 
       (picl_wrap_pend[0] & thread0_stg_m_buf) |
 
       (picl_wrap_pend[0] & thread0_stg_m_buf) |
Line 2858... Line 2465... 
*/
 
*/
 
 
 
 
 
 
 
 
 
wire [3:0] pib_pich_wrap_q;
 
wire [3:0] pib_pich_wrap_q;
 
 
 
 
 
dffr #(4) dffr_pib_pich_wrap (
 
dffr_s #(`TLU_THRD_NUM) dffr_pib_pich_wrap (
 
   .din (pib_pich_wrap_m[4-1:0]),
 
   .din (pib_pich_wrap_m[`TLU_THRD_NUM-1:0]),
 
   .q   (pib_pich_wrap_q[4-1:0]),
 
   .q   (pib_pich_wrap_q[`TLU_THRD_NUM-1:0]),
 
   .rst (local_rst),
 
   .rst (local_rst),
 
   .clk (clk),
 
   .clk (clk),
 
   .se  (se),
 
   .se  (se),
 
   .si  (),
 
   `SIMPLY_RISC_SCANIN,
 
   .so  ()
 
   .so  ()
 
);
 
);
 
 
 
 
 
// added for the bug 5436 reopened on 9/16/2004 by Samy. The following pushes
 
// added for the bug 5436 reopened on 9/16/2004 by Samy. The following pushes
 
// the qualification by hold signal to G stage.So sofint bit15 is set for signaling
 
// the qualification by hold signal to G stage.So sofint bit15 is set for signaling
Line 2893... Line 2500... 
           (tlu_thrd_rsel_e[1]) ? pich_exu_wrap_e[1]:
 
           (tlu_thrd_rsel_e[1]) ? pich_exu_wrap_e[1]:
 
           (tlu_thrd_rsel_e[2]) ? pich_exu_wrap_e[2]:
 
           (tlu_thrd_rsel_e[2]) ? pich_exu_wrap_e[2]:
 
            pich_exu_wrap_e[3];
 
            pich_exu_wrap_e[3];
 
*/
 
*/
 
 
 
 
 
dffr dffr_pich_wrap_flg_m (
 
dffr_s dffr_pich_wrap_flg_m (
 
   .din (tlu_pic_wrap_e),
 
   .din (tlu_pic_wrap_e),
 
   .q   (pich_wrap_flg_m),
 
   .q   (pich_wrap_flg_m),
 
   .rst (local_rst),
 
   .rst (local_rst),
 
   .clk (clk),
 
   .clk (clk),
 
   .se  (se),
 
   .se  (se),
 
   .si  (),
 
   `SIMPLY_RISC_SCANIN,
 
   .so  ()
 
   .so  ()
 
);
 
);
 
//
 
//
 
// modified for bug 5436 - Niagara 2.0
 
// modified for bug 5436 - Niagara 2.0
 
assign tlu_pich_wrap_flg_m =
 
assign tlu_pich_wrap_flg_m =
Line 2974... Line 2581... 
             (~pic_hpstate_enb_e  & pic_hpstate_priv_e & pcr_st_e) |
 
             (~pic_hpstate_enb_e  & pic_hpstate_priv_e & pcr_st_e) |
 
             (pic_hpstate_enb_e   & pic_pstate_priv_e  & ~pic_hpstate_priv_e &
 
             (pic_hpstate_enb_e   & pic_pstate_priv_e  & ~pic_hpstate_priv_e &
 
              pcr_st_e)) & pic_trap_en_e;
 
              pcr_st_e)) & pic_trap_en_e;
 
*/
 
*/
 
 
 
 
 
dffr dffr_tlu_pic_cnt_en_m (
 
dffr_s dffr_tlu_pic_cnt_en_m (
 
   .din (pic_cnt_en_e),
 
   .din (pic_cnt_en_e),
 
   .q   (pic_cnt_en_m),
 
   .q   (pic_cnt_en_m),
 
   .rst (local_rst),
 
   .rst (local_rst),
 
   .clk (clk),
 
   .clk (clk),
 
   .se  (se),
 
   .se  (se),
 
   .si  (),
 
   `SIMPLY_RISC_SCANIN,
 
   .so  ()
 
   .so  ()
 
);
 
);
 
 
 
 
 
/**** replaced the following with and-or for better synthesis interms of timing
 
/**** replaced the following with and-or for better synthesis interms of timing
 
assign tlu_pich_cnt_hld =
 
assign tlu_pich_cnt_hld =
Line 3009... Line 2616... 
           (tlu_thrd_rsel_e[2]) ? pib_trap_en[2]:
 
           (tlu_thrd_rsel_e[2]) ? pib_trap_en[2]:
 
            pib_trap_en[3];
 
            pib_trap_en[3];
 
 
 
 
 
wire pic_trap_en_m;
 
wire pic_trap_en_m;
 
 
 
 
 
dffr dffr_pic_trap_en_m (
 
dffr_s dffr_pic_trap_en_m (
 
   .din (pic_trap_en_e),
 
   .din (pic_trap_en_e),
 
   .q   (pic_trap_en_m),
 
   .q   (pic_trap_en_m),
 
   .rst (local_rst), .clk (clk), .se  (se), .si  (), .so  ());
 
   .rst (local_rst), .clk (clk), .se  (se), `SIMPLY_RISC_SCANIN, .so  ());
 
 
 
 
 
wire tlu_pic_cnt_en_m_prequal = pic_cnt_en_m & pic_trap_en_m;
 
wire tlu_pic_cnt_en_m_prequal = pic_cnt_en_m & pic_trap_en_m;
 
 
 
 
 
assign tlu_pic_cnt_en_m = tlu_pic_cnt_en_m_prequal & ~tlu_pich_cnt_hld;
 
assign tlu_pic_cnt_en_m = tlu_pic_cnt_en_m_prequal & ~tlu_pich_cnt_hld;
 
 
 
 
 
//
 
//
 
// added for bug 5436 - Niagara 2.0
 
// added for bug 5436 - Niagara 2.0
 
dffr dffr_pic_cnt_en_w (
 
dffr_s dffr_pic_cnt_en_w (
 
   .din (pic_cnt_en_m),
 
   .din (pic_cnt_en_m),
 
   .q   (pic_cnt_en_w),
 
   .q   (pic_cnt_en_w),
 
   .rst (local_rst),
 
   .rst (local_rst),
 
   .clk (clk),
 
   .clk (clk),
 
   .se  (se),
 
   .se  (se),
 
   .si  (),
 
   `SIMPLY_RISC_SCANIN,
 
   .so  ()
 
   .so  ()
 
);
 
);
 
 
 
 
 
dffr dffr_pic_cnt_en_w2 (
 
dffr_s dffr_pic_cnt_en_w2 (
 
   .din (pic_cnt_en_w),
 
   .din (pic_cnt_en_w),
 
   .q   (pic_cnt_en_w2),
 
   .q   (pic_cnt_en_w2),
 
   .rst (local_rst),
 
   .rst (local_rst),
 
   .clk (clk),
 
   .clk (clk),
 
   .se  (se),
 
   .se  (se),
 
   .si  (),
 
   `SIMPLY_RISC_SCANIN,
 
   .so  ()
 
   .so  ()
 
);
 
);
 
 
 
 
 
/*
 
/*
 
// added for bug 4785
 
// added for bug 4785
Line 3048... Line 2655... 
           (thread0_rsel_e) ? pich_onebelow_flg[0] :
 
           (thread0_rsel_e) ? pich_onebelow_flg[0] :
 
           (thread1_rsel_e) ? pich_onebelow_flg[1] :
 
           (thread1_rsel_e) ? pich_onebelow_flg[1] :
 
           (thread2_rsel_e) ? pich_onebelow_flg[2] :
 
           (thread2_rsel_e) ? pich_onebelow_flg[2] :
 
           pich_onebelow_flg[3];
 
           pich_onebelow_flg[3];
 
 
 
 
 
dffr dffr_tlu_exu_pic_onebelow_m (
 
dffr_s dffr_tlu_exu_pic_onebelow_m (
 
   .din (tlu_pic_onebelow_e),
 
   .din (tlu_pic_onebelow_e),
 
   .q   (tlu_exu_pic_onebelow_m),
 
   .q   (tlu_exu_pic_onebelow_m),
 
   .rst (local_rst),
 
   .rst (local_rst),
 
   .clk (clk),
 
   .clk (clk),
 
   .se  (se),
 
   .se  (se),
 
   .si  (),
 
   `SIMPLY_RISC_SCANIN,
 
   .so  ()
 
   .so  ()
 
);
 
);
 
 
 
 
 
assign tlu_pic_twobelow_e =
 
assign tlu_pic_twobelow_e =
 
           (thread0_rsel_e) ? pich_twobelow_flg[0] :
 
           (thread0_rsel_e) ? pich_twobelow_flg[0] :
 
           (thread1_rsel_e) ? pich_twobelow_flg[1] :
 
           (thread1_rsel_e) ? pich_twobelow_flg[1] :
 
           (thread2_rsel_e) ? pich_twobelow_flg[2] :
 
           (thread2_rsel_e) ? pich_twobelow_flg[2] :
 
           pich_twobelow_flg[3];
 
           pich_twobelow_flg[3];
 
 
 
 
 
dffr dffr_tlu_exu_pic_twobelow_m (
 
dffr_s dffr_tlu_exu_pic_twobelow_m (
 
   .din (tlu_pic_twobelow_e),
 
   .din (tlu_pic_twobelow_e),
 
   .q   (tlu_exu_pic_twobelow_m),
 
   .q   (tlu_exu_pic_twobelow_m),
 
   .rst (local_rst),
 
   .rst (local_rst),
 
   .clk (clk),
 
   .clk (clk),
 
   .se  (se),
 
   .se  (se),
 
   .si  (),
 
   `SIMPLY_RISC_SCANIN,
 
   .so  ()
 
   .so  ()
 
);
 
);
 
*/
 
*/
 
//
 
//
 
// added for bug 4395
 
// added for bug 4395
 
dffr dffr_tlu_tcc_inst_w (
 
dffr_s dffr_tlu_tcc_inst_w (
 
    .din (exu_tlu_ttype_m[8]),
 
    .din (exu_tlu_ttype_m[8]),
 
    .q   (tlu_tcc_inst_w),
 
    .q   (tlu_tcc_inst_w),
 
    .clk (clk),
 
    .clk (clk),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
//
 
//
 
assign pib_wrap_trap_m = (|pib_wrap_m[4-1:0]);
 
assign pib_wrap_trap_m = (|pib_wrap_m[`TLU_THRD_NUM-1:0]);
 
//
 
//
 
// modified for bug 4342
 
// modified for bug 4342
 
// pib wrap precise trap 
// pib wrap precise trap 
dffr dffr_pib_wrap_trap_nq_g (
 
dffr_s dffr_pib_wrap_trap_nq_g (
 
   .din (pib_wrap_trap_m),
 
   .din (pib_wrap_trap_m),
 
   .q   (pib_wrap_trap_nq_g),
 
   .q   (pib_wrap_trap_nq_g),
 
   .rst (local_rst),
 
   .rst (local_rst),
 
   .clk (clk),
 
   .clk (clk),
 
   .se  (se),
 
   .se  (se),
 
   .si  (),
 
   `SIMPLY_RISC_SCANIN,
 
   .so  ()
 
   .so  ()
 
);
 
);
 
 
 
 
 
// modified for bug 4916
 
// modified for bug 4916
 
assign pib_wrap_trap_g =
 
assign pib_wrap_trap_g =
 
           pib_wrap_trap_nq_g & ~lsu_tlu_defr_trp_taken_g;
 
           pib_wrap_trap_nq_g & ~lsu_tlu_defr_trp_taken_g;
 
//
 
//
 
// modified for bug 2955
 
// modified for bug 2955
 
assign tlu_exu_priv_trap_m =
 
assign tlu_exu_priv_trap_m =
 
           exu_pib_priv_act_trap_m | exu_tick_npt_priv_act_m |
 
           exu_pib_priv_act_trap_m | exu_tick_npt_priv_act_m |
 
           (|tlz_exu_trap_m[4-1:0]) | tlu_pich_wrap_flg_m |
 
           (|tlz_exu_trap_m[`TLU_THRD_NUM-1:0]) | tlu_pich_wrap_flg_m |
 
           tlu_picl_wrap_flg_m;
 
           tlu_picl_wrap_flg_m;
 
// 
// 
// illegal instruction from ffu
 
// illegal instruction from ffu
 
dffr dffr_ffu_ill_inst_uf_g (
 
dffr_s dffr_ffu_ill_inst_uf_g (
 
   .din (ffu_tlu_ill_inst_m),
 
   .din (ffu_tlu_ill_inst_m),
 
   .q   (ffu_ill_inst_uf_g),
 
   .q   (ffu_ill_inst_uf_g),
 
   .rst (local_rst),
 
   .rst (local_rst),
 
   .clk (clk),
 
   .clk (clk),
 
   .se  (se),
 
   .se  (se),
 
   .si  (),
 
   `SIMPLY_RISC_SCANIN,
 
   .so  ()
 
   .so  ()
 
);
 
);
 
 
 
 
 
assign ffu_ill_inst_g = ffu_ill_inst_uf_g & ~inst_ifu_flush_w;
 
assign ffu_ill_inst_g = ffu_ill_inst_uf_g & ~inst_ifu_flush_w;
 
/*
 
/*
 
dffr dffr_lsu_ill_inst_uf_g (
 
dffr_s dffr_lsu_ill_inst_uf_g (
 
   .din (lsu_tlu_ill_inst_m),
 
   .din (lsu_tlu_ill_inst_m),
 
   .q   (lsu_ill_inst_uf_g),
 
   .q   (lsu_ill_inst_uf_g),
 
   .rst (local_rst),
 
   .rst (local_rst),
 
   .clk (clk),
 
   .clk (clk),
 
   .se  (se),
 
   .se  (se),
 
   .si  (),
 
   `SIMPLY_RISC_SCANIN,
 
   .so  ()
 
   .so  ()
 
);
 
);
 
 
 
 
 
assign lsu_ill_inst_g = lsu_ill_inst_uf_g & ~inst_ifu_flush_w;
 
assign lsu_ill_inst_g = lsu_ill_inst_uf_g & ~inst_ifu_flush_w;
 
//
 
//
 
*/
 
*/
 
// added for bug 4074 and modified for bug 4715
 
// added for bug 4074 and modified for bug 4715
 
/*
 
/*
 
dffr dffr_lsu_tlu_defr_trp_taken_w2 (
 
dffr_s dffr_lsu_tlu_defr_trp_taken_w2 (
 
   .din (lsu_tlu_defr_trp_taken_g),
 
   .din (lsu_tlu_defr_trp_taken_g),
 
   .q   (lsu_tlu_defr_trp_taken_w2),
 
   .q   (lsu_tlu_defr_trp_taken_w2),
 
   .rst (local_rst),
 
   .rst (local_rst),
 
   .clk (clk),
 
   .clk (clk),
 
   .se  (se),
 
   .se  (se),
 
   .si  (),
 
   `SIMPLY_RISC_SCANIN,
 
   .so  ()
 
   .so  ()
 
);
 
);
 
*/
 
*/
 
 
 
 
 
assign lsu_defr_trp_taken_w2[0] = lsu_defr_trap_w2 & thread0_wsel_w2;
 
assign lsu_defr_trp_taken_w2[0] = lsu_defr_trap_w2 & thread0_wsel_w2;
Line 3164... Line 2771... 
 
 
 
 
assign local_lsu_async_ttype_vld_w = lsu_tlu_async_ttype_vld_g;
 
assign local_lsu_async_ttype_vld_w = lsu_tlu_async_ttype_vld_g;
 
//
 
//
 
// modified for bug 4443 and 4561
 
// modified for bug 4443 and 4561
 
// added for timing
 
// added for timing
 
dffr dffr_lsu_defr_trap_w2 (
 
dffr_s dffr_lsu_defr_trap_w2 (
 
   .din (lsu_defr_trap_g),
 
   .din (lsu_defr_trap_g),
 
   .q   (lsu_defr_trap_w2),
 
   .q   (lsu_defr_trap_w2),
 
   .rst (local_rst),
 
   .rst (local_rst),
 
   .clk (clk),
 
   .clk (clk),
 
   .se  (se),
 
   .se  (se),
 
   .si  (),
 
   `SIMPLY_RISC_SCANIN,
 
   .so  ()
 
   .so  ()
 
);
 
);
 
//
 
//
 
// privilege action trap of the PIB registers
 
// privilege action trap of the PIB registers
 
dffr dffr_pib_priv_act_trap_g (
 
dffr_s dffr_pib_priv_act_trap_g (
 
   .din (pib_priv_act_early_trap_m),
 
   .din (pib_priv_act_early_trap_m),
 
   .q   (pib_priv_act_trap_uf_g),
 
   .q   (pib_priv_act_trap_uf_g),
 
   .rst (local_rst),
 
   .rst (local_rst),
 
   .clk (clk),
 
   .clk (clk),
 
   .se  (se),
 
   .se  (se),
 
   .si  (),
 
   `SIMPLY_RISC_SCANIN,
 
   .so  ()
 
   .so  ()
 
);
 
);
 
//
 
//
 
// added for bug 2133
 
// added for bug 2133
 
assign pib_priv_act_trap_g = pib_priv_act_trap_uf_g & ~inst_ifu_flush_w;
 
assign pib_priv_act_trap_g = pib_priv_act_trap_uf_g & ~inst_ifu_flush_w;
Line 3208... Line 2815... 
            lsu_ttype_vld_w | early_dside_trap_g;
 
            lsu_ttype_vld_w | early_dside_trap_g;
 
//
 
//
 
// The sync ttype is being recoded for timing
 
// The sync ttype is being recoded for timing
 
// Merge with lsu traps.
 
// Merge with lsu traps.
 
//
 
//
 
mux2ds #(9) mx_local_sync_ttype (
 
mux2ds #(`TSA_TTYPE_WIDTH) mx_local_sync_ttype (
 
    .in0  (9'h008),
 
    .in0  (`INST_ACC_EXC),
 
        .in1  (9'h030),
 
        .in1  (`DATA_ACC_EXC),
 
    .sel0 (va_oor_inst_acc_excp_g),
 
    .sel0 (va_oor_inst_acc_excp_g),
 
    .sel1 (~va_oor_inst_acc_excp_g),
 
    .sel1 (~va_oor_inst_acc_excp_g),
 
    .dout (local_sync_ttype_g[9-1:0])
 
    .dout (local_sync_ttype_g[`TSA_TTYPE_WIDTH-1:0])
 
);
 
);
 
 
 
 
 
// Need 9b comparator.
 
// Need 9b comparator.
 
// assign dside_higher_priority = (dside_sync_ttype_g[8:0] > exu_ttype_g[8:0]);
 
// assign dside_higher_priority = (dside_sync_ttype_g[8:0] > exu_ttype_g[8:0]);
 
assign local_higher_ttype_flg =
 
assign local_higher_ttype_flg =
 
           (local_sync_ttype_g[9-1:0] >
 
           (local_sync_ttype_g[`TSA_TTYPE_WIDTH-1:0] >
 
            exu_ttype_g[9-1:0]);
 
            exu_ttype_g[`TSA_TTYPE_WIDTH-1:0]);
 
 
 
 
 
// added for bug 3977
 
// added for bug 3977
 
dffr dffr_exu_ue_trap_g (
 
dffr_s dffr_exu_ue_trap_g (
 
   .din (exu_tlu_ue_trap_m),
 
   .din (exu_tlu_ue_trap_m),
 
   .q   (exu_ue_trap_g),
 
   .q   (exu_ue_trap_g),
 
   .rst (local_rst),
 
   .rst (local_rst),
 
   .clk (clk),
 
   .clk (clk),
 
   .se  (se),
 
   .se  (se),
 
   .si  (),
 
   `SIMPLY_RISC_SCANIN,
 
   .so  ()
 
   .so  ()
 
);
 
);
 
assign exu_higher_pri_g =
 
assign exu_higher_pri_g =
 
           exu_ue_trap_g & exu_ttype_vld_g & ~immu_miss_g;
 
           exu_ue_trap_g & exu_ttype_vld_g & ~immu_miss_g;
 
 
 
 
 
// Is the prioritization needed or is this handled among the units themselves ?
 
// Is the prioritization needed or is this handled among the units themselves ?
 
// modified for bug 3977
 
// modified for bug 3977
 
assign  priority_trap_sel0 =
 
assign  priority_trap_sel0 =
 
            ifu_ttype_vld_g & ~((|tlz_trap_g[4-1:0]) |
 
            ifu_ttype_vld_g & ~((|tlz_trap_g[`TLU_THRD_NUM-1:0]) |
 
            lsu_defr_trap_g | exu_higher_pri_g);
 
            lsu_defr_trap_g | exu_higher_pri_g);
 
//
 
//
 
// modified for support to lsu deferred traps
 
// modified for support to lsu deferred traps
 
// modified for bug 3977
 
// modified for bug 3977
 
assign  priority_trap_sel1 =
 
assign  priority_trap_sel1 =
 
            ~((|tlz_trap_g[4-1:0]) | lsu_defr_trap_g) &
 
            ~((|tlz_trap_g[`TLU_THRD_NUM-1:0]) | lsu_defr_trap_g) &
 
            ~(ifu_ttype_vld_g & ~exu_higher_pri_g) &
 
            ~(ifu_ttype_vld_g & ~exu_higher_pri_g) &
 
             ((exu_ttype_vld_g & ~early_dside_trap_g) |
 
             ((exu_ttype_vld_g & ~early_dside_trap_g) |
 
                         ((exu_ttype_vld_g &  early_dside_trap_g) & ~local_higher_ttype_flg));
 
                         ((exu_ttype_vld_g &  early_dside_trap_g) & ~local_higher_ttype_flg));
 
// 
// 
// modified for bug 3634
 
// modified for bug 3634
Line 3270... Line 2877... 
);
 
);
 
*/
 
*/
 
//
 
//
 
// modified for bug 3634
 
// modified for bug 3634
 
// modified for bug 3977
 
// modified for bug 3977
 
mux3ds #(9) mx_early_sync_ttype (
 
mux3ds #(`TSA_TTYPE_WIDTH) mx_early_sync_ttype (
 
//     .in0    ({2'b00,`TLZ_TRAP}),
 
//     .in0    ({2'b00,`TLZ_TRAP}),
 
    .in0    (ifu_ttype_g[8:0]),
 
    .in0    (ifu_ttype_g[8:0]),
 
        .in1    (exu_ttype_g[8:0]),
 
        .in1    (exu_ttype_g[8:0]),
 
        .in2    (local_sync_ttype_g[8:0]),
 
        .in2    (local_sync_ttype_g[8:0]),
 
    .sel0   (priority_trap_sel0),
 
    .sel0   (priority_trap_sel0),
 
        .sel1   (priority_trap_sel1),
 
        .sel1   (priority_trap_sel1),
 
        .sel2   (priority_trap_sel2),
 
        .sel2   (priority_trap_sel2),
 
    .dout   (early_sync_ttype_g[9-1:0])
 
    .dout   (early_sync_ttype_g[`TSA_TTYPE_WIDTH-1:0])
 
);
 
);
 
//
 
//
 
// added for timing 
// added for timing 
dff #(9) dff_early_sync_ttype_w2 (
 
dff_s #(`TSA_TTYPE_WIDTH) dff_early_sync_ttype_w2 (
 
    .din (early_sync_ttype_g[9-1:0]),
 
    .din (early_sync_ttype_g[`TSA_TTYPE_WIDTH-1:0]),
 
    .q   (early_sync_ttype_w2[9-1:0]),
 
    .q   (early_sync_ttype_w2[`TSA_TTYPE_WIDTH-1:0]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
//
 
//
 
// Now pend Div and Spill/Fill traps if necessary. These traps are always pended
 
// Now pend Div and Spill/Fill traps if necessary. These traps are always pended
 
// even if there is no concurrent synchronous trap. They are pended by thread.
 
// even if there is no concurrent synchronous trap. They are pended by thread.
 
// Include fp traps
 
// Include fp traps
 
// modified for bug 4857
 
// modified for bug 4857
 
assign  sync_trap_taken_g =
 
assign  sync_trap_taken_g =
 
        ((ifu_ttype_vld_g | exu_ttype_vld_g | lsu_tlu_ttype_vld_m2 | early_dside_trap_g |
 
        ((ifu_ttype_vld_g | exu_ttype_vld_g | lsu_tlu_ttype_vld_m2 | early_dside_trap_g |
 
     (|tlz_trap_g[4-1:0]) | pib_wrap_trap_g) & inst_vld_g) |
 
     (|tlz_trap_g[`TLU_THRD_NUM-1:0]) | pib_wrap_trap_g) & inst_vld_g) |
 
      intrpt_taken | swint_taken | lsu_defr_trap_g;
 
      intrpt_taken | swint_taken | lsu_defr_trap_g;
 
     // (|tlz_trap_g[`TLU_THRD_NUM-1:0])) & inst_vld_g) | intrpt_taken | swint_taken |
 
     // (|tlz_trap_g[`TLU_THRD_NUM-1:0])) & inst_vld_g) | intrpt_taken | swint_taken |
 
     //  lsu_defr_trap_g | pib_wrap_trap_g; 
     //  lsu_defr_trap_g | pib_wrap_trap_g; 
// 
// 
// added for timing
 
// added for timing
 
dff dff_sync_trap_taken_w2 (
 
dff_s dff_sync_trap_taken_w2 (
 
    .din (sync_trap_taken_g),
 
    .din (sync_trap_taken_g),
 
        .q   (sync_trap_taken_w2),
 
        .q   (sync_trap_taken_w2),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
//
 
//
 
// added for timing fix 
// added for timing fix 
// modified for bug 3653, bug 4758 and bug 5169
 
// modified for bug 3653, bug 4758 and bug 5169
 
assign  sync_trap_taken_m =
 
assign  sync_trap_taken_m =
 
         (exu_tlu_va_oor_jl_ret_m | exu_tlu_ttype_vld_m |
 
         (exu_tlu_va_oor_jl_ret_m | exu_tlu_ttype_vld_m |
 
      ifu_ttype_early_vld_m | (|tlz_trap_m[4-1:0]) | true_hscpd_dacc_excpt_m |
 
      ifu_ttype_early_vld_m | (|tlz_trap_m[`TLU_THRD_NUM-1:0]) | true_hscpd_dacc_excpt_m |
 
      true_qtail_dacc_excpt_m | dmmu_va_oor_m | exu_tlu_va_oor_jl_ret_m |
 
      true_qtail_dacc_excpt_m | dmmu_va_oor_m | exu_tlu_va_oor_jl_ret_m |
 
      pib_wrap_trap_m | ifu_swint_m | ifu_hwint_m | ifu_rstint_m) & inst_vld_m;
 
      pib_wrap_trap_m | ifu_swint_m | ifu_hwint_m | ifu_rstint_m) & inst_vld_m;
 
/*
 
/*
 
assign  sync_trap_taken_m =
 
assign  sync_trap_taken_m =
 
        ((exu_tlu_va_oor_jl_ret_m | exu_tlu_ttype_vld_m |
 
        ((exu_tlu_va_oor_jl_ret_m | exu_tlu_ttype_vld_m |
Line 3343... Line 2950... 
assign spill_thrd1 = ~exu_tlu_spill_tid[1] &  exu_tlu_spill_tid[0];
 
assign spill_thrd1 = ~exu_tlu_spill_tid[1] &  exu_tlu_spill_tid[0];
 
assign spill_thrd2 =  exu_tlu_spill_tid[1] & ~exu_tlu_spill_tid[0];
 
assign spill_thrd2 =  exu_tlu_spill_tid[1] & ~exu_tlu_spill_tid[0];
 
assign spill_thrd3 =  exu_tlu_spill_tid[1] &  exu_tlu_spill_tid[0];
 
assign spill_thrd3 =  exu_tlu_spill_tid[1] &  exu_tlu_spill_tid[0];
 
// 
// 
// added for bug 3499
 
// added for bug 3499
 
dff #(4) dff_cwp_en_thrd_reset (
 
dff_s #(`TLU_THRD_NUM) dff_cwp_en_thrd_reset (
 
    .din ({pend_to_thrd3_reset, pend_to_thrd2_reset,
 
    .din ({pend_to_thrd3_reset, pend_to_thrd2_reset,
 
           pend_to_thrd1_reset, pend_to_thrd0_reset}),
 
           pend_to_thrd1_reset, pend_to_thrd0_reset}),
 
    .q   (cwp_en_thrd_reset[4-1:0]),
 
    .q   (cwp_en_thrd_reset[`TLU_THRD_NUM-1:0]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dffre dffre_trap_cwp0_enb (
 
dffre_s dffre_trap_cwp0_enb (
 
    .din (spill_thrd0),
 
    .din (spill_thrd0),
 
    .q   (trap_cwp_enb[0]),
 
    .q   (trap_cwp_enb[0]),
 
    .rst (cwp_en_thrd_reset[0]),
 
    .rst (cwp_en_thrd_reset[0]),
 
    .en  (exu_tlu_spill & spill_thrd0),
 
    .en  (exu_tlu_spill & spill_thrd0),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dffre dffre_trap_cwp1_enb (
 
dffre_s dffre_trap_cwp1_enb (
 
    .din (spill_thrd1),
 
    .din (spill_thrd1),
 
    .q   (trap_cwp_enb[1]),
 
    .q   (trap_cwp_enb[1]),
 
    .rst (cwp_en_thrd_reset[1]),
 
    .rst (cwp_en_thrd_reset[1]),
 
    .en  (exu_tlu_spill & spill_thrd1),
 
    .en  (exu_tlu_spill & spill_thrd1),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dffre dffre_trap_cwp2_enb (
 
dffre_s dffre_trap_cwp2_enb (
 
    .din (spill_thrd2),
 
    .din (spill_thrd2),
 
    .q   (trap_cwp_enb[2]),
 
    .q   (trap_cwp_enb[2]),
 
    .rst (cwp_en_thrd_reset[2]),
 
    .rst (cwp_en_thrd_reset[2]),
 
    .en  (exu_tlu_spill & spill_thrd2),
 
    .en  (exu_tlu_spill & spill_thrd2),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dffre dffre_trap_cwp3_enb (
 
dffre_s dffre_trap_cwp3_enb (
 
    .din (spill_thrd3),
 
    .din (spill_thrd3),
 
    .q   (trap_cwp_enb[3]),
 
    .q   (trap_cwp_enb[3]),
 
    .rst (cwp_en_thrd_reset[3]),
 
    .rst (cwp_en_thrd_reset[3]),
 
    .en  (exu_tlu_spill & spill_thrd3),
 
    .en  (exu_tlu_spill & spill_thrd3),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
assign tlu_trap_cwp_en[4-1:0] = ~(trap_cwp_enb[4-1:0]);
 
assign tlu_trap_cwp_en[`TLU_THRD_NUM-1:0] = ~(trap_cwp_enb[`TLU_THRD_NUM-1:0]);
 
 
 
 
 
//
 
//
 
// added for asynchronize dmmu traps (correctable parity error)
 
// added for asynchronize dmmu traps (correctable parity error)
 
assign dmmu_async_thrd0 = ~lsu_tlu_async_tid_g[1] & ~lsu_tlu_async_tid_g[0];
 
assign dmmu_async_thrd0 = ~lsu_tlu_async_tid_g[1] & ~lsu_tlu_async_tid_g[0];
 
assign dmmu_async_thrd1 = ~lsu_tlu_async_tid_g[1] &  lsu_tlu_async_tid_g[0];
 
assign dmmu_async_thrd1 = ~lsu_tlu_async_tid_g[1] &  lsu_tlu_async_tid_g[0];
Line 3420... Line 3027... 
           local_lsu_async_ttype_vld_w & dmmu_async_thrd2 & ~lsu_defr_trp_taken_w2[2];
 
           local_lsu_async_ttype_vld_w & dmmu_async_thrd2 & ~lsu_defr_trp_taken_w2[2];
 
assign lsu_async_vld_en_g[3] =
 
assign lsu_async_vld_en_g[3] =
 
//           local_lsu_async_ttype_vld_w & dmmu_async_thrd3 & ~lsu_tlu_defr_trp_taken_g;
 
//           local_lsu_async_ttype_vld_w & dmmu_async_thrd3 & ~lsu_tlu_defr_trp_taken_g;
 
           local_lsu_async_ttype_vld_w & dmmu_async_thrd3 & ~lsu_defr_trp_taken_w2[3];
 
           local_lsu_async_ttype_vld_w & dmmu_async_thrd3 & ~lsu_defr_trp_taken_w2[3];
 
//
 
//
 
dffre dffre_lsu_async_vld_en_w2_0 (
 
dffre_s dffre_lsu_async_vld_en_w2_0 (
 
    .din (lsu_async_vld_en_g[0]),
 
    .din (lsu_async_vld_en_g[0]),
 
    .q   (lsu_async_vld_en_w2[0]),
 
    .q   (lsu_async_vld_en_w2[0]),
 
    .rst (pend_to_thrd0_reset),
 
    .rst (pend_to_thrd0_reset),
 
    .en  (lsu_async_vld_en_g[0]),
 
    .en  (lsu_async_vld_en_g[0]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
dffre dffre_lsu_async_vld_en_w2_1 (
 
dffre_s dffre_lsu_async_vld_en_w2_1 (
 
    .din (lsu_async_vld_en_g[1]),
 
    .din (lsu_async_vld_en_g[1]),
 
    .q   (lsu_async_vld_en_w2[1]),
 
    .q   (lsu_async_vld_en_w2[1]),
 
    .rst (pend_to_thrd1_reset),
 
    .rst (pend_to_thrd1_reset),
 
    .en  (lsu_async_vld_en_g[1]),
 
    .en  (lsu_async_vld_en_g[1]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
dffre dffre_lsu_async_vld_en_w2_2 (
 
dffre_s dffre_lsu_async_vld_en_w2_2 (
 
    .din (lsu_async_vld_en_g[2]),
 
    .din (lsu_async_vld_en_g[2]),
 
    .q   (lsu_async_vld_en_w2[2]),
 
    .q   (lsu_async_vld_en_w2[2]),
 
    .rst (pend_to_thrd2_reset),
 
    .rst (pend_to_thrd2_reset),
 
    .en  (lsu_async_vld_en_g[2]),
 
    .en  (lsu_async_vld_en_g[2]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
dffre dffre_lsu_async_vld_en_w2_3 (
 
dffre_s dffre_lsu_async_vld_en_w2_3 (
 
    .din (lsu_async_vld_en_g[3]),
 
    .din (lsu_async_vld_en_g[3]),
 
    .q   (lsu_async_vld_en_w2[3]),
 
    .q   (lsu_async_vld_en_w2[3]),
 
    .rst (pend_to_thrd3_reset),
 
    .rst (pend_to_thrd3_reset),
 
    .en  (lsu_async_vld_en_g[3]),
 
    .en  (lsu_async_vld_en_g[3]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
//
 
//
 
// assign trap type base on information send
 
// assign trap type base on information send
 
assign dmmu_async_ttype[9-1:0] =
 
assign dmmu_async_ttype[`TSA_TTYPE_WIDTH-1:0] =
 
           {2'b0, lsu_tlu_async_ttype_g[6:0]};
 
           {2'b0, lsu_tlu_async_ttype_g[6:0]};
 
// 
// 
// derived the spill ttype
 
// derived the spill ttype
 
assign exu_spill_ttype[9-1:0] =
 
assign exu_spill_ttype[`TSA_TTYPE_WIDTH-1:0] =
 
           {3'b010,exu_tlu_spill_other,exu_tlu_spill_wtype[2:0], 2'b00};
 
           {3'b010,exu_tlu_spill_other,exu_tlu_spill_wtype[2:0], 2'b00};
 
//
 
//
 
// derived ffu_asynchronous ttype
 
// derived ffu_asynchronous ttype
 
// modified for bug 4084 - new ffu asynchronous trap type: 0x29
 
// modified for bug 4084 - new ffu asynchronous trap type: 0x29
 
assign ffu_async_ttype[9-1:0] =
 
assign ffu_async_ttype[`TSA_TTYPE_WIDTH-1:0] =
 
           (ffu_tlu_trap_ue) ? 9'h029:
 
           (ffu_tlu_trap_ue) ? 9'h029:
 
               ({7'b0001000, ffu_tlu_trap_other, ffu_tlu_trap_ieee754});
 
               ({7'b0001000, ffu_tlu_trap_other, ffu_tlu_trap_ieee754});
 
//
 
//
 
//
 
//
 
// modified for bug 4084 - new ffu_tlu_trap_ue 
// modified for bug 4084 - new ffu_tlu_trap_ue 
assign pend_ttype0[9-1:0] =
 
assign pend_ttype0[`TSA_TTYPE_WIDTH-1:0] =
 
                (exu_tlu_spill & spill_thrd0) ?
 
                (exu_tlu_spill & spill_thrd0) ?
 
         exu_spill_ttype[9-1:0] :
 
         exu_spill_ttype[`TSA_TTYPE_WIDTH-1:0] :
 
                (((ffu_tlu_trap_other | ffu_tlu_trap_ieee754 | ffu_tlu_trap_ue) & fp_trap_thrd0) ?
 
                (((ffu_tlu_trap_other | ffu_tlu_trap_ieee754 | ffu_tlu_trap_ue) & fp_trap_thrd0) ?
 
           ffu_async_ttype[9-1:0] :
 
           ffu_async_ttype[`TSA_TTYPE_WIDTH-1:0] :
 
           dmmu_async_ttype[9-1:0]);
 
           dmmu_async_ttype[`TSA_TTYPE_WIDTH-1:0]);
 
 
 
 
 
// always flop if selected for thread.
 
// always flop if selected for thread.
 
// THREAD0
 
// THREAD0
 
// added support for dmmu_async_traps
 
// added support for dmmu_async_traps
 
// modified for bug 4084 - new ffu_tlu_trap_ue 
// modified for bug 4084 - new ffu_tlu_trap_ue
Line 3522... Line 3129... 
// modified for bug 3827
 
// modified for bug 3827
 
assign pending_thrd0_event_taken =
 
assign pending_thrd0_event_taken =
 
            pending_trap_sel[0] & ~(sync_trap_taken_g | dnrtry_inst_g |
 
            pending_trap_sel[0] & ~(sync_trap_taken_g | dnrtry_inst_g |
 
            tsa_wr_tid_sel_g | ifu_thrd_flush_w[0] | (tlu_gl_rw_g & wsr_inst_g));
 
            tsa_wr_tid_sel_g | ifu_thrd_flush_w[0] | (tlu_gl_rw_g & wsr_inst_g));
 
 
 
 
 
dffre #(12) dffre_pendthrd0 (
 
dffre_s #(12) dffre_pendthrd0 (
 
    .din ({pend_to_thrd0_en,pend_ttype0[8:0],cwp_cmplt0,exu_tlu_cwp_retry}),
 
    .din ({pend_to_thrd0_en,pend_ttype0[8:0],cwp_cmplt0,exu_tlu_cwp_retry}),
 
        .q   ({pending_trap0,pending_ttype0[8:0],cwp_cmplt0_pending,cwp_retry0}),
 
        .q   ({pending_trap0,pending_ttype0[8:0],cwp_cmplt0_pending,cwp_retry0}),
 
    .rst (pend_to_thrd0_reset),
 
    .rst (pend_to_thrd0_reset),
 
    .en  (pend_to_thrd0_en),
 
    .en  (pend_to_thrd0_en),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
// THREAD1
 
// THREAD1
 
// added support for dmmu_async_traps
 
// added support for dmmu_async_traps
 
// modified for bug 4084 - new ffu_tlu_trap_ue 
// modified for bug 4084 - new ffu_tlu_trap_ue
Line 3560... Line 3167... 
            pending_trap_sel[1] & ~(sync_trap_taken_g | dnrtry_inst_g |
 
            pending_trap_sel[1] & ~(sync_trap_taken_g | dnrtry_inst_g |
 
            tsa_wr_tid_sel_g | ifu_thrd_flush_w[1] | (tlu_gl_rw_g & wsr_inst_g));
 
            tsa_wr_tid_sel_g | ifu_thrd_flush_w[1] | (tlu_gl_rw_g & wsr_inst_g));
 
 
 
 
 
//
 
//
 
// modified for bug 4084 - new ffu_tlu_trap_ue 
// modified for bug 4084 - new ffu_tlu_trap_ue 
assign pend_ttype1[9-1:0] =
 
assign pend_ttype1[`TSA_TTYPE_WIDTH-1:0] =
 
                (exu_tlu_spill & spill_thrd1) ?
 
                (exu_tlu_spill & spill_thrd1) ?
 
         exu_spill_ttype[9-1:0] :
 
         exu_spill_ttype[`TSA_TTYPE_WIDTH-1:0] :
 
                (((ffu_tlu_trap_other | ffu_tlu_trap_ieee754 | ffu_tlu_trap_ue) & fp_trap_thrd1) ?
 
                (((ffu_tlu_trap_other | ffu_tlu_trap_ieee754 | ffu_tlu_trap_ue) & fp_trap_thrd1) ?
 
           ffu_async_ttype[9-1:0] :
 
           ffu_async_ttype[`TSA_TTYPE_WIDTH-1:0] :
 
           dmmu_async_ttype[9-1:0]);
 
           dmmu_async_ttype[`TSA_TTYPE_WIDTH-1:0]);
 
 
 
 
 
dffre #(12) dffre_pendthrd1 (
 
dffre_s #(12) dffre_pendthrd1 (
 
    .din ({pend_to_thrd1_en,pend_ttype1[8:0],cwp_cmplt1,exu_tlu_cwp_retry}),
 
    .din ({pend_to_thrd1_en,pend_ttype1[8:0],cwp_cmplt1,exu_tlu_cwp_retry}),
 
        .q   ({pending_trap1,pending_ttype1[8:0],cwp_cmplt1_pending,cwp_retry1}),
 
        .q   ({pending_trap1,pending_ttype1[8:0],cwp_cmplt1_pending,cwp_retry1}),
 
    .rst (pend_to_thrd1_reset),
 
    .rst (pend_to_thrd1_reset),
 
    .en  (pend_to_thrd1_en),
 
    .en  (pend_to_thrd1_en),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
// THREAD2
 
// THREAD2
 
// added support for dmmu_async_traps
 
// added support for dmmu_async_traps
Line 3606... Line 3213... 
            pending_trap_sel[2] & ~(sync_trap_taken_g | dnrtry_inst_g |
 
            pending_trap_sel[2] & ~(sync_trap_taken_g | dnrtry_inst_g |
 
            tsa_wr_tid_sel_g | ifu_thrd_flush_w[2] | (tlu_gl_rw_g & wsr_inst_g));
 
            tsa_wr_tid_sel_g | ifu_thrd_flush_w[2] | (tlu_gl_rw_g & wsr_inst_g));
 
 
 
 
 
//
 
//
 
// modified for bug 4084 - new ffu_tlu_trap_ue
 
// modified for bug 4084 - new ffu_tlu_trap_ue
 
assign pend_ttype2[9-1:0] =
 
assign pend_ttype2[`TSA_TTYPE_WIDTH-1:0] =
 
                (exu_tlu_spill & spill_thrd2) ?
 
                (exu_tlu_spill & spill_thrd2) ?
 
         exu_spill_ttype[9-1:0] :
 
         exu_spill_ttype[`TSA_TTYPE_WIDTH-1:0] :
 
                (((ffu_tlu_trap_other | ffu_tlu_trap_ieee754 | ffu_tlu_trap_ue) & fp_trap_thrd2) ?
 
                (((ffu_tlu_trap_other | ffu_tlu_trap_ieee754 | ffu_tlu_trap_ue) & fp_trap_thrd2) ?
 
           ffu_async_ttype[9-1:0] :
 
           ffu_async_ttype[`TSA_TTYPE_WIDTH-1:0] :
 
           dmmu_async_ttype[9-1:0]);
 
           dmmu_async_ttype[`TSA_TTYPE_WIDTH-1:0]);
 
 
 
 
 
dffre #(12) dffre_pendthrd2 (
 
dffre_s #(12) dffre_pendthrd2 (
 
    .din ({pend_to_thrd2_en,pend_ttype2[8:0],cwp_cmplt2,exu_tlu_cwp_retry}),
 
    .din ({pend_to_thrd2_en,pend_ttype2[8:0],cwp_cmplt2,exu_tlu_cwp_retry}),
 
        .q   ({pending_trap2,pending_ttype2[8:0],cwp_cmplt2_pending,cwp_retry2}),
 
        .q   ({pending_trap2,pending_ttype2[8:0],cwp_cmplt2_pending,cwp_retry2}),
 
    .rst (pend_to_thrd2_reset),
 
    .rst (pend_to_thrd2_reset),
 
    .en  (pend_to_thrd2_en),
 
    .en  (pend_to_thrd2_en),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
// THREAD3
 
// THREAD3
 
// added support for dmmu_async_traps
 
// added support for dmmu_async_traps
Line 3650... Line 3257... 
assign pending_thrd3_event_taken =
 
assign pending_thrd3_event_taken =
 
            pending_trap_sel[3] & ~(sync_trap_taken_g | dnrtry_inst_g |
 
            pending_trap_sel[3] & ~(sync_trap_taken_g | dnrtry_inst_g |
 
            tsa_wr_tid_sel_g | ifu_thrd_flush_w[3] | (tlu_gl_rw_g & wsr_inst_g));
 
            tsa_wr_tid_sel_g | ifu_thrd_flush_w[3] | (tlu_gl_rw_g & wsr_inst_g));
 
 
 
 
 
//
 
//
 
assign pend_ttype3[9-1:0] =
 
assign pend_ttype3[`TSA_TTYPE_WIDTH-1:0] =
 
                (exu_tlu_spill & spill_thrd3) ?
 
                (exu_tlu_spill & spill_thrd3) ?
 
         exu_spill_ttype[9-1:0] :
 
         exu_spill_ttype[`TSA_TTYPE_WIDTH-1:0] :
 
                (((ffu_tlu_trap_other | ffu_tlu_trap_ieee754 | ffu_tlu_trap_ue) & fp_trap_thrd3) ?
 
                (((ffu_tlu_trap_other | ffu_tlu_trap_ieee754 | ffu_tlu_trap_ue) & fp_trap_thrd3) ?
 
           ffu_async_ttype[9-1:0] :
 
           ffu_async_ttype[`TSA_TTYPE_WIDTH-1:0] :
 
           dmmu_async_ttype[9-1:0]);
 
           dmmu_async_ttype[`TSA_TTYPE_WIDTH-1:0]);
 
//
 
//
 
dffre #(12) dffre_pendthrd3 (
 
dffre_s #(12) dffre_pendthrd3 (
 
    .din ({pend_to_thrd3_en,pend_ttype3[8:0],cwp_cmplt3,exu_tlu_cwp_retry}),
 
    .din ({pend_to_thrd3_en,pend_ttype3[8:0],cwp_cmplt3,exu_tlu_cwp_retry}),
 
        .q   ({pending_trap3,pending_ttype3[8:0],cwp_cmplt3_pending,cwp_retry3}),
 
        .q   ({pending_trap3,pending_ttype3[8:0],cwp_cmplt3_pending,cwp_retry3}),
 
    .rst (pend_to_thrd3_reset),
 
    .rst (pend_to_thrd3_reset),
 
    .en  (pend_to_thrd3_en),
 
    .en  (pend_to_thrd3_en),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
//
 
//
 
// added for bug 5436 - Niagara 2.0
 
// added for bug 5436 - Niagara 2.0
 
//assign pich_cnt_hld_rst[`TLU_THRD_NUM-1:0] = 
//assign pich_cnt_hld_rst[`TLU_THRD_NUM-1:0] =
Line 3682... Line 3289... 
assign pich_cnt_hld_rst_g[3:0] =
 
assign pich_cnt_hld_rst_g[3:0] =
 
                        (thread_inst_vld_g[3:0] & {4{pic_cnt_en_w}}) &
 
                        (thread_inst_vld_g[3:0] & {4{pic_cnt_en_w}}) &
 
                        {4{~(lsu_ttype_vld_w | tlu_flush_all_w)}};
 
                        {4{~(lsu_ttype_vld_w | tlu_flush_all_w)}};
 
 
 
 
 
 
 
 
 
dff #(4) dff_pich_cnt_hld_rst_g (
 
dff_s #(4) dff_pich_cnt_hld_rst_g (
 
    .din (pich_cnt_hld_rst_g[3:0]),
 
    .din (pich_cnt_hld_rst_g[3:0]),
 
    .q   (pich_cnt_hld_rst_w2[3:0]),
 
    .q   (pich_cnt_hld_rst_w2[3:0]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
 
 
 
 
assign pend_pich_cnt_hld_early[3:0] = pend_pich_cnt_hld_q[3:0] & ~pich_cnt_hld_rst_w2[3:0];
 
assign pend_pich_cnt_hld_early[3:0] = pend_pich_cnt_hld_q[3:0] & ~pich_cnt_hld_rst_w2[3:0];
Line 3699... Line 3306... 
assign pend_pich_cnt_hld[3:0] = pend_pich_cnt_hld_early[3:0];
 
assign pend_pich_cnt_hld[3:0] = pend_pich_cnt_hld_early[3:0];
 
 
 
 
 
// following is used in pib_wrap_m logic as per bug5436(reopened 9/17/04).
 
// following is used in pib_wrap_m logic as per bug5436(reopened 9/17/04).
 
assign pend_pich_cnt_hld_noqual[3:0] = pend_pich_cnt_hld_q[3:0];
 
assign pend_pich_cnt_hld_noqual[3:0] = pend_pich_cnt_hld_q[3:0];
 
 
 
 
 
dffre dffre_pend_pich_cnt_adj_0 (
 
dffre_s dffre_pend_pich_cnt_adj_0 (
 
    .din (pend_pich_cnt_adj[0]),
 
    .din (pend_pich_cnt_adj[0]),
 
        .q   (pend_pich_cnt_hld_q[0]),
 
        .q   (pend_pich_cnt_hld_q[0]),
 
    .rst (local_rst | pich_cnt_hld_rst_w2[0]),
 
    .rst (local_rst | pich_cnt_hld_rst_w2[0]),
 
    .en  (pend_pich_cnt_adj[0]),
 
    .en  (pend_pich_cnt_adj[0]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dffre dffre_pend_pich_cnt_adj_1 (
 
dffre_s dffre_pend_pich_cnt_adj_1 (
 
    .din (pend_pich_cnt_adj[1]),
 
    .din (pend_pich_cnt_adj[1]),
 
        .q   (pend_pich_cnt_hld_q[1]),
 
        .q   (pend_pich_cnt_hld_q[1]),
 
    .rst (local_rst | pich_cnt_hld_rst_w2[1]),
 
    .rst (local_rst | pich_cnt_hld_rst_w2[1]),
 
    .en  (pend_pich_cnt_adj[1]),
 
    .en  (pend_pich_cnt_adj[1]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dffre dffre_pend_pich_cnt_adj_2 (
 
dffre_s dffre_pend_pich_cnt_adj_2 (
 
    .din (pend_pich_cnt_adj[2]),
 
    .din (pend_pich_cnt_adj[2]),
 
        .q   (pend_pich_cnt_hld_q[2]),
 
        .q   (pend_pich_cnt_hld_q[2]),
 
    .rst (local_rst | pich_cnt_hld_rst_w2[2]),
 
    .rst (local_rst | pich_cnt_hld_rst_w2[2]),
 
    .en  (pend_pich_cnt_adj[2]),
 
    .en  (pend_pich_cnt_adj[2]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dffre dffre_pend_pich_cnt_adj_3 (
 
dffre_s dffre_pend_pich_cnt_adj_3 (
 
    .din (pend_pich_cnt_adj[3]),
 
    .din (pend_pich_cnt_adj[3]),
 
        .q   (pend_pich_cnt_hld_q[3]),
 
        .q   (pend_pich_cnt_hld_q[3]),
 
    .rst (local_rst | pich_cnt_hld_rst_w2[3]),
 
    .rst (local_rst | pich_cnt_hld_rst_w2[3]),
 
    .en  (pend_pich_cnt_adj[3]),
 
    .en  (pend_pich_cnt_adj[3]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
 
 
 
 
assign  trap_taken_g =  thrd0_traps | thrd1_traps | thrd2_traps | thrd3_traps;
 
assign  trap_taken_g =  thrd0_traps | thrd1_traps | thrd2_traps | thrd3_traps;
 
// 
// 
// added for timing 
// added for timing 
dff dff_trap_taken_w2 (
 
dff_s dff_trap_taken_w2 (
 
    .din (trap_taken_g),
 
    .din (trap_taken_g),
 
    .q   (trap_taken_w2),
 
    .q   (trap_taken_w2),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
// Selection of traps should be round-robin.
 
// Selection of traps should be round-robin.
 
assign  trap_tid_g[1:0] =
 
assign  trap_tid_g[1:0] =
 
    // lsu_defr_trap_g ? thrid_w2[1:0] :
 
    // lsu_defr_trap_g ? thrid_w2[1:0] :
Line 3769... Line 3376... 
               pending_trap_sel[0] ? 2'b00 :
 
               pending_trap_sel[0] ? 2'b00 :
 
                       (pending_trap_sel[1] ? 2'b01 :
 
                       (pending_trap_sel[1] ? 2'b01 :
 
                               (pending_trap_sel[2] ? 2'b10 :
 
                               (pending_trap_sel[2] ? 2'b10 :
 
                        2'b11));
 
                        2'b11));
 
 
 
 
 
dff #(2) dff_pend_trap_tid_w2 (
 
dff_s #(2) dff_pend_trap_tid_w2 (
 
    .din (pend_trap_tid_g[1:0]),
 
    .din (pend_trap_tid_g[1:0]),
 
    .q   (pend_trap_tid_w2[1:0]),
 
    .q   (pend_trap_tid_w2[1:0]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
 
 
 
 
// Assume fixed priority for now. Should change to round-robin selection !!!
 
// Assume fixed priority for now. Should change to round-robin selection !!!
Line 3787... Line 3394... 
// modified to support lsu deferred traps - modified for timing
 
// modified to support lsu deferred traps - modified for timing
 
// modified for bug 4640 and 5127
 
// modified for bug 4640 and 5127
 
//
 
//
 
assign  reset_sel_g =
 
assign  reset_sel_g =
 
            rstint_g | (sir_inst_g & ~(lsu_defr_trap_g | pib_wrap_trap_g |
 
            rstint_g | (sir_inst_g & ~(lsu_defr_trap_g | pib_wrap_trap_g |
 
            (|tlz_trap_g[4-1:0]))) | rst_tri_en;
 
            (|tlz_trap_g[`TLU_THRD_NUM-1:0]))) | rst_tri_en;
 
            // rstint_g | (sir_inst_g & ~lsu_defr_trap_g) | rst_tri_en;
 
            // rstint_g | (sir_inst_g & ~lsu_defr_trap_g) | rst_tri_en;
 
//
 
//
 
// added for timing
 
// added for timing
 
dffr dffr_reset_sel_w2 (
 
dffr_s dffr_reset_sel_w2 (
 
   .din (reset_sel_g),
 
   .din (reset_sel_g),
 
   .q   (reset_sel_w2),
 
   .q   (reset_sel_w2),
 
   .rst (local_rst),
 
   .rst (local_rst),
 
   .clk (clk),
 
   .clk (clk),
 
   .se  (se),
 
   .se  (se),
 
   .si  (),
 
   `SIMPLY_RISC_SCANIN,
 
   .so  ()
 
   .so  ()
 
);
 
);
 
// 
// 
// modified for timing
 
// modified for timing
 
// assign       reset_defr_id_g[6:0] =
 
// assign       reset_defr_id_g[6:0] =
Line 3818... Line 3425... 
// modified for bug 3634 and timing
 
// modified for bug 3634 and timing
 
 
 
 
 
assign tba_ttype_sel_w2 =
 
assign tba_ttype_sel_w2 =
 
           final_ttype_sel_w2[0] | (hyper_wdr_trap_w2 & ~lsu_defr_trap_w2);
 
           final_ttype_sel_w2[0] | (hyper_wdr_trap_w2 & ~lsu_defr_trap_w2);
 
 
 
 
 
mux2ds #(9) mx_tba_ttype_w2 (
 
mux2ds #(`TSA_TTYPE_WIDTH) mx_tba_ttype_w2 (
 
    .sel0 (tba_ttype_sel_w2),
 
    .sel0 (tba_ttype_sel_w2),
 
    .sel1 (~tba_ttype_sel_w2),
 
    .sel1 (~tba_ttype_sel_w2),
 
    .in0  ({2'b0,rst_hwdr_ttype_w2[9-3:0]}),
 
    .in0  ({2'b0,rst_hwdr_ttype_w2[`TSA_TTYPE_WIDTH-3:0]}),
 
    .in1  (final_ttype_w2[9-1:0]),
 
    .in1  (final_ttype_w2[`TSA_TTYPE_WIDTH-1:0]),
 
    .dout (tba_ttype_w1[9-1:0])
 
    .dout (tba_ttype_w1[`TSA_TTYPE_WIDTH-1:0])
 
);
 
);
 
/*
 
/*
 
assign tba_ttype_sel_g[0] =
 
assign tba_ttype_sel_g[0] =
 
               (rstint_g | rst_tri_en | ((hwint_g | swint_g | hyper_wdr_trap |
 
               (rstint_g | rst_tri_en | ((hwint_g | swint_g | hyper_wdr_trap |
 
               (|tlz_trap_g[`TLU_THRD_NUM-1:0] | sir_inst_g) | pib_wrap_trap_g) &
 
               (|tlz_trap_g[`TLU_THRD_NUM-1:0] | sir_inst_g) | pib_wrap_trap_g) &
Line 3842... Line 3449... 
           ~(|tba_ttype_sel_g[1:0])) | (lsu_defr_trap_g & ~(rstint_g | rst_tri_en));
 
           ~(|tba_ttype_sel_g[1:0])) | (lsu_defr_trap_g & ~(rstint_g | rst_tri_en));
 
assign tba_ttype_sel_g[3] =
 
assign tba_ttype_sel_g[3] =
 
           ~(|tba_ttype_sel_g[2:0]);
 
           ~(|tba_ttype_sel_g[2:0]);
 
 
 
 
 
// added for timing
 
// added for timing
 
dffr #(4) dffr_tba_ttype_sel_w2 (
 
dffr_s #(4) dffr_tba_ttype_sel_w2 (
 
    .din (tba_ttype_sel_g[3:0]),
 
    .din (tba_ttype_sel_g[3:0]),
 
    .q   (tba_ttype_sel_w2[3:0]),
 
    .q   (tba_ttype_sel_w2[3:0]),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
//
 
//
 
mux4ds #(`TSA_TTYPE_WIDTH) mx_tba_ttype_w2 (
 
mux4ds #(`TSA_TTYPE_WIDTH) mx_tba_ttype_w2 (
 
    .sel0 (tba_ttype_sel_w2[0]),
 
    .sel0 (tba_ttype_sel_w2[0]),
Line 3864... Line 3471... 
    .in2  (adj_lsu_ttype_w2[`TSA_TTYPE_WIDTH-1:0]),
 
    .in2  (adj_lsu_ttype_w2[`TSA_TTYPE_WIDTH-1:0]),
 
    .in3  (pending_ttype_w2[`TSA_TTYPE_WIDTH-1:0]),
 
    .in3  (pending_ttype_w2[`TSA_TTYPE_WIDTH-1:0]),
 
    .dout (tba_ttype_w1[`TSA_TTYPE_WIDTH-1:0])
 
    .dout (tba_ttype_w1[`TSA_TTYPE_WIDTH-1:0])
 
);
 
);
 
 
 
 
 
dff #(`TSA_TTYPE_WIDTH) dff_tba_ttype_w1 (
 
dff_s #(`TSA_TTYPE_WIDTH) dff_tba_ttype_w1 (
 
    .din (tba_ttype_g[`TSA_TTYPE_WIDTH-1:0]),
 
    .din (tba_ttype_g[`TSA_TTYPE_WIDTH-1:0]),
 
    .q   (tba_ttype_w1[`TSA_TTYPE_WIDTH-1:0]),
 
    .q   (tba_ttype_w1[`TSA_TTYPE_WIDTH-1:0]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
*/
 
*/
 
//
 
//
 
// construct the final_ttype to be written into the trap stack 
// construct the final_ttype to be written into the trap stack 
// modified for bug 3634, 4640 and timing  
// modified for bug 3634, 4640 and timing  
assign final_ttype_sel_g[0] =
 
assign final_ttype_sel_g[0] =
 
            (rstint_g | rst_tri_en) | ((hwint_g | swint_g | sir_inst_g |
 
            (rstint_g | rst_tri_en) | ((hwint_g | swint_g | sir_inst_g |
 
            (|tlz_trap_g[4-1:0]) | pib_wrap_trap_g) & inst_vld_g &
 
            (|tlz_trap_g[`TLU_THRD_NUM-1:0]) | pib_wrap_trap_g) & inst_vld_g &
 
            ~lsu_defr_trap_g);
 
            ~lsu_defr_trap_g);
 
//             reset_sel_g | ((hwint_g | swint_g |
 
//             reset_sel_g | ((hwint_g | swint_g |
 
//             (|tlz_trap_g[`TLU_THRD_NUM-1:0]) | pib_wrap_trap_g) & inst_vld_g &
 
//             (|tlz_trap_g[`TLU_THRD_NUM-1:0]) | pib_wrap_trap_g) & inst_vld_g &
 
//             ~lsu_defr_trap_g);
 
//             ~lsu_defr_trap_g);
 
 
 
 
 
assign final_ttype_sel_g[1] =
 
assign final_ttype_sel_g[1] =
 
           (((ifu_ttype_vld_g | exu_ttype_vld_g | va_oor_inst_acc_excp_g) |
 
           (((ifu_ttype_vld_g | exu_ttype_vld_g | va_oor_inst_acc_excp_g) |
 
            (local_sync_trap_g & ~(lsu_tlu_priv_action_g | misalign_addr_ldst_atm_g))) &
 
            (local_sync_trap_g & ~(lsu_tlu_priv_action_g | misalign_addr_ldst_atm_g))) &
 
           ~(rstint_g | sir_inst_g  | hwint_g | swint_g | rst_tri_en | (|tlz_trap_g[4-1:0])) &
 
           ~(rstint_g | sir_inst_g  | hwint_g | swint_g | rst_tri_en | (|tlz_trap_g[`TLU_THRD_NUM-1:0])) &
 
             inst_vld_g) & ~lsu_defr_trap_g & ~pib_wrap_trap_g;
 
             inst_vld_g) & ~lsu_defr_trap_g & ~pib_wrap_trap_g;
 
assign final_ttype_sel_g[2] =
 
assign final_ttype_sel_g[2] =
 
           ((lsu_tlu_ttype_vld_m2 & inst_vld_g) | va_oor_data_acc_excp_g)  &
 
           ((lsu_tlu_ttype_vld_m2 & inst_vld_g) | va_oor_data_acc_excp_g)  &
 
           ~(|final_ttype_sel_g[1:0]) | (lsu_defr_trap_g & ~(rst_tri_en | rstint_g));
 
           ~(|final_ttype_sel_g[1:0]) | (lsu_defr_trap_g & ~(rst_tri_en | rstint_g));
 
assign final_ttype_sel_g[3] =
 
assign final_ttype_sel_g[3] =
 
           ~(|final_ttype_sel_g[2:0]);
 
           ~(|final_ttype_sel_g[2:0]);
 
//
 
//
 
// added for timing
 
// added for timing
 
dffr #(4) dffr_final_ttype_sel_w2 (
 
dffr_s #(4) dffr_final_ttype_sel_w2 (
 
    .din (final_ttype_sel_g[3:0]),
 
    .din (final_ttype_sel_g[3:0]),
 
    .q   (final_ttype_sel_w2[3:0]),
 
    .q   (final_ttype_sel_w2[3:0]),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
// 
// 
// modified for timing
 
// modified for timing
 
/*
 
/*
Line 3919... Line 3526... 
    .in2  (lsu_tlu_ttype_m2),
 
    .in2  (lsu_tlu_ttype_m2),
 
    .dout (adj_lsu_ttype_m2[`TSA_TTYPE_WIDTH-1:0])
 
    .dout (adj_lsu_ttype_m2[`TSA_TTYPE_WIDTH-1:0])
 
);
 
);
 
*/
 
*/
 
// added for timing 
// added for timing 
dff #(9) dff_lsu_tlu_ttype_w2 (
 
dff_s #(`TSA_TTYPE_WIDTH) dff_lsu_tlu_ttype_w2 (
 
    .din (lsu_tlu_ttype_m2[9-1:0]),
 
    .din (lsu_tlu_ttype_m2[`TSA_TTYPE_WIDTH-1:0]),
 
    .q   (lsu_tlu_ttype_w2[9-1:0]),
 
    .q   (lsu_tlu_ttype_w2[`TSA_TTYPE_WIDTH-1:0]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
//
 
//
 
/*
 
/*
 
dff #(`TSA_TTYPE_WIDTH-2) dff_lsu_tlu_async_ttype_w2 (
 
dff_s #(`TSA_TTYPE_WIDTH-2) dff_lsu_tlu_async_ttype_w2 (
 
    .din (lsu_tlu_async_ttype_g[`TSA_TTYPE_WIDTH-3:0]),
 
    .din (lsu_tlu_async_ttype_g[`TSA_TTYPE_WIDTH-3:0]),
 
    .q   (lsu_tlu_async_ttype_w2[`TSA_TTYPE_WIDTH-3:0]),
 
    .q   (lsu_tlu_async_ttype_w2[`TSA_TTYPE_WIDTH-3:0]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
*/
 
*/
 
mux3ds #(9) mx_adj_lsu_ttype_w2 (
 
mux3ds #(`TSA_TTYPE_WIDTH) mx_adj_lsu_ttype_w2 (
 
    .sel0 (lsu_defr_trap_w2),
 
    .sel0 (lsu_defr_trap_w2),
 
    .sel1 (va_oor_data_acc_excp_w2 & ~lsu_defr_trap_w2),
 
    .sel1 (va_oor_data_acc_excp_w2 & ~lsu_defr_trap_w2),
 
    .sel2 (~(va_oor_data_acc_excp_w2 | lsu_defr_trap_w2)),
 
    .sel2 (~(va_oor_data_acc_excp_w2 | lsu_defr_trap_w2)),
 
    // modified for bug 4561
 
    // modified for bug 4561
 
    // .in0  ({2'b0, lsu_tlu_async_ttype_w2[6:0]}),
 
    // .in0  ({2'b0, lsu_tlu_async_ttype_w2[6:0]}),
 
    .in0  (9'h032),
 
    .in0  (9'h032),
 
    .in1  (9'h030),
 
    .in1  (9'h030),
 
    .in2  (lsu_tlu_ttype_w2[9-1:0]),
 
    .in2  (lsu_tlu_ttype_w2[`TSA_TTYPE_WIDTH-1:0]),
 
    .dout (adj_lsu_ttype_w2[9-1:0])
 
    .dout (adj_lsu_ttype_w2[`TSA_TTYPE_WIDTH-1:0])
 
);
 
);
 
//
 
//
 
// modified for timing 
// modified for timing 
mux4ds #(9) mx_final_ttype_w2 (
 
mux4ds #(`TSA_TTYPE_WIDTH) mx_final_ttype_w2 (
 
    .sel0 (final_ttype_sel_w2[0]),
 
    .sel0 (final_ttype_sel_w2[0]),
 
    .sel1 (final_ttype_sel_w2[1]),
 
    .sel1 (final_ttype_sel_w2[1]),
 
    .sel2 (final_ttype_sel_w2[2]),
 
    .sel2 (final_ttype_sel_w2[2]),
 
    .sel3 (final_ttype_sel_w2[3]),
 
    .sel3 (final_ttype_sel_w2[3]),
 
    .in0  ({2'b0,rst_ttype_w2[9-3:0]}),
 
    .in0  ({2'b0,rst_ttype_w2[`TSA_TTYPE_WIDTH-3:0]}),
 
    .in1  (early_sync_ttype_w2[9-1:0]),
 
    .in1  (early_sync_ttype_w2[`TSA_TTYPE_WIDTH-1:0]),
 
    .in2  (adj_lsu_ttype_w2[9-1:0]),
 
    .in2  (adj_lsu_ttype_w2[`TSA_TTYPE_WIDTH-1:0]),
 
    .in3  (pending_ttype_w2[9-1:0]),
 
    .in3  (pending_ttype_w2[`TSA_TTYPE_WIDTH-1:0]),
 
    .dout (final_ttype_w2[9-1:0])
 
    .dout (final_ttype_w2[`TSA_TTYPE_WIDTH-1:0])
 
);
 
);
 
//
 
//
 
// modified for timing
 
// modified for timing
 
/*
 
/*
 
dff #(`TSA_TTYPE_WIDTH) dff_tlu_final_ttype_w2 (
 
dff_s #(`TSA_TTYPE_WIDTH) dff_tlu_final_ttype_w2 (
 
    .din (final_ttype_g[`TSA_TTYPE_WIDTH-1:0]),
 
    .din (final_ttype_g[`TSA_TTYPE_WIDTH-1:0]),
 
    .q   (final_ttype_w2[`TSA_TTYPE_WIDTH-1:0]),
 
    .q   (final_ttype_w2[`TSA_TTYPE_WIDTH-1:0]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
*/
 
*/
 
 
 
 
 
assign tlu_final_ttype_w2[9-1:0] =
 
assign tlu_final_ttype_w2[`TSA_TTYPE_WIDTH-1:0] =
 
           final_ttype_w2[9-1:0];
 
           final_ttype_w2[`TSA_TTYPE_WIDTH-1:0];
 
//
 
//
 
// added for timing
 
// added for timing
 
// pending trap type 
// pending trap type 
assign onehot_pending_ttype_sel = ~(|pending_trap_sel[2:0]);
 
assign onehot_pending_ttype_sel = ~(|pending_trap_sel[2:0]);
 
//
 
//
 
mux4ds #(9) mx_pending_ttype (
 
mux4ds #(`TSA_TTYPE_WIDTH) mx_pending_ttype (
 
    .sel0 (pending_trap_sel[0]),
 
    .sel0 (pending_trap_sel[0]),
 
    .sel1 (pending_trap_sel[1]),
 
    .sel1 (pending_trap_sel[1]),
 
        .sel2 (pending_trap_sel[2]),
 
        .sel2 (pending_trap_sel[2]),
 
        .sel3 (onehot_pending_ttype_sel),
 
        .sel3 (onehot_pending_ttype_sel),
 
    .in0  (pending_ttype0[9-1:0]),
 
    .in0  (pending_ttype0[`TSA_TTYPE_WIDTH-1:0]),
 
    .in1  (pending_ttype1[9-1:0]),
 
    .in1  (pending_ttype1[`TSA_TTYPE_WIDTH-1:0]),
 
    .in2  (pending_ttype2[9-1:0]),
 
    .in2  (pending_ttype2[`TSA_TTYPE_WIDTH-1:0]),
 
    .in3  (pending_ttype3[9-1:0]),
 
    .in3  (pending_ttype3[`TSA_TTYPE_WIDTH-1:0]),
 
    .dout (pending_ttype[9-1:0])
 
    .dout (pending_ttype[`TSA_TTYPE_WIDTH-1:0])
 
);
 
);
 
//
 
//
 
// added for timing 
// added for timing 
dff #(9) dff_pending_ttype_w2 (
 
dff_s #(`TSA_TTYPE_WIDTH) dff_pending_ttype_w2 (
 
    .din (pending_ttype[9-1:0]),
 
    .din (pending_ttype[`TSA_TTYPE_WIDTH-1:0]),
 
    .q   (pending_ttype_w2[9-1:0]),
 
    .q   (pending_ttype_w2[`TSA_TTYPE_WIDTH-1:0]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
//
 
//
 
// modified for timing and bug 5117
 
// modified for timing and bug 5117
 
assign rst_ttype_sel[0] = reset_sel_g;
 
assign rst_ttype_sel[0] = reset_sel_g;
 
// modified for bug 5127
 
// modified for bug 5127
 
assign rst_ttype_sel[1] =
 
assign rst_ttype_sel[1] =
 
           ((|tlz_trap_g[4-1:0]) | pib_wrap_trap_g);
 
           ((|tlz_trap_g[`TLU_THRD_NUM-1:0]) | pib_wrap_trap_g);
 
           // ~(rstint_g | rst_tri_en); 
           // ~(rstint_g | rst_tri_en); 
           // ((|tlz_trap_g[`TLU_THRD_NUM-1:0]) | pib_wrap_trap_g) & ~reset_sel_g; 
           // ((|tlz_trap_g[`TLU_THRD_NUM-1:0]) | pib_wrap_trap_g) & ~reset_sel_g; 
// assign rst_ttype_sel[2] = ~(|rst_ttype_sel[1:0]); 
// assign rst_ttype_sel[2] = ~(|rst_ttype_sel[1:0]); 
 
 
 
 
// reset ttype  
// reset ttype  
// modified for bug 3634 and bug 3705
 
// modified for bug 3634 and bug 3705
 
// modified for timing and bug 5117
 
// modified for timing and bug 5117
 
assign rst_hwint_ttype_g[9-3:0] =
 
assign rst_hwint_ttype_g[`TSA_TTYPE_WIDTH-3:0] =
 
           (rst_ttype_sel[0])? {4'b00,reset_id_g[2:0]}:
 
           (rst_ttype_sel[0])? {4'b00,reset_id_g[2:0]}:
 
          ((rst_ttype_sel[1])? wrap_tlz_ttype[6:0]:
 
          ((rst_ttype_sel[1])? wrap_tlz_ttype[6:0]:
 
            7'h60);
 
            `HWINT_INT);
 
 
 
 
 
dff #(9-2) dff_rst_hwint_ttype_w2 (
 
dff_s #(`TSA_TTYPE_WIDTH-2) dff_rst_hwint_ttype_w2 (
 
    .din (rst_hwint_ttype_g[9-3:0]),
 
    .din (rst_hwint_ttype_g[`TSA_TTYPE_WIDTH-3:0]),
 
    .q   (rst_hwint_ttype_w2[9-3:0]),
 
    .q   (rst_hwint_ttype_w2[`TSA_TTYPE_WIDTH-3:0]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dffr dffr_rst_hwint_sel_w2 (
 
dffr_s dffr_rst_hwint_sel_w2 (
 
    .din ((|rst_ttype_sel[1:0]) | hwint_g),
 
    .din ((|rst_ttype_sel[1:0]) | hwint_g),
 
    .q   (rst_hwint_sel_w2),
 
    .q   (rst_hwint_sel_w2),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
assign rst_ttype_w2[9-3:0] =
 
assign rst_ttype_w2[`TSA_TTYPE_WIDTH-3:0] =
 
       (rst_hwint_sel_w2)? rst_hwint_ttype_w2[9-3:0]:
 
       (rst_hwint_sel_w2)? rst_hwint_ttype_w2[`TSA_TTYPE_WIDTH-3:0]:
 
        final_swint_id_w2[9-3:0];
 
        final_swint_id_w2[`TSA_TTYPE_WIDTH-3:0];
 
 
 
 
 
/*
 
/*
 
mux3ds #(`TSA_TTYPE_WIDTH-2) mx_rst_ttype_g (
 
mux3ds #(`TSA_TTYPE_WIDTH-2) mx_rst_ttype_g (
 
    .sel0  (rst_ttype_sel[0]),
 
    .sel0  (rst_ttype_sel[0]),
 
    .sel1  (rst_ttype_sel[1]),
 
    .sel1  (rst_ttype_sel[1]),
Line 4056... Line 3663... 
    .in2 (hwint_swint_ttype[6:0]),
 
    .in2 (hwint_swint_ttype[6:0]),
 
    .dout (rst_ttype_g[`TSA_TTYPE_WIDTH-3:0])
 
    .dout (rst_ttype_g[`TSA_TTYPE_WIDTH-3:0])
 
);
 
);
 
//
 
//
 
// added for timing
 
// added for timing
 
dff #(`TSA_TTYPE_WIDTH-2) dff_rst_ttype_w2 (
 
dff_s #(`TSA_TTYPE_WIDTH-2) dff_rst_ttype_w2 (
 
    .din (rst_ttype_g[`TSA_TTYPE_WIDTH-3:0]),
 
    .din (rst_ttype_g[`TSA_TTYPE_WIDTH-3:0]),
 
    .q   (rst_ttype_w2[`TSA_TTYPE_WIDTH-3:0]),
 
    .q   (rst_ttype_w2[`TSA_TTYPE_WIDTH-3:0]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
// modified for timing
 
// modified for timing
 
 
 
 
 
assign rst_hwdr_ttype_sel[0] = reset_sel_g;
 
assign rst_hwdr_ttype_sel[0] = reset_sel_g;
Line 4082... Line 3689... 
    .in1  (final_swint_id[6:0]),
 
    .in1  (final_swint_id[6:0]),
 
    .dout (hwint_swint_ttype[6:0])
 
    .dout (hwint_swint_ttype[6:0])
 
);
 
);
 
*/
 
*/
 
 
 
 
 
mux2ds #(9-2) mx_wrap_tlz_ttype (
 
mux2ds #(`TSA_TTYPE_WIDTH-2) mx_wrap_tlz_ttype (
 
    .sel0 (|tlz_trap_g[4-1:0]),
 
    .sel0 (|tlz_trap_g[`TLU_THRD_NUM-1:0]),
 
    .sel1 (~(|tlz_trap_g[4-1:0])),
 
    .sel1 (~(|tlz_trap_g[`TLU_THRD_NUM-1:0])),
 
    .in0  (7'h5f),
 
    .in0  (`TLZ_TRAP),
 
    .in1  (7'h4f),
 
    .in1  (`PIB_OVERFLOW_TTYPE),
 
    .dout (wrap_tlz_ttype[6:0])
 
    .dout (wrap_tlz_ttype[6:0])
 
);
 
);
 
//
 
//
 
// modified for timing
 
// modified for timing
 
assign rst_hwdr_ttype_sel_w2 = hyper_wdr_trap_w2 & ~reset_sel_w2;
 
assign rst_hwdr_ttype_sel_w2 = hyper_wdr_trap_w2 & ~reset_sel_w2;
 
 
 
 
 
mux2ds #(9-2) mx_rst_hwdr_ttype_w2 (
 
mux2ds #(`TSA_TTYPE_WIDTH-2) mx_rst_hwdr_ttype_w2 (
 
    .sel0  (rst_hwdr_ttype_sel_w2),
 
    .sel0  (rst_hwdr_ttype_sel_w2),
 
    .sel1  (~rst_hwdr_ttype_sel_w2),
 
    .sel1  (~rst_hwdr_ttype_sel_w2),
 
    .in0 ({7'b0000010}),
 
    .in0 ({7'b0000010}),
 
    .in1 (rst_ttype_w2[9-3:0]),
 
    .in1 (rst_ttype_w2[`TSA_TTYPE_WIDTH-3:0]),
 
    .dout (rst_hwdr_ttype_w2[9-3:0])
 
    .dout (rst_hwdr_ttype_w2[`TSA_TTYPE_WIDTH-3:0])
 
);
 
);
 
//
 
//
 
/*
 
/*
 
mux4ds #(`TSA_TTYPE_WIDTH-2) mx_rst_hwdr_ttype (
 
mux4ds #(`TSA_TTYPE_WIDTH-2) mx_rst_hwdr_ttype (
 
    .sel0  (rst_hwdr_ttype_sel[0]),
 
    .sel0  (rst_hwdr_ttype_sel[0]),
Line 4115... Line 3722... 
    .in3 (hwint_swint_ttype[6:0]),
 
    .in3 (hwint_swint_ttype[6:0]),
 
    .dout (rst_hwdr_ttype_g[`TSA_TTYPE_WIDTH-3:0])
 
    .dout (rst_hwdr_ttype_g[`TSA_TTYPE_WIDTH-3:0])
 
);
 
);
 
//
 
//
 
// added for timing
 
// added for timing
 
dff #(`TSA_TTYPE_WIDTH-2) dff_rst_hwdr_ttype_w2 (
 
dff_s #(`TSA_TTYPE_WIDTH-2) dff_rst_hwdr_ttype_w2 (
 
    .din (rst_hwdr_ttype_g[`TSA_TTYPE_WIDTH-3:0]),
 
    .din (rst_hwdr_ttype_g[`TSA_TTYPE_WIDTH-3:0]),
 
    .q   (rst_hwdr_ttype_w2[`TSA_TTYPE_WIDTH-3:0]),
 
    .q   (rst_hwdr_ttype_w2[`TSA_TTYPE_WIDTH-3:0]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
*/
 
*/
 
//
 
//
 
// construct the early_ttype_g for timing to determine whether
 
// construct the early_ttype_g for timing to determine whether
 
// the trap is hypervisor or supervisor traps
 
// the trap is hypervisor or supervisor traps
 
// modified for bug 3646, 5117 and timing
 
// modified for bug 3646, 5117 and timing
 
assign early_ttype_sel[0] =
 
assign early_ttype_sel[0] =
 
             reset_sel_g | hwint_g | (|tlz_trap_g[4-1:0]);
 
             reset_sel_g | hwint_g | (|tlz_trap_g[`TLU_THRD_NUM-1:0]);
 
             // reset_sel_g | hwint_g | swint_g | (|tlz_trap_g[`TLU_THRD_NUM-1:0]);
 
             // reset_sel_g | hwint_g | swint_g | (|tlz_trap_g[`TLU_THRD_NUM-1:0]);
 
assign early_ttype_sel[1] =
 
assign early_ttype_sel[1] =
 
            local_early_flush_pipe_w;
 
            local_early_flush_pipe_w;
 
            // local_early_flush_pipe_w & ~(reset_sel_g | hwint_g | swint_g | 
            // local_early_flush_pipe_w & ~(reset_sel_g | hwint_g | swint_g | 
            // (|tlz_trap_g[`TLU_THRD_NUM-1:0])); 
            // (|tlz_trap_g[`TLU_THRD_NUM-1:0])); 
assign early_ttype_sel[2] =
 
assign early_ttype_sel[2] =
 
            ~inst_vld_nf_g | inst_ifu_flush_w | ~(|early_ttype_sel[1:0]);
 
            ~inst_vld_nf_g | inst_ifu_flush_w | ~(|early_ttype_sel[1:0]);
 
 
 
 
 
assign early_ttype_g[9-1:0] =
 
assign early_ttype_g[`TSA_TTYPE_WIDTH-1:0] =
 
           (early_ttype_sel[2])? pending_ttype[9-1:0]:
 
           (early_ttype_sel[2])? pending_ttype[`TSA_TTYPE_WIDTH-1:0]:
 
           (early_ttype_sel[0])? {2'b0,rst_hwint_ttype_g[9-3:0]}:
 
           (early_ttype_sel[0])? {2'b0,rst_hwint_ttype_g[`TSA_TTYPE_WIDTH-3:0]}:
 
           // (early_ttype_sel[0])? {2'b0,rst_ttype_g[`TSA_TTYPE_WIDTH-3:0]}:
 
           // (early_ttype_sel[0])? {2'b0,rst_ttype_g[`TSA_TTYPE_WIDTH-3:0]}:
 
            early_sync_ttype_g[9-1:0];
 
            early_sync_ttype_g[`TSA_TTYPE_WIDTH-1:0];
 
/*
 
/*
 
assign early_ttype_sel[0] =
 
assign early_ttype_sel[0] =
 
            reset_sel_g | ((hwint_g | swint_g | (|tlz_trap_g[`TLU_THRD_NUM-1:0])) &
 
            reset_sel_g | ((hwint_g | swint_g | (|tlz_trap_g[`TLU_THRD_NUM-1:0])) &
 
            inst_vld_g) ;
 
            inst_vld_g) ;
 
assign early_ttype_sel[1] =
 
assign early_ttype_sel[1] =
Line 4170... Line 3777... 
assign final_offset_en_g[0] = trap_to_redmode & ~(sir_inst_g | internal_wdr);
 
assign final_offset_en_g[0] = trap_to_redmode & ~(sir_inst_g | internal_wdr);
 
assign final_offset_en_g[1] = internal_wdr & ~final_offset_en_g[0];
 
assign final_offset_en_g[1] = internal_wdr & ~final_offset_en_g[0];
 
// modified due to one-hot mux bug
 
// modified due to one-hot mux bug
 
// assign final_offset_en_g[2] = ~(|final_offset_en_g[1:0]); 
// assign final_offset_en_g[2] = ~(|final_offset_en_g[1:0]); 
 
 
 
 
dffr #(2) dffr_final_offset_en_w1 (
 
dffr_s #(2) dffr_final_offset_en_w1 (
 
    .din (final_offset_en_g[1:0]),
 
    .din (final_offset_en_g[1:0]),
 
    .q   (final_offset_en_w1[1:0]),
 
    .q   (final_offset_en_w1[1:0]),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
assign final_offset_sel_w1[2] =
 
assign final_offset_sel_w1[2] =
 
           ~(|final_offset_sel_w1[1:0]);
 
           ~(|final_offset_sel_w1[1:0]);
 
assign final_offset_sel_w1[1] =
 
assign final_offset_sel_w1[1] =
 
           final_offset_en_w1[1] & ~rst_tri_en;
 
           final_offset_en_w1[1] & ~rst_tri_en;
 
assign final_offset_sel_w1[0] =
 
assign final_offset_sel_w1[0] =
 
           final_offset_en_w1[0] & ~rst_tri_en;
 
           final_offset_en_w1[0] & ~rst_tri_en;
 
 
 
 
 
mux3ds #(9) mx_final_offset_w1 (
 
mux3ds #(`TSA_TTYPE_WIDTH) mx_final_offset_w1 (
 
    .sel0 (final_offset_sel_w1[0]),
 
    .sel0 (final_offset_sel_w1[0]),
 
    .sel1 (final_offset_sel_w1[1]),
 
    .sel1 (final_offset_sel_w1[1]),
 
    .sel2 (final_offset_sel_w1[2]),
 
    .sel2 (final_offset_sel_w1[2]),
 
    .in0  (9'b000000101),
 
    .in0  (9'b000000101),
 
    .in1  (9'b000000010),
 
    .in1  (9'b000000010),
 
    .in2  (tba_ttype_w1[9-1:0]),
 
    .in2  (tba_ttype_w1[`TSA_TTYPE_WIDTH-1:0]),
 
    .dout (final_offset_w1[9-1:0])
 
    .dout (final_offset_w1[`TSA_TTYPE_WIDTH-1:0])
 
);
 
);
 
 
 
 
 
assign tlu_final_offset_w1[9-1:0] =
 
assign tlu_final_offset_w1[`TSA_TTYPE_WIDTH-1:0] =
 
           final_offset_w1[9-1:0];
 
           final_offset_w1[`TSA_TTYPE_WIDTH-1:0];
 
// 
// 
// generating the trap pc and trap npc
 
// generating the trap pc and trap npc
 
// This section has been modified due to bug 3017 
// This section has been modified due to bug 3017 
// pc and npc has been changed from 48 -> 49 bits
 
// pc and npc has been changed from 48 -> 49 bits
 
// added for one-hot mux problem
 
// added for one-hot mux problem
Line 4229... Line 3836... 
       .sel0 (~restore_pc_sel_w1),
 
       .sel0 (~restore_pc_sel_w1),
 
       .sel1 (restore_pc_sel_w1),
 
       .sel1 (restore_pc_sel_w1),
 
       .dout (trap_pc_w1[48:0])
 
       .dout (trap_pc_w1[48:0])
 
);
 
);
 
//
 
//
 
dff #(49) dff_trap_pc_w2 (
 
dff_s #(49) dff_trap_pc_w2 (
 
    .din (trap_pc_w1[48:0]),
 
    .din (trap_pc_w1[48:0]),
 
    .q   (trap_pc_w2[48:0]),
 
    .q   (trap_pc_w2[48:0]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
assign tlu_ifu_trappc_w2[48:0] = trap_pc_w2[48:0];
 
assign tlu_ifu_trappc_w2[48:0] = trap_pc_w2[48:0];
 
 
 
 
Line 4248... Line 3855... 
       .sel0 (~restore_pc_sel_w1),
 
       .sel0 (~restore_pc_sel_w1),
 
       .sel1 (restore_pc_sel_w1),
 
       .sel1 (restore_pc_sel_w1),
 
       .dout (trap_npc_w1[48:0])
 
       .dout (trap_npc_w1[48:0])
 
);
 
);
 
//
 
//
 
dff #(49) dff_trap_npc_w2 (
 
dff_s #(49) dff_trap_npc_w2 (
 
    .din (trap_npc_w1[48:0]),
 
    .din (trap_npc_w1[48:0]),
 
    .q   (trap_npc_w2[48:0]),
 
    .q   (trap_npc_w2[48:0]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
assign tlu_ifu_trapnpc_w2[48:0] = trap_npc_w2[48:0];
 
assign tlu_ifu_trapnpc_w2[48:0] = trap_npc_w2[48:0];
 
*/
 
*/
Line 4272... Line 3879... 
                   (tlu_hpstate_enb[1] & ~tlu_hpstate_priv[1] & trp_lvl_at_maxstl[1]):
 
                   (tlu_hpstate_enb[1] & ~tlu_hpstate_priv[1] & trp_lvl_at_maxstl[1]):
 
                  ((true_trap_tid_g[1:0] == 2'b10) ?
 
                  ((true_trap_tid_g[1:0] == 2'b10) ?
 
                       (tlu_hpstate_enb[2] & ~tlu_hpstate_priv[2] & trp_lvl_at_maxstl[2]):
 
                       (tlu_hpstate_enb[2] & ~tlu_hpstate_priv[2] & trp_lvl_at_maxstl[2]):
 
                       (tlu_hpstate_enb[3] & ~tlu_hpstate_priv[3] & trp_lvl_at_maxstl[3]))));
 
                       (tlu_hpstate_enb[3] & ~tlu_hpstate_priv[3] & trp_lvl_at_maxstl[3]))));
 
 
 
 
 
dffr dffr_hyper_wdr_early_trap_w2 (
 
dffr_s dffr_hyper_wdr_early_trap_w2 (
 
   .din (hyper_wdr_early_trap_g),
 
   .din (hyper_wdr_early_trap_g),
 
   .q   (hyper_wdr_early_trap_w2),
 
   .q   (hyper_wdr_early_trap_w2),
 
   .rst (local_rst),
 
   .rst (local_rst),
 
   .clk (clk),
 
   .clk (clk),
 
   .se  (se),
 
   .se  (se),
 
   .si  (),
 
   `SIMPLY_RISC_SCANIN,
 
   .so  ()
 
   .so  ()
 
);
 
);
 
 
 
 
 
assign hyper_wdr_trap_w2 =
 
assign hyper_wdr_trap_w2 =
 
           hyper_wdr_early_trap_w2 & (tlu_priv_traps_w2 & ~lsu_defr_trap_w2);
 
           hyper_wdr_early_trap_w2 & (tlu_priv_traps_w2 & ~lsu_defr_trap_w2);
Line 4312... Line 3919... 
                       (~tlu_hpstate_enb[2] | tlu_hpstate_priv[2] |
 
                       (~tlu_hpstate_enb[2] | tlu_hpstate_priv[2] |
 
                         trp_lvl_gte_maxstl[2] | (tlz_trap_g[2] & inst_vld_g)):
 
                         trp_lvl_gte_maxstl[2] | (tlz_trap_g[2] & inst_vld_g)):
 
                       (~tlu_hpstate_enb[3] | tlu_hpstate_priv[3] |
 
                       (~tlu_hpstate_enb[3] | tlu_hpstate_priv[3] |
 
                         trp_lvl_gte_maxstl[3] | (tlz_trap_g[3] & inst_vld_g))));
 
                         trp_lvl_gte_maxstl[3] | (tlz_trap_g[3] & inst_vld_g))));
 
// added for timing
 
// added for timing
 
dffr dffr_tlu_tlu_trap_to_hyper_w2 (
 
dffr_s dffr_tlu_tlu_trap_to_hyper_w2 (
 
    .din (tlu_trap_to_hyper_g),
 
    .din (tlu_trap_to_hyper_g),
 
    .q   (tlu_trap_to_hyper_w2),
 
    .q   (tlu_trap_to_hyper_w2),
 
    .clk (clk),
 
    .clk (clk),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
// recoded for timing
 
// recoded for timing
 
assign select_tba_element_w2[0] =
 
assign select_tba_element_w2[0] =
Line 4334... Line 3941... 
assign tdp_select_tba_w2 = local_select_tba_w2;
 
assign tdp_select_tba_w2 = local_select_tba_w2;
 
assign tlu_select_tba_w2 =
 
assign tlu_select_tba_w2 =
 
           select_tba_element_w2[1] | (select_tba_element_w2[0] & ~lsu_ttype_vld_w2);
 
           select_tba_element_w2[1] | (select_tba_element_w2[0] & ~lsu_ttype_vld_w2);
 
 
 
 
 
/*
 
/*
 
dffr dffr_tlu_select_tba_w2 (
 
dffr_s dffr_tlu_select_tba_w2 (
 
    .din (select_tba_g),
 
    .din (select_tba_g),
 
    .q   (tlu_select_tba_w2),
 
    .q   (tlu_select_tba_w2),
 
    .clk (clk),
 
    .clk (clk),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
*/
 
*/
 
//
 
//
 
// added for bug 2064 and modified for bug 2165
 
// added for bug 2064 and modified for bug 2165
Line 4354... Line 3961... 
           ((early_ttype_g[8:4] == 5'b00100)    & (|early_ttype_g[3:0])) |
 
           ((early_ttype_g[8:4] == 5'b00100)    & (|early_ttype_g[3:0])) |
 
           ((early_ttype_g[8:4] == 5'b00010)    & ~(early_ttype_g[3] & early_ttype_g[0]))|
 
           ((early_ttype_g[8:4] == 5'b00010)    & ~(early_ttype_g[3] & early_ttype_g[0]))|
 
           ((early_ttype_g[8:2] == 7'b0011000)  & (early_ttype_g[1] ^ early_ttype_g[0])) |
 
           ((early_ttype_g[8:2] == 7'b0011000)  & (early_ttype_g[1] ^ early_ttype_g[0])) |
 
           ((early_ttype_g[8:4] == 5'b00111)    & (early_ttype_g[3:2]== 2'b11))       |
 
           ((early_ttype_g[8:4] == 5'b00111)    & (early_ttype_g[3:2]== 2'b11))       |
 
           (early_ttype_g[8] & ~early_ttype_g[7]) | (early_ttype_g[7] & ~early_ttype_g[8]) |
 
           (early_ttype_g[8] & ~early_ttype_g[7]) | (early_ttype_g[7] & ~early_ttype_g[8]) |
 
           (pib_wrap_trap_g & ~(|tlz_trap_g[4-1:0]) & inst_vld_g) |
 
           (pib_wrap_trap_g & ~(|tlz_trap_g[`TLU_THRD_NUM-1:0]) & inst_vld_g) |
 
           (swint_g & ~(|tlz_trap_g[4-1:0]) & inst_vld_g);
 
           (swint_g & ~(|tlz_trap_g[`TLU_THRD_NUM-1:0]) & inst_vld_g);
 
 
 
 
 
assign exu_hyper_traps_g =
 
assign exu_hyper_traps_g =
 
           exu_ttype_vld_g & ((early_ttype_g[8:0] == 9'h029) | (early_ttype_g[8:0] == 9'h034));
 
           exu_ttype_vld_g & ((early_ttype_g[8:0] == 9'h029) | (early_ttype_g[8:0] == 9'h034));
 
 
 
 
 
//
 
//
Line 4374... Line 3981... 
          lsu_tlu_wtchpt_trp_g & ~(misalign_addr_jmpl_rtn_g | misalign_addr_ldst_atm_g |
 
          lsu_tlu_wtchpt_trp_g & ~(misalign_addr_jmpl_rtn_g | misalign_addr_ldst_atm_g |
 
          ifu_ttype_vld_g | exu_hyper_traps_g | lsu_tlu_priv_action_g);
 
          ifu_ttype_vld_g | exu_hyper_traps_g | lsu_tlu_priv_action_g);
 
//          lsu_tlu_wtchpt_trp_g & ~(lsu_tlu_priv_violtn_g | misalign_addr_jmpl_rtn_g |
 
//          lsu_tlu_wtchpt_trp_g & ~(lsu_tlu_priv_violtn_g | misalign_addr_jmpl_rtn_g |
 
//
 
//
 
// modified for added for timing
 
// modified for added for timing
 
dffr #(3) dffr_tlu_early_priv_element_w2 (
 
dffr_s #(3) dffr_tlu_early_priv_element_w2 (
 
    .din (tlu_early_priv_element_g[2:0]),
 
    .din (tlu_early_priv_element_g[2:0]),
 
        .q   (tlu_early_priv_element_w2[2:0]),
 
        .q   (tlu_early_priv_element_w2[2:0]),
 
    .clk (clk),
 
    .clk (clk),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
assign tlu_priv_traps_w2 =
 
assign tlu_priv_traps_w2 =
 
            tlu_early_priv_element_w2[0] & ~lsu_ttype_vld_w2 |
 
            tlu_early_priv_element_w2[0] & ~lsu_ttype_vld_w2 |
 
            tlu_early_priv_element_w2[1] |
 
            tlu_early_priv_element_w2[1] |
 
            tlu_early_priv_element_w2[2];
 
            tlu_early_priv_element_w2[2];
 
 
 
 
 
dffr dffr_tlu_self_boot_rst_w2 (
 
dffr_s dffr_tlu_self_boot_rst_w2 (
 
    .din (tlu_self_boot_rst_g),
 
    .din (tlu_self_boot_rst_g),
 
        .q   (tlu_self_boot_rst_w2),
 
        .q   (tlu_self_boot_rst_w2),
 
    .clk (clk),
 
    .clk (clk),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
//=========================================================================================
 
//=========================================================================================
 
//      Generate TSA Control and Data
 
//      Generate TSA Control and Data
Line 4420... Line 4027... 
           (((wsr_inst_g & (tstate_rw_g | tpc_rw_g |
 
           (((wsr_inst_g & (tstate_rw_g | tpc_rw_g |
 
            tnpc_rw_g  | ttype_rw_g | tlu_htstate_rw_g)) |
 
            tnpc_rw_g  | ttype_rw_g | tlu_htstate_rw_g)) |
 
           ((retry_inst_g | done_inst_g) & cwp_fastcmplt_g)) &
 
           ((retry_inst_g | done_inst_g) & cwp_fastcmplt_g)) &
 
            inst_vld_g) | sync_trap_taken_g ;
 
            inst_vld_g) | sync_trap_taken_g ;
 
 
 
 
 
dffr dffr_tsa_wr_tid_sel_w2 (
 
dffr_s dffr_tsa_wr_tid_sel_w2 (
 
    .din (tsa_wr_tid_sel_tim_g),
 
    .din (tsa_wr_tid_sel_tim_g),
 
        .q   (tsa_wr_tid_sel_w2),
 
        .q   (tsa_wr_tid_sel_w2),
 
    .clk (clk),
 
    .clk (clk),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
/*
 
/*
 
assign tsa_wr_tid_sel_w2 =
 
assign tsa_wr_tid_sel_w2 =
 
           (((wsr_inst_w2 & (tstate_rw_w2 | tpc_rw_w2 |
 
           (((wsr_inst_w2 & (tstate_rw_w2 | tpc_rw_w2 |
Line 4486... Line 4093... 
                        (tpc_rw_d | tnpc_rw_d | tstate_rw_d | ttype_rw_d |
 
                        (tpc_rw_d | tnpc_rw_d | tstate_rw_d | ttype_rw_d |
 
                         // tick_rw_d | tba_rw_d | pstate_rw_d | tl_rw_d    |
 
                         // tick_rw_d | tba_rw_d | pstate_rw_d | tl_rw_d    |
 
             tlu_htstate_rw_d) & ifu_tlu_rsr_inst_d; // rdpr-tsa
 
             tlu_htstate_rw_d) & ifu_tlu_rsr_inst_d; // rdpr-tsa
 
//
 
//
 
// added for timing
 
// added for timing
 
dff dff_tsa_rd_vld_e (
 
dff_s dff_tsa_rd_vld_e (
 
    .din (tsa_rd_vld),
 
    .din (tsa_rd_vld),
 
        .q   (tsa_rd_vld_e),
 
        .q   (tsa_rd_vld_e),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
//
 
//
 
// added for timing
 
// added for timing
 
assign  tsa_rd_en = ifu_tlu_done_inst_d | ifu_tlu_retry_inst_d | // done/retry
 
assign  tsa_rd_en = ifu_tlu_done_inst_d | ifu_tlu_retry_inst_d | // done/retry
 
                    (~(|sraddr2[4:2]) & ifu_tlu_rsr_inst_d); // rdpr-tsa
 
                    (~(|sraddr2[4:2]) & ifu_tlu_rsr_inst_d); // rdpr-tsa
 
// 
// 
dff #(4) dff_thread_wsel_w2 (
 
dff_s #(`TLU_THRD_NUM) dff_thread_wsel_w2 (
 
    .din ({thread3_wsel_g, thread2_wsel_g, thread1_wsel_g, thread0_wsel_g}),
 
    .din ({thread3_wsel_g, thread2_wsel_g, thread1_wsel_g, thread0_wsel_g}),
 
    .q   ({thread3_wsel_w2, thread2_wsel_w2, thread1_wsel_w2, thread0_wsel_w2}),
 
    .q   ({thread3_wsel_w2, thread2_wsel_w2, thread1_wsel_w2, thread0_wsel_w2}),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
assign  tlu_thread_wsel_g[0] = thread0_rsel_dec_g;
 
assign  tlu_thread_wsel_g[0] = thread0_rsel_dec_g;
 
assign  tlu_thread_wsel_g[1] = thread1_rsel_dec_g;
 
assign  tlu_thread_wsel_g[1] = thread1_rsel_dec_g;
Line 4556... Line 4163... 
 
 
 
 
// The initial state of TT should be 1 on por. Since this is required for 4 thread,
 
// The initial state of TT should be 1 on por. Since this is required for 4 thread,
 
// it will be difficult to do this thru a write to the tsa while reset is occuring.
 
// it will be difficult to do this thru a write to the tsa while reset is occuring.
 
// Instead a bit will be used to mark whether the tt for a thread has been written to.
 
// Instead a bit will be used to mark whether the tt for a thread has been written to.
 
// If it hasn't then a '1' has to be inserted into the 
// If it hasn't then a '1' has to be inserted into the 
dff dff_rst_d1 (
 
dff_s dff_rst_d1 (
 
    .din (local_rst),
 
    .din (local_rst),
 
    .q   (reset_d1),
 
    .q   (reset_d1),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
assign  tt_init_en =  reset_d1 & tlu_rst_l;
 
assign  tt_init_en =  reset_d1 & tlu_rst_l;
 
//
 
//
Line 4579... Line 4186... 
assign  tt_init_rst[3] =
 
assign  tt_init_rst[3] =
 
            local_rst | (tsa_ttype_en & (|tsa_wr_vld[1:0]) & thread3_wtrp_w2);
 
            local_rst | (tsa_ttype_en & (|tsa_wr_vld[1:0]) & thread3_wtrp_w2);
 
 
 
 
 
assign  lsu_tlu_rsr_data_mod_e[7:0] = ttype_unwritten_sel ? 8'b0000_0001 : lsu_tlu_rsr_data_e[7:0];
 
assign  lsu_tlu_rsr_data_mod_e[7:0] = ttype_unwritten_sel ? 8'b0000_0001 : lsu_tlu_rsr_data_e[7:0];
 
 
 
 
 
dffre dffre_tt_init0  (
 
dffre_s dffre_tt_init0  (
 
    .din (tt_init_en),
 
    .din (tt_init_en),
 
    .q   (tt_unwritten[0]),
 
    .q   (tt_unwritten[0]),
 
    .rst (tt_init_rst[0]),
 
    .rst (tt_init_rst[0]),
 
    .en  (tt_init_en),
 
    .en  (tt_init_en),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dffre dffre_tt_init1  (
 
dffre_s dffre_tt_init1  (
 
    .din (tt_init_en),
 
    .din (tt_init_en),
 
    .q   (tt_unwritten[1]),
 
    .q   (tt_unwritten[1]),
 
    .rst (tt_init_rst[1]),
 
    .rst (tt_init_rst[1]),
 
    .en  (tt_init_en),
 
    .en  (tt_init_en),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dffre dffre_tt_init2  (
 
dffre_s dffre_tt_init2  (
 
    .din (tt_init_en),
 
    .din (tt_init_en),
 
    .q   (tt_unwritten[2]),
 
    .q   (tt_unwritten[2]),
 
    .rst (tt_init_rst[2]),
 
    .rst (tt_init_rst[2]),
 
    .en  (tt_init_en),
 
    .en  (tt_init_en),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dffre dffre_tt_init3  (
 
dffre_s dffre_tt_init3  (
 
    .din (tt_init_en),
 
    .din (tt_init_en),
 
    .q   (tt_unwritten[3]),
 
    .q   (tt_unwritten[3]),
 
    .rst (tt_init_rst[3]),
 
    .rst (tt_init_rst[3]),
 
    .en  (tt_init_en),
 
    .en  (tt_init_en),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
//=========================================================================================
 
//=========================================================================================
 
//      Decode SR Addr
 
//      Decode SR Addr
Line 4644... Line 4251... 
// - Access to reserved rs1 fields causes an illegal_inst exception.
 
// - Access to reserved rs1 fields causes an illegal_inst exception.
 
// - privileged opcode.
 
// - privileged opcode.
 
// RDSR :
 
// RDSR :
 
// - privileged opcode. rdasr only - implementation dependent.
 
// - privileged opcode. rdasr only - implementation dependent.
 
// - Access to reserved rs1 fields causes an illegal_inst exception.
 
// - Access to reserved rs1 fields causes an illegal_inst exception.
 
assign  sraddr[7-1:0]    =
 
assign  sraddr[`TLU_ASR_ADDR_WIDTH-1:0]  =
 
            ifu_tlu_sraddr_d[7-1:0];
 
            ifu_tlu_sraddr_d[`TLU_ASR_ADDR_WIDTH-1:0];
 
assign  sraddr2[7-1:0] =
 
assign  sraddr2[`TLU_ASR_ADDR_WIDTH-1:0] =
 
            sraddr[7-1:0];
 
            sraddr[`TLU_ASR_ADDR_WIDTH-1:0];
 
//
 
//
 
// added for hypervisor support
 
// added for hypervisor support
 
assign  asr_hyperp  =   sraddr2[6];
 
assign  asr_hyperp  =   sraddr2[6];
 
assign  asr_priv    =   sraddr2[5];
 
assign  asr_priv    =   sraddr2[5];
 
 
 
 
Line 4695... Line 4302... 
assign  sftint_rg_rw_d  =  sraddr2[4] &  ~sraddr2[3] & sraddr2[2] &  sraddr2[1] & ~sraddr2[0] &
 
assign  sftint_rg_rw_d  =  sraddr2[4] &  ~sraddr2[3] & sraddr2[2] &  sraddr2[1] & ~sraddr2[0] &
 
                           ~(asr_priv | asr_hyperp);
 
                           ~(asr_priv | asr_hyperp);
 
//
 
//
 
// pib register decodes
 
// pib register decodes
 
assign pcr_rsr_d =
 
assign pcr_rsr_d =
 
           (sraddr[7-1:0] == 7'b0010000);
 
           (sraddr[`TLU_ASR_ADDR_WIDTH-1:0] == `PCR_ASR_ADDR);
 
assign pic_rsr_d =
 
assign pic_rsr_d =
 
           ((sraddr[7-1:0] == 7'b0110001) |
 
           ((sraddr[`TLU_ASR_ADDR_WIDTH-1:0] == `PIC_ASR_PRIV_ADDR) |
 
            (sraddr[7-1:0] == 7'b0010001));
 
            (sraddr[`TLU_ASR_ADDR_WIDTH-1:0] == `PIC_ASR_NPRIV_ADDR));
 
 
 
 
 
// Bug 818 fix: The qualification to sraddr[5] is removed due to the sftint and tick_cmp registers
 
// Bug 818 fix: The qualification to sraddr[5] is removed due to the sftint and tick_cmp registers
 
// are priveledged write state registers and not priveledged registers, therefore, the sraddr[5] is 
// are priveledged write state registers and not priveledged registers, therefore, the sraddr[5] is 
// not asserted for these
 
// not asserted for these
 
// modified due to timing
 
// modified due to timing
Line 4710... Line 4317... 
//
 
//
 
// added for bug 1293
 
// added for bug 1293
 
 
 
 
 
// Stage to E1.
 
// Stage to E1.
 
 
 
 
 
dff dff_tpc_rw_e (
 
dff_s dff_tpc_rw_e (
 
    .din (tpc_rw_d),
 
    .din (tpc_rw_d),
 
    .q   (tpc_rw_e),
 
    .q   (tpc_rw_e),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_tnpc_rw_e (
 
dff_s dff_tnpc_rw_e (
 
    .din (tnpc_rw_d),
 
    .din (tnpc_rw_d),
 
    .q   (tnpc_rw_e),
 
    .q   (tnpc_rw_e),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_tstate_rw_e (
 
dff_s dff_tstate_rw_e (
 
    .din (tstate_rw_d),
 
    .din (tstate_rw_d),
 
    .q   (tstate_rw_e),
 
    .q   (tstate_rw_e),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_ttype_rw_e (
 
dff_s dff_ttype_rw_e (
 
    .din (ttype_rw_d),
 
    .din (ttype_rw_d),
 
    .q   (ttype_rw_e),
 
    .q   (ttype_rw_e),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_tick_rw_e (
 
dff_s dff_tick_rw_e (
 
    .din (tick_rw_d),
 
    .din (tick_rw_d),
 
    .q   (tick_rw_e),
 
    .q   (tick_rw_e),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_tick_npriv_r_e (
 
dff_s dff_tick_npriv_r_e (
 
    .din (tick_npriv_r_d),
 
    .din (tick_npriv_r_d),
 
    .q   (tick_npriv_r_e),
 
    .q   (tick_npriv_r_e),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_tickcmp_rw_e (
 
dff_s dff_tickcmp_rw_e (
 
    .din (tickcmp_rw_d),
 
    .din (tickcmp_rw_d),
 
    .q   (tickcmp_rw_e),
 
    .q   (tickcmp_rw_e),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_tba_rw_e (
 
dff_s dff_tba_rw_e (
 
    .din (tba_rw_d),
 
    .din (tba_rw_d),
 
    .q   (tba_rw_e),
 
    .q   (tba_rw_e),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_pstate_rw_e (
 
dff_s dff_pstate_rw_e (
 
    .din (pstate_rw_d),
 
    .din (pstate_rw_d),
 
    .q   (pstate_rw_e),
 
    .q   (pstate_rw_e),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_tl_rw_d_e (
 
dff_s dff_tl_rw_d_e (
 
    .din (tl_rw_d),
 
    .din (tl_rw_d),
 
    .q   (tl_rw_e),
 
    .q   (tl_rw_e),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_pil_rw_d_e (
 
dff_s dff_pil_rw_d_e (
 
    .din (pil_rw_d),
 
    .din (pil_rw_d),
 
    .q   (pil_rw_e),
 
    .q   (pil_rw_e),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_set_sftint_e (
 
dff_s dff_set_sftint_e (
 
    .din (set_sftint_d),
 
    .din (set_sftint_d),
 
    .q   (set_sftint_e),
 
    .q   (set_sftint_e),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_clr_sftint_e (
 
dff_s dff_clr_sftint_e (
 
    .din (clr_sftint_d),
 
    .din (clr_sftint_d),
 
    .q   (clr_sftint_e),
 
    .q   (clr_sftint_e),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_sftint_rg_rw_e (
 
dff_s dff_sftint_rg_rw_e (
 
    .din (sftint_rg_rw_d),
 
    .din (sftint_rg_rw_d),
 
    .q   (sftint_rg_rw_e),
 
    .q   (sftint_rg_rw_e),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_pcr_rsr_e (
 
dff_s dff_pcr_rsr_e (
 
    .din (pcr_rsr_d),
 
    .din (pcr_rsr_d),
 
    .q   (pcr_rsr_e),
 
    .q   (pcr_rsr_e),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_pic_rsr_e (
 
dff_s dff_pic_rsr_e (
 
    .din (pic_rsr_d),
 
    .din (pic_rsr_d),
 
    .q   (pic_rsr_e),
 
    .q   (pic_rsr_e),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
//
 
//
 
// modified due to timing
 
// modified due to timing
 
/*
 
/*
 
dff dff_wsr_inst_d_e (
 
dff_s dff_wsr_inst_d_e (
 
    .din (wsr_inst_d),
 
    .din (wsr_inst_d),
 
    .q   (wsr_inst_e),
 
    .q   (wsr_inst_e),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
*/
 
*/
 
assign  wsr_inst_e      = lsu_tlu_wsr_inst_e;
 
assign  wsr_inst_e      = lsu_tlu_wsr_inst_e;
 
 
 
 
 
dff dff_stickcmp_rw_e (
 
dff_s dff_stickcmp_rw_e (
 
    .din (stickcmp_rw_d),
 
    .din (stickcmp_rw_d),
 
    .q   (stickcmp_rw_e),
 
    .q   (stickcmp_rw_e),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
// Stage to E2.
 
// Stage to E2.
 
 
 
 
 
dff dff_tpc_rw_m (
 
dff_s dff_tpc_rw_m (
 
   .din (tpc_rw_e),
 
   .din (tpc_rw_e),
 
   .q   (tpc_rw_m),
 
   .q   (tpc_rw_m),
 
   .clk (clk),
 
   .clk (clk),
 
   .se  (se),
 
   .se  (se),
 
   .si  (),
 
   `SIMPLY_RISC_SCANIN,
 
   .so  ()
 
   .so  ()
 
);
 
);
 
 
 
 
 
dff dff_tnpc_rw_m (
 
dff_s dff_tnpc_rw_m (
 
   .din (tnpc_rw_e),
 
   .din (tnpc_rw_e),
 
   .q   (tnpc_rw_m),
 
   .q   (tnpc_rw_m),
 
   .clk (clk),
 
   .clk (clk),
 
   .se  (se),
 
   .se  (se),
 
   .si  (),
 
   `SIMPLY_RISC_SCANIN,
 
   .so  ()
 
   .so  ()
 
);
 
);
 
 
 
 
 
dff dff_tstate_rw_m (
 
dff_s dff_tstate_rw_m (
 
    .din (tstate_rw_e),
 
    .din (tstate_rw_e),
 
    .q   (tstate_rw_m),
 
    .q   (tstate_rw_m),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_ttype_rw_m (
 
dff_s dff_ttype_rw_m (
 
   .din (ttype_rw_e),
 
   .din (ttype_rw_e),
 
   .q   (ttype_rw_m),
 
   .q   (ttype_rw_m),
 
   .clk (clk),
 
   .clk (clk),
 
   .se  (se),
 
   .se  (se),
 
   .si  (),
 
   `SIMPLY_RISC_SCANIN,
 
   .so  ()
 
   .so  ()
 
);
 
);
 
 
 
 
 
dff dff_tick_rw_m (
 
dff_s dff_tick_rw_m (
 
   .din (tick_rw_e),
 
   .din (tick_rw_e),
 
   .q   (tick_rw_m),
 
   .q   (tick_rw_m),
 
   .clk (clk),
 
   .clk (clk),
 
   .se  (se),
 
   .se  (se),
 
   .si  (),
 
   `SIMPLY_RISC_SCANIN,
 
   .so  ()
 
   .so  ()
 
);
 
);
 
 
 
 
 
dff dff_tick_npriv_r_m (
 
dff_s dff_tick_npriv_r_m (
 
   .din (tick_npriv_r_e),
 
   .din (tick_npriv_r_e),
 
   .q   (tick_npriv_r_m),
 
   .q   (tick_npriv_r_m),
 
   .clk (clk),
 
   .clk (clk),
 
   .se  (se),
 
   .se  (se),
 
   .si  (),
 
   `SIMPLY_RISC_SCANIN,
 
   .so  ()
 
   .so  ()
 
);
 
);
 
 
 
 
 
dff dff_tickcmp_rw_m (
 
dff_s dff_tickcmp_rw_m (
 
   .din (tickcmp_rw_e),
 
   .din (tickcmp_rw_e),
 
   .q   (tickcmp_rw_m),
 
   .q   (tickcmp_rw_m),
 
   .clk (clk),
 
   .clk (clk),
 
   .se  (se),
 
   .se  (se),
 
   .si  (),
 
   `SIMPLY_RISC_SCANIN,
 
   .so  ()
 
   .so  ()
 
);
 
);
 
//
 
//
 
// added for timing - moved from hypervisor
 
// added for timing - moved from hypervisor
 
dff dff_htickcmp_rw_m_m (
 
dff_s dff_htickcmp_rw_m_m (
 
    .din (tlu_htickcmp_rw_e),
 
    .din (tlu_htickcmp_rw_e),
 
    .q   (htickcmp_rw_m),
 
    .q   (htickcmp_rw_m),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_tba_rw_m (
 
dff_s dff_tba_rw_m (
 
   .din (tba_rw_e),
 
   .din (tba_rw_e),
 
   .q   (tba_rw_m),
 
   .q   (tba_rw_m),
 
   .clk (clk),
 
   .clk (clk),
 
   .se  (se),
 
   .se  (se),
 
   .si  (),
 
   `SIMPLY_RISC_SCANIN,
 
   .so  ()
 
   .so  ()
 
);
 
);
 
 
 
 
 
dff dff_pstate_rw_m (
 
dff_s dff_pstate_rw_m (
 
   .din (pstate_rw_e),
 
   .din (pstate_rw_e),
 
   .q   (pstate_rw_m),
 
   .q   (pstate_rw_m),
 
   .clk (clk),
 
   .clk (clk),
 
   .se  (se),
 
   .se  (se),
 
   .si  (),
 
   `SIMPLY_RISC_SCANIN,
 
   .so  ()
 
   .so  ()
 
);
 
);
 
 
 
 
 
dff dff_tl_rw_m (
 
dff_s dff_tl_rw_m (
 
    .din (tl_rw_e),
 
    .din (tl_rw_e),
 
    .q   (tl_rw_m),
 
    .q   (tl_rw_m),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_pil_rw_m (
 
dff_s dff_pil_rw_m (
 
    .din (pil_rw_e),
 
    .din (pil_rw_e),
 
    .q   (pil_rw_m),
 
    .q   (pil_rw_m),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_set_sftint_m (
 
dff_s dff_set_sftint_m (
 
    .din (set_sftint_e),
 
    .din (set_sftint_e),
 
    .q   (set_sftint_m),
 
    .q   (set_sftint_m),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_clr_sftint_m (
 
dff_s dff_clr_sftint_m (
 
    .din (clr_sftint_e),
 
    .din (clr_sftint_e),
 
    .q   (clr_sftint_m),
 
    .q   (clr_sftint_m),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_sftint_rg_rw_m (
 
dff_s dff_sftint_rg_rw_m (
 
    .din (sftint_rg_rw_e),
 
    .din (sftint_rg_rw_e),
 
    .q   (sftint_rg_rw_m),
 
    .q   (sftint_rg_rw_m),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_wsr_inst_m (
 
dff_s dff_wsr_inst_m (
 
    .din (wsr_inst_e),
 
    .din (wsr_inst_e),
 
    .q   (wsr_inst_m),
 
    .q   (wsr_inst_m),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
//
 
//
 
// added for hypervisor support
 
// added for hypervisor support
 
dff dff_stickcmp_rw_m (
 
dff_s dff_stickcmp_rw_m (
 
    .din (stickcmp_rw_e),
 
    .din (stickcmp_rw_e),
 
    .q   (stickcmp_rw_m),
 
    .q   (stickcmp_rw_m),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_tpc_rw_g (
 
dff_s dff_tpc_rw_g (
 
    .din (tpc_rw_m),
 
    .din (tpc_rw_m),
 
    .q   (tpc_rw_g),
 
    .q   (tpc_rw_g),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_tnpc_rw_g (
 
dff_s dff_tnpc_rw_g (
 
    .din (tnpc_rw_m),
 
    .din (tnpc_rw_m),
 
    .q   (tnpc_rw_g),
 
    .q   (tnpc_rw_g),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_tstate_rw_g (
 
dff_s dff_tstate_rw_g (
 
    .din (tstate_rw_m),
 
    .din (tstate_rw_m),
 
    .q   (tstate_rw_g),
 
    .q   (tstate_rw_g),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_ttype_rw_g (
 
dff_s dff_ttype_rw_g (
 
    .din (ttype_rw_m),
 
    .din (ttype_rw_m),
 
    .q   (ttype_rw_g),
 
    .q   (ttype_rw_g),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_tick_rw_g (
 
dff_s dff_tick_rw_g (
 
    .din (tick_rw_m),
 
    .din (tick_rw_m),
 
    .q   (tick_rw_g),
 
    .q   (tick_rw_g),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_tick_npriv_r_g (
 
dff_s dff_tick_npriv_r_g (
 
     .din (tick_npriv_r_m),
 
     .din (tick_npriv_r_m),
 
     .q   (tick_npriv_r_g),
 
     .q   (tick_npriv_r_g),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
 
 
 
 
dff dff_tickcmp_rw_g (
 
dff_s dff_tickcmp_rw_g (
 
     .din (tickcmp_rw_m),
 
     .din (tickcmp_rw_m),
 
     .q   (tickcmp_rw_g),
 
     .q   (tickcmp_rw_g),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
//
 
//
 
// added for timing - moved form hyperv
 
// added for timing - moved form hyperv
 
dff dff_htickcmp_rw_m_g (
 
dff_s dff_htickcmp_rw_m_g (
 
    .din (htickcmp_rw_m),
 
    .din (htickcmp_rw_m),
 
    .q   (htickcmp_rw_g),
 
    .q   (htickcmp_rw_g),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_tba_rw_g (
 
dff_s dff_tba_rw_g (
 
     .din (tba_rw_m),
 
     .din (tba_rw_m),
 
     .q   (tba_rw_g),
 
     .q   (tba_rw_g),
 
     .clk (clk),
 
     .clk (clk),
 
     .se  (se),
 
     .se  (se),
 
     .si  (),
 
     `SIMPLY_RISC_SCANIN,
 
     .so  ()
 
     .so  ()
 
);
 
);
 
 
 
 
 
dff dff_pstate_rw_g (
 
dff_s dff_pstate_rw_g (
 
    .din (pstate_rw_m),
 
    .din (pstate_rw_m),
 
    .q   (pstate_rw_g),
 
    .q   (pstate_rw_g),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_pstate_rw_w2 (
 
dff_s dff_pstate_rw_w2 (
 
    .din (pstate_rw_g),
 
    .din (pstate_rw_g),
 
    .q   (pstate_rw_w2),
 
    .q   (pstate_rw_w2),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_tl_rw_g (
 
dff_s dff_tl_rw_g (
 
    .din (tl_rw_m),
 
    .din (tl_rw_m),
 
    .q   (tl_rw_g),
 
    .q   (tl_rw_g),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_tl_rw_w2 (
 
dff_s dff_tl_rw_w2 (
 
    .din (tl_rw_g),
 
    .din (tl_rw_g),
 
    .q   (tl_rw_w2),
 
    .q   (tl_rw_w2),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_pil_rw_g (
 
dff_s dff_pil_rw_g (
 
    .din (pil_rw_m),
 
    .din (pil_rw_m),
 
    .q   (pil_rw_g),
 
    .q   (pil_rw_g),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_tpc_rw_w2 (
 
dff_s dff_tpc_rw_w2 (
 
    .din (tpc_rw_g),
 
    .din (tpc_rw_g),
 
    .q   (tpc_rw_w2),
 
    .q   (tpc_rw_w2),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_tnpc_rw_w2 (
 
dff_s dff_tnpc_rw_w2 (
 
    .din (tnpc_rw_g),
 
    .din (tnpc_rw_g),
 
    .q   (tnpc_rw_w2),
 
    .q   (tnpc_rw_w2),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_tstate_rw_w2 (
 
dff_s dff_tstate_rw_w2 (
 
    .din (tstate_rw_g),
 
    .din (tstate_rw_g),
 
    .q   (tstate_rw_w2),
 
    .q   (tstate_rw_w2),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_ttype_rw_w2 (
 
dff_s dff_ttype_rw_w2 (
 
    .din (ttype_rw_g),
 
    .din (ttype_rw_g),
 
    .q   (ttype_rw_w2),
 
    .q   (ttype_rw_w2),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_htstate_rw_w2 (
 
dff_s dff_htstate_rw_w2 (
 
    .din (tlu_htstate_rw_g),
 
    .din (tlu_htstate_rw_g),
 
    .q   (htstate_rw_w2),
 
    .q   (htstate_rw_w2),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_set_sftint_g (
 
dff_s dff_set_sftint_g (
 
    .din (set_sftint_m),
 
    .din (set_sftint_m),
 
    .q   (set_sftint_g),
 
    .q   (set_sftint_g),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_clr_sftint_g (
 
dff_s dff_clr_sftint_g (
 
    .din (clr_sftint_m),
 
    .din (clr_sftint_m),
 
    .q   (clr_sftint_g),
 
    .q   (clr_sftint_g),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_sftint_rg_rw_g (
 
dff_s dff_sftint_rg_rw_g (
 
    .din (sftint_rg_rw_m),
 
    .din (sftint_rg_rw_m),
 
    .q   (sftint_rg_rw_g),
 
    .q   (sftint_rg_rw_g),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_wsr_inst_g (
 
dff_s dff_wsr_inst_g (
 
    .din (wsr_inst_m),
 
    .din (wsr_inst_m),
 
    .q   (wsr_inst_g_unflushed),
 
    .q   (wsr_inst_g_unflushed),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_wsr_inst_w2 (
 
dff_s dff_wsr_inst_w2 (
 
    .din (wsr_inst_g),
 
    .din (wsr_inst_g),
 
    .q   (wsr_inst_w2),
 
    .q   (wsr_inst_w2),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_tlu_gl_rw_g (
 
dff_s dff_tlu_gl_rw_g (
 
    .din (tlu_gl_rw_m),
 
    .din (tlu_gl_rw_m),
 
    .q   (tlu_gl_rw_g),
 
    .q   (tlu_gl_rw_g),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
//
 
//
 
// added for hypervisor support
 
// added for hypervisor support
 
dff dff_stickcmp_rw_g (
 
dff_s dff_stickcmp_rw_g (
 
    .din (stickcmp_rw_m),
 
    .din (stickcmp_rw_m),
 
    .q   (stickcmp_rw_g),
 
    .q   (stickcmp_rw_g),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
// modified due to timing violations                                            
// modified due to timing violations                                            
// assign       wsr_inst_g = wsr_inst_g_unflushed & ~tlu_ifu_flush_pipe_w & inst_vld_g;
 
// assign       wsr_inst_g = wsr_inst_g_unflushed & ~tlu_ifu_flush_pipe_w & inst_vld_g;
 
assign  wsr_inst_g = wsr_inst_g_unflushed & ~local_early_flush_pipe_w & inst_vld_g;
 
assign  wsr_inst_g = wsr_inst_g_unflushed & ~local_early_flush_pipe_w & inst_vld_g;
Line 5288... Line 4895... 
// modified due to swapping in the incr64 soft macro
 
// modified due to swapping in the incr64 soft macro
 
// assign tckctr_incr = tckctr + 1;
 
// assign tckctr_incr = tckctr + 1;
 
assign tckctr_in[1:0] = tlu_tckctr_in[1:0];
 
assign tckctr_in[1:0] = tlu_tckctr_in[1:0];
 
assign tlu_incr_tick[1:0] = tckctr[1:0];
 
assign tlu_incr_tick[1:0] = tckctr[1:0];
 
 
 
 
 
dffr #(2) dffr_tckctr_cnt (
 
dffr_s #(2) dffr_tckctr_cnt (
 
    .din (tckctr_in[1:0]),
 
    .din (tckctr_in[1:0]),
 
    .q (tckctr[1:0]),
 
    .q (tckctr[1:0]),
 
    .rst (local_rst | ~tlu_tick_en_l),
 
    .rst (local_rst | ~tlu_tick_en_l),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so ()
 
    .so ()
 
);
 
);
 
 
 
 
 
// 3rd cycle, increment tick reg.
 
// 3rd cycle, increment tick reg.
 
// assign       tlu_incr_tick = tckctr[1] & tckctr[0];
 
// assign       tlu_incr_tick = tckctr[1] & tckctr[0];
Line 5312... Line 4919... 
 
 
 
 
// reset should not be needed in this equation !!!
 
// reset should not be needed in this equation !!!
 
assign  tick_ctl_din = tlu_wsr_data_b63_w | local_rst | por_rstint_g;
 
assign  tick_ctl_din = tlu_wsr_data_b63_w | local_rst | por_rstint_g;
 
assign  tlu_tick_ctl_din = tick_ctl_din;
 
assign  tlu_tick_ctl_din = tick_ctl_din;
 
 
 
 
 
dffe dffe_npt0 (
 
dffe_s dffe_npt0 (
 
    .din (tick_ctl_din),
 
    .din (tick_ctl_din),
 
    .q   (tick_npt0),
 
    .q   (tick_npt0),
 
    .en  (tick_en[0]),
 
    .en  (tick_en[0]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dffe dffe_npt1 (
 
dffe_s dffe_npt1 (
 
    .din (tick_ctl_din),
 
    .din (tick_ctl_din),
 
    .q   (tick_npt1),
 
    .q   (tick_npt1),
 
    .en  (tick_en[1]),
 
    .en  (tick_en[1]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dffe dffe_npt2 (
 
dffe_s dffe_npt2 (
 
    .din (tick_ctl_din),
 
    .din (tick_ctl_din),
 
    .q   (tick_npt2),
 
    .q   (tick_npt2),
 
    .en  (tick_en[2]),
 
    .en  (tick_en[2]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dffe dffe_npt3 (
 
dffe_s dffe_npt3 (
 
    .din (tick_ctl_din),
 
    .din (tick_ctl_din),
 
    .q   (tick_npt3),
 
    .q   (tick_npt3),
 
    .en  (tick_en[3]),
 
    .en  (tick_en[3]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
assign  tlu_tick_npt =
 
assign  tlu_tick_npt =
 
        (thread0_rsel_e & tick_npt0) |
 
        (thread0_rsel_e & tick_npt0) |
Line 5389... Line 4996... 
wire    [1:0]    sftintctr;
 
wire    [1:0]    sftintctr;
 
wire    [1:0]    sftintctr_incr;
 
wire    [1:0]    sftintctr_incr;
 
 
 
 
 
assign sftintctr_incr[1:0] = sftintctr[1:0] + 2'b01;
 
assign sftintctr_incr[1:0] = sftintctr[1:0] + 2'b01;
 
 
 
 
 
dffr #(2) dffr_sftint_cnt  (
 
dffr_s #(2) dffr_sftint_cnt  (
 
   .din (sftintctr_incr[1:0]),
 
   .din (sftintctr_incr[1:0]),
 
   .q (sftintctr[1:0]),
 
   .q (sftintctr[1:0]),
 
   .rst (local_rst),
 
   .rst (local_rst),
 
   .clk (clk),
 
   .clk (clk),
 
   .se  (se),
 
   .se  (se),
 
   .si  (),
 
   `SIMPLY_RISC_SCANIN,
 
   .so ()
 
   .so ()
 
);
 
);
 
// 
// 
// modified for bug 4626 and 5117 
// modified for bug 4626 and 5117 
/*
 
/*
Line 5411... Line 5018... 
*/
 
*/
 
 
 
 
 
assign sftint_user_update_g =
 
assign sftint_user_update_g =
 
       clr_sftint_g | sftint_rg_rw_g;
 
       clr_sftint_g | sftint_rg_rw_g;
 
 
 
 
 
dffr dffr_sftint_user_update_w2 (
 
dffr_s dffr_sftint_user_update_w2 (
 
    .din (sftint_user_update_g),
 
    .din (sftint_user_update_g),
 
        .q   (sftint_user_update_w2),
 
        .q   (sftint_user_update_w2),
 
    .clk (clk),
 
    .clk (clk),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
assign penc_sel_user_update = sftint_user_update_w2 & ~swint_g;
 
assign penc_sel_user_update = sftint_user_update_w2 & ~swint_g;
 
 
 
 
Line 5453... Line 5060... 
assign sftint_wait_rst[2] =
 
assign sftint_wait_rst[2] =
 
           sftint_pend_wait[2] & tlu_sftint_penc_sel[2];
 
           sftint_pend_wait[2] & tlu_sftint_penc_sel[2];
 
assign sftint_wait_rst[3] =
 
assign sftint_wait_rst[3] =
 
           sftint_pend_wait[3] & tlu_sftint_penc_sel[3];
 
           sftint_pend_wait[3] & tlu_sftint_penc_sel[3];
 
 
 
 
 
dffr dffr_sftint_pend_wait_0 (
 
dffr_s dffr_sftint_pend_wait_0 (
 
    .din (sftint_user_update_g & thread0_rsel_dec_g),
 
    .din (sftint_user_update_g & thread0_rsel_dec_g),
 
        .q   (sftint_pend_wait[0]),
 
        .q   (sftint_pend_wait[0]),
 
    .clk (clk),
 
    .clk (clk),
 
    .rst (local_rst | sftint_wait_rst[0]),
 
    .rst (local_rst | sftint_wait_rst[0]),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
dffr dffr_sftint_pend_wait_1 (
 
dffr_s dffr_sftint_pend_wait_1 (
 
    .din (sftint_user_update_g & thread1_rsel_dec_g),
 
    .din (sftint_user_update_g & thread1_rsel_dec_g),
 
        .q   (sftint_pend_wait[1]),
 
        .q   (sftint_pend_wait[1]),
 
    .clk (clk),
 
    .clk (clk),
 
    .rst (local_rst | sftint_wait_rst[1]),
 
    .rst (local_rst | sftint_wait_rst[1]),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dffr dffr_sftint_pend_wait_2 (
 
dffr_s dffr_sftint_pend_wait_2 (
 
    .din (sftint_user_update_g & thread2_rsel_dec_g),
 
    .din (sftint_user_update_g & thread2_rsel_dec_g),
 
        .q   (sftint_pend_wait[2]),
 
        .q   (sftint_pend_wait[2]),
 
    .clk (clk),
 
    .clk (clk),
 
    .rst (local_rst | sftint_wait_rst[2]),
 
    .rst (local_rst | sftint_wait_rst[2]),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dffr dffr_sftint_pend_wait_3 (
 
dffr_s dffr_sftint_pend_wait_3 (
 
    .din (sftint_user_update_g & thread3_rsel_dec_g),
 
    .din (sftint_user_update_g & thread3_rsel_dec_g),
 
        .q   (sftint_pend_wait[3]),
 
        .q   (sftint_pend_wait[3]),
 
    .clk (clk),
 
    .clk (clk),
 
    .rst (local_rst | sftint_wait_rst[3]),
 
    .rst (local_rst | sftint_wait_rst[3]),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
/*
 
/*
 
assign  tlu_sftint_penc_sel[0] =
 
assign  tlu_sftint_penc_sel[0] =
 
            (~sftintctr[1] & ~sftintctr[0] & ~swint_nq_g) | swint_thrd_g[0];
 
            (~sftintctr[1] & ~sftintctr[0] & ~swint_nq_g) | swint_thrd_g[0];
Line 5514... Line 5121... 
assign  tlu_sftint_penc_sel[2] =  sftintctr[1] & ~sftintctr[0];
 
assign  tlu_sftint_penc_sel[2] =  sftintctr[1] & ~sftintctr[0];
 
assign  tlu_sftint_penc_sel[3] =  sftintctr[1] &  sftintctr[0];
 
assign  tlu_sftint_penc_sel[3] =  sftintctr[1] &  sftintctr[0];
 
*/
 
*/
 
 
 
 
 
//  Flop sftint values on a per thread basis.
 
//  Flop sftint values on a per thread basis.
 
dffe #(4) dffe_sftint_id0  (
 
dffe_s #(4) dffe_sftint_id0  (
 
    .din (tlu_sftint_id[3:0]),
 
    .din (tlu_sftint_id[3:0]),
 
    .q   (sftint0_id[3:0]),
 
    .q   (sftint0_id[3:0]),
 
    .en  (tlu_sftint_penc_sel[0]),
 
    .en  (tlu_sftint_penc_sel[0]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dffe #(4) dffe_sftint_id1  (
 
dffe_s #(4) dffe_sftint_id1  (
 
    .din (tlu_sftint_id[3:0]),
 
    .din (tlu_sftint_id[3:0]),
 
    .q   (sftint1_id[3:0]),
 
    .q   (sftint1_id[3:0]),
 
    .en  (tlu_sftint_penc_sel[1]),
 
    .en  (tlu_sftint_penc_sel[1]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dffe #(4) dffe_sftint_id2  (
 
dffe_s #(4) dffe_sftint_id2  (
 
    .din (tlu_sftint_id[3:0]),
 
    .din (tlu_sftint_id[3:0]),
 
    .q   (sftint2_id[3:0]),
 
    .q   (sftint2_id[3:0]),
 
    .en  (tlu_sftint_penc_sel[2]),
 
    .en  (tlu_sftint_penc_sel[2]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dffe #(4) dffe_sftint_id3  (
 
dffe_s #(4) dffe_sftint_id3  (
 
    .din (tlu_sftint_id[3:0]),
 
    .din (tlu_sftint_id[3:0]),
 
    .q   (sftint3_id[3:0]),
 
    .q   (sftint3_id[3:0]),
 
    .en  (tlu_sftint_penc_sel[3]),
 
    .en  (tlu_sftint_penc_sel[3]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
// Soft Int Control
 
// Soft Int Control
 
// modified to fix one-hot problem
 
// modified to fix one-hot problem
Line 5736... Line 5343... 
 
 
 
 
assign  tick_int_en[3] = ~tlu_sftint_en_l_g[3] | tick_intrpt[3];
 
assign  tick_int_en[3] = ~tlu_sftint_en_l_g[3] | tick_intrpt[3];
 
assign  tick_int_din[3] = (tick_intrpt[3] | wsr_tick_intset_g) ? 1'b1 : 1'b0;
 
assign  tick_int_din[3] = (tick_intrpt[3] | wsr_tick_intset_g) ? 1'b1 : 1'b0;
 
//
 
//
 
// recoded tlu_tick_int for bug 818
 
// recoded tlu_tick_int for bug 818
 
dffre dffre_tick_int0 (
 
dffre_s dffre_tick_int0 (
 
    .din (tick_int_din[0]),
 
    .din (tick_int_din[0]),
 
    .q   (tlu_tick_int[0]),
 
    .q   (tlu_tick_int[0]),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .en  (tick_int_en[0]),
 
    .en  (tick_int_en[0]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
//
 
//
 
// recoded tlu_tick_int for bug 818
 
// recoded tlu_tick_int for bug 818
 
dffre dffre_tick_int1 (
 
dffre_s dffre_tick_int1 (
 
    .din (tick_int_din[1]),
 
    .din (tick_int_din[1]),
 
    .q   (tlu_tick_int[1]),
 
    .q   (tlu_tick_int[1]),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .en  (tick_int_en[1]),
 
    .en  (tick_int_en[1]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
// recoded tlu_tick_int for bug 818
 
// recoded tlu_tick_int for bug 818
 
//
 
//
 
dffre dffre_tick_int2 (
 
dffre_s dffre_tick_int2 (
 
    .din (tick_int_din[2]),
 
    .din (tick_int_din[2]),
 
    .q   (tlu_tick_int[2]),
 
    .q   (tlu_tick_int[2]),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .en  (tick_int_en[2]),
 
    .en  (tick_int_en[2]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
//
 
//
 
// recoded tlu_tick_int for bug 818
 
// recoded tlu_tick_int for bug 818
 
dffre dffre_tick_int3 (
 
dffre_s dffre_tick_int3 (
 
    .din (tick_int_din[3]),
 
    .din (tick_int_din[3]),
 
    .q   (tlu_tick_int[3]),
 
    .q   (tlu_tick_int[3]),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .en  (tick_int_en[3]),
 
    .en  (tick_int_en[3]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
*/
 
*/
 
//
 
//
 
// added and/or modified for hypervisor support
 
// added and/or modified for hypervisor support
Line 5819... Line 5426... 
assign  stick_int_en[3] = ~tlu_sftint_en_l_g[3] | stick_intrpt[3];
 
assign  stick_int_en[3] = ~tlu_sftint_en_l_g[3] | stick_intrpt[3];
 
assign  stick_int_din[3] = (stick_intrpt[3] | wsr_stick_intset_g) ? 1'b1 : 1'b0;
 
assign  stick_int_din[3] = (stick_intrpt[3] | wsr_stick_intset_g) ? 1'b1 : 1'b0;
 
 
 
 
 
// recoded tlu_tick_int for bug 818
 
// recoded tlu_tick_int for bug 818
 
//
 
//
 
dffre dffre_stick_int0 (
 
dffre_s dffre_stick_int0 (
 
    .din (stick_int_din[0]),
 
    .din (stick_int_din[0]),
 
    .q   (tlu_stick_int[0]),
 
    .q   (tlu_stick_int[0]),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .en  (stick_int_en[0]),
 
    .en  (stick_int_en[0]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
//
 
//
 
dffre dffre_stick_int1 (
 
dffre_s dffre_stick_int1 (
 
    .din (stick_int_din[1]),
 
    .din (stick_int_din[1]),
 
    .q   (tlu_stick_int[1]),
 
    .q   (tlu_stick_int[1]),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .en  (stick_int_en[1]),
 
    .en  (stick_int_en[1]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
//
 
//
 
dffre dffre_stick_int2  (
 
dffre_s dffre_stick_int2  (
 
    .din (stick_int_din[2]),
 
    .din (stick_int_din[2]),
 
    .q   (tlu_stick_int[2]),
 
    .q   (tlu_stick_int[2]),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .en  (stick_int_en[2]),
 
    .en  (stick_int_en[2]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so ()
 
    .so ()
 
);
 
);
 
//
 
//
 
dffre dffre_stick_int3 (
 
dffre_s dffre_stick_int3 (
 
    .din (stick_int_din[3]),
 
    .din (stick_int_din[3]),
 
    .q   (tlu_stick_int[3]),
 
    .q   (tlu_stick_int[3]),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .en  (stick_int_en[3]),
 
    .en  (stick_int_en[3]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
// modified for hypervisor support
 
// modified for hypervisor support
 
//
 
//
 
assign  tlu_sftint_lvl14_all[0] =
 
assign  tlu_sftint_lvl14_all[0] =
Line 5889... Line 5496... 
assign  pil1_en = pil_rw_g & wsr_inst_g & thread1_wsel_g;
 
assign  pil1_en = pil_rw_g & wsr_inst_g & thread1_wsel_g;
 
assign  pil2_en = pil_rw_g & wsr_inst_g & thread2_wsel_g;
 
assign  pil2_en = pil_rw_g & wsr_inst_g & thread2_wsel_g;
 
assign  pil3_en = pil_rw_g & wsr_inst_g & thread3_wsel_g;
 
assign  pil3_en = pil_rw_g & wsr_inst_g & thread3_wsel_g;
 
 
 
 
 
// THREAD 0
 
// THREAD 0
 
dffe #(4) dffe_pil0 (
 
dffe_s #(4) dffe_pil0 (
 
    .din (tlu_wsr_data_w[3:0]),
 
    .din (tlu_wsr_data_w[3:0]),
 
    .q   (true_pil0[3:0]),
 
    .q   (true_pil0[3:0]),
 
    .en  (pil0_en),
 
    .en  (pil0_en),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
// 
// 
// THREAD 1
 
// THREAD 1
 
dffe #(4) dffe_pil1 (
 
dffe_s #(4) dffe_pil1 (
 
    .din (tlu_wsr_data_w[3:0]),
 
    .din (tlu_wsr_data_w[3:0]),
 
    .q   (true_pil1[3:0]),
 
    .q   (true_pil1[3:0]),
 
    .en  (pil1_en),
 
    .en  (pil1_en),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
// 
// 
// THREAD 2
 
// THREAD 2
 
dffe #(4) dffe_pil2 (
 
dffe_s #(4) dffe_pil2 (
 
    .din (tlu_wsr_data_w[3:0]),
 
    .din (tlu_wsr_data_w[3:0]),
 
    .q   (true_pil2[3:0]),
 
    .q   (true_pil2[3:0]),
 
    .en  (pil2_en),
 
    .en  (pil2_en),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
//
 
//
 
// THREAD 3
 
// THREAD 3
 
dffe #(4) dffe_pil3 (
 
dffe_s #(4) dffe_pil3 (
 
    .din (tlu_wsr_data_w[3:0]),
 
    .din (tlu_wsr_data_w[3:0]),
 
    .q   (true_pil3[3:0]),
 
    .q   (true_pil3[3:0]),
 
    .en  (pil3_en),
 
    .en  (pil3_en),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
//=========================================================================================
 
//=========================================================================================
 
//      TL for Threads
 
//      TL for Threads
 
//=========================================================================================
 
//=========================================================================================
 
//
 
//
 
dff dff_stgim_g (
 
dff_s dff_stgim_g (
 
    .din (ifu_tlu_immu_miss_m),
 
    .din (ifu_tlu_immu_miss_m),
 
    .q  (immu_miss_g),
 
    .q  (immu_miss_g),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
// wrpr supplies new value else increment on trap.
 
// wrpr supplies new value else increment on trap.
 
// wrpr %tl when tl=0 will cause a trap.
 
// wrpr %tl when tl=0 will cause a trap.
 
// trap in MAXTL-1 enters RED_MODE. 
// trap in MAXTL-1 enters RED_MODE. 
// added for hypervisor support
 
// added for hypervisor support
 
// capped the tl value by supervisor write at MAXSTL 
// capped the tl value by supervisor write at MAXSTL 
//
 
//
 
assign maxstl_wr_sel[0] =
 
assign maxstl_wr_sel[0] =
 
           ~tlu_hyper_lite[0] & (tlu_wsr_data_w[2:0] > 3'b010);
 
           ~tlu_hyper_lite[0] & (tlu_wsr_data_w[2:0] > `MAXSTL);
 
assign maxstl_wr_sel[1] =
 
assign maxstl_wr_sel[1] =
 
           ~tlu_hyper_lite[1] & (tlu_wsr_data_w[2:0] > 3'b010);
 
           ~tlu_hyper_lite[1] & (tlu_wsr_data_w[2:0] > `MAXSTL);
 
assign maxstl_wr_sel[2] =
 
assign maxstl_wr_sel[2] =
 
           ~tlu_hyper_lite[2] & (tlu_wsr_data_w[2:0] > 3'b010);
 
           ~tlu_hyper_lite[2] & (tlu_wsr_data_w[2:0] > `MAXSTL);
 
assign maxstl_wr_sel[3] =
 
assign maxstl_wr_sel[3] =
 
           ~tlu_hyper_lite[3] & (tlu_wsr_data_w[2:0] > 3'b010);
 
           ~tlu_hyper_lite[3] & (tlu_wsr_data_w[2:0] > `MAXSTL);
 
 
 
 
 
assign maxtl_wr_sel =  (tlu_wsr_data_w[2:0] == 3'b111);
 
assign maxtl_wr_sel =  (tlu_wsr_data_w[2:0] == 3'b111);
 
 
 
 
 
// THREAD0
 
// THREAD0
 
// Use to signal page fault for now.
 
// Use to signal page fault for now.
Line 5976... Line 5583... 
            (pending_trap_sel[0] & ~(dnrtry_inst_g | tsa_wr_tid_sel_g |
 
            (pending_trap_sel[0] & ~(dnrtry_inst_g | tsa_wr_tid_sel_g |
 
             ifu_thrd_flush_w[0] | cwp_cmplt0_pending | sync_trap_taken_g |
 
             ifu_thrd_flush_w[0] | cwp_cmplt0_pending | sync_trap_taken_g |
 
            (tlu_gl_rw_g & wsr_inst_g)));
 
            (tlu_gl_rw_g & wsr_inst_g)));
 
//
 
//
 
// trap level will get updated next cycle.
 
// trap level will get updated next cycle.
 
dff #(1) dff_stgw2_0 (
 
dff_s #(1) dff_stgw2_0 (
 
    .din (thrd0_traps),
 
    .din (thrd0_traps),
 
    .q   (thrd0_traps_w2),
 
    .q   (thrd0_traps_w2),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
assign tlu_thrd_traps_w2[0] = thrd0_traps_w2;
 
assign tlu_thrd_traps_w2[0] = thrd0_traps_w2;
 
 
 
 
 
assign  trp_lvl0_at_maxtl = (trp_lvl0[2:0] == 3'b110);
 
assign  trp_lvl0_at_maxtl = (trp_lvl0[2:0] == `MAXTL);
 
assign  trp_lvl0_at_maxtlless1 = (trp_lvl0[2:0] == 3'b101);
 
assign  trp_lvl0_at_maxtlless1 = (trp_lvl0[2:0] == `MAXTL_LESSONE);
 
//
 
//
 
// added for modified for hypervisor support
 
// added for modified for hypervisor support
 
assign trp_lvl_at_maxstl[0]   = (trp_lvl0[2:0] == 3'b010);
 
assign trp_lvl_at_maxstl[0]   = (trp_lvl0[2:0] == `MAXSTL);
 
assign trp_lvl_gte_maxstl[0]  = (trp_lvl0[2:0] > 3'b010) | trp_lvl_at_maxstl[0];
 
assign trp_lvl_gte_maxstl[0]  = (trp_lvl0[2:0] > `MAXSTL) | trp_lvl_at_maxstl[0];
 
assign wsr_trp_lvl0_data_w[2:0] =
 
assign wsr_trp_lvl0_data_w[2:0] =
 
           (maxstl_wr_sel[0])? 3'b010:
 
           (maxstl_wr_sel[0])? `MAXSTL_TL:
 
           ((maxtl_wr_sel)? 3'b110: tlu_wsr_data_w[2:0]);
 
           ((maxtl_wr_sel)? `MAXTL: tlu_wsr_data_w[2:0]);
 
//
 
//
 
// added for timing
 
// added for timing
 
dff #(3) dff_wsr_trp_lvl0_data_w2 (
 
dff_s #(3) dff_wsr_trp_lvl0_data_w2 (
 
    .din (wsr_trp_lvl0_data_w[2:0]),
 
    .din (wsr_trp_lvl0_data_w[2:0]),
 
    .q   (wsr_trp_lvl0_data_w2[2:0]),
 
    .q   (wsr_trp_lvl0_data_w2[2:0]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
//=========================================================================================
 
//=========================================================================================
 
// The following section has been recoded due to timing
 
// The following section has been recoded due to timing
Line 6016... Line 5623... 
assign  trp_lvl0_incr_w2 = thrd0_traps_w2 & ~trp_lvl0_at_maxtl;
 
assign  trp_lvl0_incr_w2 = thrd0_traps_w2 & ~trp_lvl0_at_maxtl;
 
 
 
 
 
assign trp_lvl0_new[2:0] =
 
assign trp_lvl0_new[2:0] =
 
           (tl_rw_w2 & wsr_inst_w2 & thread0_wsel_w2) ?
 
           (tl_rw_w2 & wsr_inst_w2 & thread0_wsel_w2) ?
 
                        wsr_trp_lvl0_data_w2[2:0] :
 
                        wsr_trp_lvl0_data_w2[2:0] :
 
                        (local_rst | por_rstint0_w2) ? 3'b110 :
 
                        (local_rst | por_rstint0_w2) ? `MAXTL :
 
                        (dnrtry_inst_w2[0]) ?
 
                        (dnrtry_inst_w2[0]) ?
 
                                trp_lvl0[2:0] - 3'b001:// done/retry decrements
 
                                trp_lvl0[2:0] - 3'b001:// done/retry decrements
 
                                trp_lvl0[2:0] + {2'b00,trp_lvl0_incr_w2};// trap increments
 
                                trp_lvl0[2:0] + {2'b00,trp_lvl0_incr_w2};// trap increments
 
assign tl0_en =
 
assign tl0_en =
 
           (tl_rw_w2 & wsr_inst_w2 & thread0_wsel_w2) |
 
           (tl_rw_w2 & wsr_inst_w2 & thread0_wsel_w2) |
 
                        trp_lvl0_incr_w2| local_rst | por_rstint0_w2 |
 
                        trp_lvl0_incr_w2| local_rst | por_rstint0_w2 |
 
            dnrtry_inst_w2[0];
 
            dnrtry_inst_w2[0];
 
 
 
 
 
// Reset required as processor will start out at tl0 after reset.
 
// Reset required as processor will start out at tl0 after reset.
 
// tl has to be correctly defined for all conditions !!!
 
// tl has to be correctly defined for all conditions !!!
 
dffe #(3) dffe_tl0 (
 
dffe_s #(3) dffe_tl0 (
 
    .din (trp_lvl0_new[2:0]),
 
    .din (trp_lvl0_new[2:0]),
 
    .q   (trp_lvl0[2:0]),
 
    .q   (trp_lvl0[2:0]),
 
    .en  (tl0_en),
 
    .en  (tl0_en),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
assign  tlu_lsu_tl_zero[0] = ~trp_lvl0[2] & ~trp_lvl0[1] & ~trp_lvl0[0];
 
assign  tlu_lsu_tl_zero[0] = ~trp_lvl0[2] & ~trp_lvl0[1] & ~trp_lvl0[0];
 
assign  tl0_gt_0 = trp_lvl0[2] | trp_lvl0[1] | trp_lvl0[0];
 
assign  tl0_gt_0 = trp_lvl0[2] | trp_lvl0[1] | trp_lvl0[0];
 
//
 
//
Line 6052... Line 5659... 
            (pending_trap_sel[1] & ~(dnrtry_inst_g | tsa_wr_tid_sel_g |
 
            (pending_trap_sel[1] & ~(dnrtry_inst_g | tsa_wr_tid_sel_g |
 
             ifu_thrd_flush_w[1] | cwp_cmplt1_pending | sync_trap_taken_g |
 
             ifu_thrd_flush_w[1] | cwp_cmplt1_pending | sync_trap_taken_g |
 
            (tlu_gl_rw_g & wsr_inst_g)));
 
            (tlu_gl_rw_g & wsr_inst_g)));
 
//
 
//
 
// trap level will get updated next cycle.
 
// trap level will get updated next cycle.
 
dff #(1) dff_stgw2_1 (
 
dff_s #(1) dff_stgw2_1 (
 
    .din (thrd1_traps),
 
    .din (thrd1_traps),
 
    .q  (thrd1_traps_w2),
 
    .q  (thrd1_traps_w2),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so ()
 
    .so ()
 
);
 
);
 
 
 
 
 
assign tlu_thrd_traps_w2[1] = thrd1_traps_w2;
 
assign tlu_thrd_traps_w2[1] = thrd1_traps_w2;
 
 
 
 
 
assign  trp_lvl1_at_maxtl = (trp_lvl1[2:0] == 3'b110);
 
assign  trp_lvl1_at_maxtl = (trp_lvl1[2:0] == `MAXTL);
 
assign  trp_lvl1_at_maxtlless1 = (trp_lvl1[2:0] == 3'b101);
 
assign  trp_lvl1_at_maxtlless1 = (trp_lvl1[2:0] == `MAXTL_LESSONE);
 
//
 
//
 
// added for modified for hypervisor support
 
// added for modified for hypervisor support
 
assign trp_lvl_at_maxstl[1]   = (trp_lvl1[2:0] == 3'b010);
 
assign trp_lvl_at_maxstl[1]   = (trp_lvl1[2:0] == `MAXSTL);
 
assign trp_lvl_gte_maxstl[1]  = (trp_lvl1[2:0] > 3'b010) | trp_lvl_at_maxstl[1];
 
assign trp_lvl_gte_maxstl[1]  = (trp_lvl1[2:0] > `MAXSTL) | trp_lvl_at_maxstl[1];
 
assign wsr_trp_lvl1_data_w[2:0] =
 
assign wsr_trp_lvl1_data_w[2:0] =
 
           (maxstl_wr_sel[1])? 3'b010:
 
           (maxstl_wr_sel[1])? `MAXSTL_TL:
 
           ((maxtl_wr_sel)? 3'b110: tlu_wsr_data_w[2:0]);
 
           ((maxtl_wr_sel)? `MAXTL: tlu_wsr_data_w[2:0]);
 
//
 
//
 
// added for timing
 
// added for timing
 
dff #(3) dff_wsr_trp_lvl1_data_w2 (
 
dff_s #(3) dff_wsr_trp_lvl1_data_w2 (
 
    .din (wsr_trp_lvl1_data_w[2:0]),
 
    .din (wsr_trp_lvl1_data_w[2:0]),
 
    .q   (wsr_trp_lvl1_data_w2[2:0]),
 
    .q   (wsr_trp_lvl1_data_w2[2:0]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
//=========================================================================================
 
//=========================================================================================
 
// The following section has been recoded due to timing
 
// The following section has been recoded due to timing
Line 6092... Line 5699... 
assign  trp_lvl1_incr_w2 = thrd1_traps_w2 & ~trp_lvl1_at_maxtl;
 
assign  trp_lvl1_incr_w2 = thrd1_traps_w2 & ~trp_lvl1_at_maxtl;
 
 
 
 
 
assign trp_lvl1_new[2:0] =
 
assign trp_lvl1_new[2:0] =
 
           (tl_rw_w2 & wsr_inst_w2 & thread1_wsel_w2) ?
 
           (tl_rw_w2 & wsr_inst_w2 & thread1_wsel_w2) ?
 
                        wsr_trp_lvl1_data_w2[2:0] :
 
                        wsr_trp_lvl1_data_w2[2:0] :
 
                        (local_rst | por_rstint1_w2) ? 3'b110 :
 
                        (local_rst | por_rstint1_w2) ? `MAXTL :
 
                        (dnrtry_inst_w2[1]) ?
 
                        (dnrtry_inst_w2[1]) ?
 
                                trp_lvl1[2:0] - 3'b001:// done/retry decrements
 
                                trp_lvl1[2:0] - 3'b001:// done/retry decrements
 
                                trp_lvl1[2:0] + {2'b00,trp_lvl1_incr_w2};// trap increments
 
                                trp_lvl1[2:0] + {2'b00,trp_lvl1_incr_w2};// trap increments
 
assign tl1_en =
 
assign tl1_en =
 
           (tl_rw_w2 & wsr_inst_w2 & thread1_wsel_w2) |
 
           (tl_rw_w2 & wsr_inst_w2 & thread1_wsel_w2) |
 
                        trp_lvl1_incr_w2| local_rst | por_rstint1_w2 |
 
                        trp_lvl1_incr_w2| local_rst | por_rstint1_w2 |
 
            dnrtry_inst_w2[1];
 
            dnrtry_inst_w2[1];
 
 
 
 
 
// Reset required as processor will start out at tl1 after reset.
 
// Reset required as processor will start out at tl1 after reset.
 
// tl has to be correctly defined for all conditions !!!
 
// tl has to be correctly defined for all conditions !!!
 
dffe #(3) dffe_tl1 (
 
dffe_s #(3) dffe_tl1 (
 
    .din (trp_lvl1_new[2:0]),
 
    .din (trp_lvl1_new[2:0]),
 
    .q   (trp_lvl1[2:0]),
 
    .q   (trp_lvl1[2:0]),
 
    .en  (tl1_en),
 
    .en  (tl1_en),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
assign  tlu_lsu_tl_zero[1] = ~trp_lvl1[2] & ~trp_lvl1[1] & ~trp_lvl1[0];
 
assign  tlu_lsu_tl_zero[1] = ~trp_lvl1[2] & ~trp_lvl1[1] & ~trp_lvl1[0];
 
assign  tl1_gt_0 = trp_lvl1[2] | trp_lvl1[1] | trp_lvl1[0];
 
assign  tl1_gt_0 = trp_lvl1[2] | trp_lvl1[1] | trp_lvl1[0];
 
//
 
//
Line 6129... Line 5736... 
            (pending_trap_sel[2] & ~(dnrtry_inst_g | tsa_wr_tid_sel_g |
 
            (pending_trap_sel[2] & ~(dnrtry_inst_g | tsa_wr_tid_sel_g |
 
             ifu_thrd_flush_w[2] | cwp_cmplt2_pending | sync_trap_taken_g |
 
             ifu_thrd_flush_w[2] | cwp_cmplt2_pending | sync_trap_taken_g |
 
             (tlu_gl_rw_g & wsr_inst_g)));
 
             (tlu_gl_rw_g & wsr_inst_g)));
 
 
 
 
 
// trap level will get updated next cycle.
 
// trap level will get updated next cycle.
 
dff #(1) dff_stgw2_2 (
 
dff_s #(1) dff_stgw2_2 (
 
    .din (thrd2_traps),
 
    .din (thrd2_traps),
 
    .q   (thrd2_traps_w2),
 
    .q   (thrd2_traps_w2),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
assign tlu_thrd_traps_w2[2] = thrd2_traps_w2;
 
assign tlu_thrd_traps_w2[2] = thrd2_traps_w2;
 
 
 
 
 
assign  trp_lvl2_at_maxtl = (trp_lvl2[2:0] == 3'b110);
 
assign  trp_lvl2_at_maxtl = (trp_lvl2[2:0] == `MAXTL);
 
assign  trp_lvl2_at_maxtlless1 = (trp_lvl2[2:0] == 3'b101);
 
assign  trp_lvl2_at_maxtlless1 = (trp_lvl2[2:0] == `MAXTL_LESSONE);
 
//
 
//
 
// added or modified for hypervisor support
 
// added or modified for hypervisor support
 
assign trp_lvl_at_maxstl[2]   = (trp_lvl2[2:0] == 3'b010);
 
assign trp_lvl_at_maxstl[2]   = (trp_lvl2[2:0] == `MAXSTL);
 
assign trp_lvl_gte_maxstl[2]  = (trp_lvl2[2:0] > 3'b010) | trp_lvl_at_maxstl[2];
 
assign trp_lvl_gte_maxstl[2]  = (trp_lvl2[2:0] > `MAXSTL) | trp_lvl_at_maxstl[2];
 
assign wsr_trp_lvl2_data_w[2:0] =
 
assign wsr_trp_lvl2_data_w[2:0] =
 
           (maxstl_wr_sel[2])? 3'b010:
 
           (maxstl_wr_sel[2])? `MAXSTL_TL:
 
           ((maxtl_wr_sel)? 3'b110: tlu_wsr_data_w[2:0]);
 
           ((maxtl_wr_sel)? `MAXTL: tlu_wsr_data_w[2:0]);
 
//
 
//
 
// added for timing
 
// added for timing
 
dff #(3) dff_wsr_trp_lvl2_data_w2 (
 
dff_s #(3) dff_wsr_trp_lvl2_data_w2 (
 
    .din (wsr_trp_lvl2_data_w[2:0]),
 
    .din (wsr_trp_lvl2_data_w[2:0]),
 
    .q   (wsr_trp_lvl2_data_w2[2:0]),
 
    .q   (wsr_trp_lvl2_data_w2[2:0]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
//=========================================================================================
 
//=========================================================================================
 
// The following section has been recoded due to timing
 
// The following section has been recoded due to timing
Line 6169... Line 5776... 
assign  trp_lvl2_incr_w2 = thrd2_traps_w2 & ~trp_lvl2_at_maxtl;
 
assign  trp_lvl2_incr_w2 = thrd2_traps_w2 & ~trp_lvl2_at_maxtl;
 
 
 
 
 
assign trp_lvl2_new[2:0] =
 
assign trp_lvl2_new[2:0] =
 
           (tl_rw_w2 & wsr_inst_w2 & thread2_wsel_w2) ?
 
           (tl_rw_w2 & wsr_inst_w2 & thread2_wsel_w2) ?
 
                        wsr_trp_lvl2_data_w2[2:0] :
 
                        wsr_trp_lvl2_data_w2[2:0] :
 
                        (local_rst | por_rstint2_w2) ? 3'b110 :
 
                        (local_rst | por_rstint2_w2) ? `MAXTL :
 
                        (dnrtry_inst_w2[2]) ?
 
                        (dnrtry_inst_w2[2]) ?
 
                                trp_lvl2[2:0] - 3'b001:// done/retry decrements
 
                                trp_lvl2[2:0] - 3'b001:// done/retry decrements
 
                                trp_lvl2[2:0] + {2'b00,trp_lvl2_incr_w2};// trap increments
 
                                trp_lvl2[2:0] + {2'b00,trp_lvl2_incr_w2};// trap increments
 
assign tl2_en =
 
assign tl2_en =
 
           (tl_rw_w2 & wsr_inst_w2 & thread2_wsel_w2) |
 
           (tl_rw_w2 & wsr_inst_w2 & thread2_wsel_w2) |
 
                        trp_lvl2_incr_w2| local_rst | por_rstint2_w2 |
 
                        trp_lvl2_incr_w2| local_rst | por_rstint2_w2 |
 
            dnrtry_inst_w2[2];
 
            dnrtry_inst_w2[2];
 
 
 
 
 
// Reset required as processor will start out at tl1 after reset.
 
// Reset required as processor will start out at tl1 after reset.
 
// tl has to be correctly defined for all conditions !!!
 
// tl has to be correctly defined for all conditions !!!
 
dffe #(3) dffe_tl2 (
 
dffe_s #(3) dffe_tl2 (
 
    .din (trp_lvl2_new[2:0]),
 
    .din (trp_lvl2_new[2:0]),
 
    .q   (trp_lvl2[2:0]),
 
    .q   (trp_lvl2[2:0]),
 
    .en  (tl2_en),
 
    .en  (tl2_en),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
assign  tlu_lsu_tl_zero[2] = ~trp_lvl2[2] & ~trp_lvl2[1] & ~trp_lvl2[0];
 
assign  tlu_lsu_tl_zero[2] = ~trp_lvl2[2] & ~trp_lvl2[1] & ~trp_lvl2[0];
 
assign  tl2_gt_0 = trp_lvl2[2] | trp_lvl2[1] | trp_lvl2[0];
 
assign  tl2_gt_0 = trp_lvl2[2] | trp_lvl2[1] | trp_lvl2[0];
 
//
 
//
Line 6205... Line 5812... 
            (pending_trap_sel[3] & ~(dnrtry_inst_g | tsa_wr_tid_sel_g |
 
            (pending_trap_sel[3] & ~(dnrtry_inst_g | tsa_wr_tid_sel_g |
 
             ifu_thrd_flush_w[3] | cwp_cmplt3_pending | sync_trap_taken_g |
 
             ifu_thrd_flush_w[3] | cwp_cmplt3_pending | sync_trap_taken_g |
 
            (tlu_gl_rw_g & wsr_inst_g)));
 
            (tlu_gl_rw_g & wsr_inst_g)));
 
 
 
 
 
// trap level will get updated next cycle.
 
// trap level will get updated next cycle.
 
dff #(1) dff_stgw2_3 (
 
dff_s #(1) dff_stgw2_3 (
 
    .din (thrd3_traps),
 
    .din (thrd3_traps),
 
    .q   (thrd3_traps_w2),
 
    .q   (thrd3_traps_w2),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so ()
 
    .so ()
 
);
 
);
 
 
 
 
 
assign tlu_thrd_traps_w2[3] = thrd3_traps_w2;
 
assign tlu_thrd_traps_w2[3] = thrd3_traps_w2;
 
 
 
 
 
assign  trp_lvl3_at_maxtl = (trp_lvl3[2:0] == 3'b110);
 
assign  trp_lvl3_at_maxtl = (trp_lvl3[2:0] == `MAXTL);
 
assign  trp_lvl3_at_maxtlless1 = (trp_lvl3[2:0] == 3'b101);
 
assign  trp_lvl3_at_maxtlless1 = (trp_lvl3[2:0] == `MAXTL_LESSONE);
 
//
 
//
 
// added for modified for hypervisor support
 
// added for modified for hypervisor support
 
assign trp_lvl_at_maxstl[3]   = (trp_lvl3[2:0] == 3'b010);
 
assign trp_lvl_at_maxstl[3]   = (trp_lvl3[2:0] == `MAXSTL);
 
assign trp_lvl_gte_maxstl[3]  = (trp_lvl3[2:0] > 3'b010) | trp_lvl_at_maxstl[3];
 
assign trp_lvl_gte_maxstl[3]  = (trp_lvl3[2:0] > `MAXSTL) | trp_lvl_at_maxstl[3];
 
assign wsr_trp_lvl3_data_w[2:0] =
 
assign wsr_trp_lvl3_data_w[2:0] =
 
           (maxstl_wr_sel[3])? 3'b010:
 
           (maxstl_wr_sel[3])? `MAXSTL_TL:
 
           ((maxtl_wr_sel)? 3'b110: tlu_wsr_data_w[2:0]);
 
           ((maxtl_wr_sel)? `MAXTL: tlu_wsr_data_w[2:0]);
 
//
 
//
 
// added for timing
 
// added for timing
 
dff #(3) dff_wsr_trp_lvl3_data_w2 (
 
dff_s #(3) dff_wsr_trp_lvl3_data_w2 (
 
    .din (wsr_trp_lvl3_data_w[2:0]),
 
    .din (wsr_trp_lvl3_data_w[2:0]),
 
    .q   (wsr_trp_lvl3_data_w2[2:0]),
 
    .q   (wsr_trp_lvl3_data_w2[2:0]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
//=========================================================================================
 
//=========================================================================================
 
// The following section has been recoded due to timing
 
// The following section has been recoded due to timing
Line 6245... Line 5852... 
assign  trp_lvl3_incr_w2 = thrd3_traps_w2 & ~trp_lvl3_at_maxtl;
 
assign  trp_lvl3_incr_w2 = thrd3_traps_w2 & ~trp_lvl3_at_maxtl;
 
 
 
 
 
assign trp_lvl3_new[2:0] =
 
assign trp_lvl3_new[2:0] =
 
           (tl_rw_w2 & wsr_inst_w2 & thread3_wsel_w2) ?
 
           (tl_rw_w2 & wsr_inst_w2 & thread3_wsel_w2) ?
 
                        wsr_trp_lvl3_data_w2[2:0] :
 
                        wsr_trp_lvl3_data_w2[2:0] :
 
                        (local_rst | por_rstint3_w2) ? 3'b110 :
 
                        (local_rst | por_rstint3_w2) ? `MAXTL :
 
                        (dnrtry_inst_w2[3]) ?
 
                        (dnrtry_inst_w2[3]) ?
 
                                trp_lvl3[2:0] - 3'b001:// done/retry decrements
 
                                trp_lvl3[2:0] - 3'b001:// done/retry decrements
 
                                trp_lvl3[2:0] + {2'b00,trp_lvl3_incr_w2};// trap increments
 
                                trp_lvl3[2:0] + {2'b00,trp_lvl3_incr_w2};// trap increments
 
 
 
 
 
assign tl3_en =
 
assign tl3_en =
 
           (tl_rw_w2 & wsr_inst_w2 & thread3_wsel_w2) |
 
           (tl_rw_w2 & wsr_inst_w2 & thread3_wsel_w2) |
 
                        trp_lvl3_incr_w2| local_rst | por_rstint3_w2 |
 
                        trp_lvl3_incr_w2| local_rst | por_rstint3_w2 |
 
            dnrtry_inst_w2[3];
 
            dnrtry_inst_w2[3];
 
 
 
 
 
// Reset required as processor will start out at tl1 after reset.
 
// Reset required as processor will start out at tl1 after reset.
 
dffe #(3) dffe_tl3 (
 
dffe_s #(3) dffe_tl3 (
 
    .din (trp_lvl3_new[2:0]),
 
    .din (trp_lvl3_new[2:0]),
 
    .q   (trp_lvl3[2:0]),
 
    .q   (trp_lvl3[2:0]),
 
    .en  (tl3_en),
 
    .en  (tl3_en),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
assign  tlu_lsu_tl_zero[3] = ~trp_lvl3[2] & ~trp_lvl3[1] & ~trp_lvl3[0];
 
assign  tlu_lsu_tl_zero[3] = ~trp_lvl3[2] & ~trp_lvl3[1] & ~trp_lvl3[0];
 
assign  tl3_gt_0 = trp_lvl3[2] | trp_lvl3[1] | trp_lvl3[0];
 
assign  tl3_gt_0 = trp_lvl3[2] | trp_lvl3[1] | trp_lvl3[0];
 
//
 
//
Line 6277... Line 5884... 
assign tlz_thread_set[0] = ~(tlu_lsu_tl_zero[0] | (|(trp_lvl0_new[2:0]))) & tl0_en;
 
assign tlz_thread_set[0] = ~(tlu_lsu_tl_zero[0] | (|(trp_lvl0_new[2:0]))) & tl0_en;
 
assign tlz_thread_set[1] = ~(tlu_lsu_tl_zero[1] | (|(trp_lvl1_new[2:0]))) & tl1_en;
 
assign tlz_thread_set[1] = ~(tlu_lsu_tl_zero[1] | (|(trp_lvl1_new[2:0]))) & tl1_en;
 
assign tlz_thread_set[2] = ~(tlu_lsu_tl_zero[2] | (|(trp_lvl2_new[2:0]))) & tl2_en;
 
assign tlz_thread_set[2] = ~(tlu_lsu_tl_zero[2] | (|(trp_lvl2_new[2:0]))) & tl2_en;
 
assign tlz_thread_set[3] = ~(tlu_lsu_tl_zero[3] | (|(trp_lvl3_new[2:0]))) & tl3_en;
 
assign tlz_thread_set[3] = ~(tlu_lsu_tl_zero[3] | (|(trp_lvl3_new[2:0]))) & tl3_en;
 
 
 
 
 
dff #(4) dff_tlz_thread_data (
 
dff_s #(`TLU_THRD_NUM) dff_tlz_thread_data (
 
    .din (tlz_thread_set[4-1:0]),
 
    .din (tlz_thread_set[`TLU_THRD_NUM-1:0]),
 
        .q   (tlz_thread_data[4-1:0]),
 
        .q   (tlz_thread_data[`TLU_THRD_NUM-1:0]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
//
 
//
 
// storing the state of the tlz trap to take the trap on the next valid
 
// storing the state of the tlz trap to take the trap on the next valid
 
// instruction 
// instruction 
// modified for bug 3646
 
// modified for bug 3646
 
dffre dffr_tlz_thread_0  (
 
dffre_s dffr_tlz_thread_0  (
 
    .din (tlz_thread_data[0]),
 
    .din (tlz_thread_data[0]),
 
    .q   (tlz_thread[0]),
 
    .q   (tlz_thread[0]),
 
    .rst (local_rst | tlz_trap_g[0] | thread_inst_vld_g[0]),
 
    .rst (local_rst | tlz_trap_g[0] | thread_inst_vld_g[0]),
 
    .en  (tlz_thread_data[0] & tlu_hpstate_tlz[0]),
 
    .en  (tlz_thread_data[0] & tlu_hpstate_tlz[0]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dffre dffr_tlz_thread_1  (
 
dffre_s dffr_tlz_thread_1  (
 
    .din (tlz_thread_data[1]),
 
    .din (tlz_thread_data[1]),
 
    .q   (tlz_thread[1]),
 
    .q   (tlz_thread[1]),
 
    .rst (local_rst | tlz_trap_g[1] | thread_inst_vld_g[1]),
 
    .rst (local_rst | tlz_trap_g[1] | thread_inst_vld_g[1]),
 
    .en  (tlz_thread_data[1] & tlu_hpstate_tlz[1]),
 
    .en  (tlz_thread_data[1] & tlu_hpstate_tlz[1]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dffre dffr_tlz_thread_2  (
 
dffre_s dffr_tlz_thread_2  (
 
    .din (tlz_thread_data[2]),
 
    .din (tlz_thread_data[2]),
 
    .q   (tlz_thread[2]),
 
    .q   (tlz_thread[2]),
 
    .rst (local_rst | tlz_trap_g[2] | thread_inst_vld_g[2]),
 
    .rst (local_rst | tlz_trap_g[2] | thread_inst_vld_g[2]),
 
    .en  (tlz_thread_data[2] & tlu_hpstate_tlz[2]),
 
    .en  (tlz_thread_data[2] & tlu_hpstate_tlz[2]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dffre dffr_tlz_thread_3  (
 
dffre_s dffr_tlz_thread_3  (
 
    .din (tlz_thread_data[3]),
 
    .din (tlz_thread_data[3]),
 
    .q   (tlz_thread[3]),
 
    .q   (tlz_thread[3]),
 
    .rst (local_rst | tlz_trap_g[3] | thread_inst_vld_g[3]),
 
    .rst (local_rst | tlz_trap_g[3] | thread_inst_vld_g[3]),
 
    .en  (tlz_thread_data[3] & tlu_hpstate_tlz[3]),
 
    .en  (tlz_thread_data[3] & tlu_hpstate_tlz[3]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
//
 
//
 
// initiate the trap for the appropriate thread
 
// initiate the trap for the appropriate thread
 
// modified for bug 4434 & 4758
 
// modified for bug 4434 & 4758
Line 6374... Line 5981... 
            tlu_lsu_tl_zero[3] & thread3_rsel_m & tlz_thread[3] & ~tlu_hpstate_priv[3] &
 
            tlu_lsu_tl_zero[3] & thread3_rsel_m & tlz_thread[3] & ~tlu_hpstate_priv[3] &
 
            tlu_hpstate_tlz[3];
 
            tlu_hpstate_tlz[3];
 
//
 
//
 
// modified for bug 4862
 
// modified for bug 4862
 
// indicate that a TLZ trap needs to be taken
 
// indicate that a TLZ trap needs to be taken
 
dffr #(4) dffr_tlz_trap_g  (
 
dffr_s #(`TLU_THRD_NUM) dffr_tlz_trap_g  (
 
    .din (tlz_trap_m[4-1:0]),
 
    .din (tlz_trap_m[`TLU_THRD_NUM-1:0]),
 
    .q   (tlz_trap_nq_g[4-1:0]),
 
    .q   (tlz_trap_nq_g[`TLU_THRD_NUM-1:0]),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
assign tlz_trap_g[0] = tlz_trap_nq_g[0] & ~inst_ifu_flush2_w;
 
assign tlz_trap_g[0] = tlz_trap_nq_g[0] & ~inst_ifu_flush2_w;
 
assign tlz_trap_g[1] = tlz_trap_nq_g[1] & ~inst_ifu_flush2_w;
 
assign tlz_trap_g[1] = tlz_trap_nq_g[1] & ~inst_ifu_flush2_w;
Line 6415... Line 6022... 
           inst_ifu_flush_w | local_early_flush_pipe_w |
 
           inst_ifu_flush_w | local_early_flush_pipe_w |
 
           (lsu_tlu_early_flush_w & inst_vld_nf_g);
 
           (lsu_tlu_early_flush_w & inst_vld_nf_g);
 
 
 
 
 
 
 
 
 
// staging the all flush signal 
// staging the all flush signal 
dffr dffr_tlu_flush_all_w2 (
 
dffr_s dffr_tlu_flush_all_w2 (
 
    .din (tlu_flush_all_w),
 
    .din (tlu_flush_all_w),
 
    .q   (tlu_flush_all_w2),
 
    .q   (tlu_flush_all_w2),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
//
 
//
 
// added for timing
 
// added for timing
 
assign lsu_ttype_vld_w =
 
assign lsu_ttype_vld_w =
 
           lsu_tlu_ttype_vld_m2 & inst_vld_g;
 
           lsu_tlu_ttype_vld_m2 & inst_vld_g;
 
// 
// 
// staging the flush-pipe signal 
// staging the flush-pipe signal 
dffr dffr_lsu_ttype_vld_w2 (
 
dffr_s dffr_lsu_ttype_vld_w2 (
 
    .din (lsu_ttype_vld_w),
 
    .din (lsu_ttype_vld_w),
 
    .q   (lsu_ttype_vld_w2),
 
    .q   (lsu_ttype_vld_w2),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
assign  tlu_flush_pipe_w = tlu_ifu_flush_pipe_w;
 
assign  tlu_flush_pipe_w = tlu_ifu_flush_pipe_w;
 
//
 
//
Line 6456... Line 6063... 
assign tlu_exu_early_flush_pipe_w = local_early_flush_pipe3_w;
 
assign tlu_exu_early_flush_pipe_w = local_early_flush_pipe3_w;
 
assign tlu_early_flush_pipe_w     = local_early_flush_pipe4_w;
 
assign tlu_early_flush_pipe_w     = local_early_flush_pipe4_w;
 
 
 
 
 
// added local early flush pipe timing fix
 
// added local early flush pipe timing fix
 
 
 
 
 
dffr dffr_local_early_flush_pipe_w (
 
dffr_s dffr_local_early_flush_pipe_w (
 
    .din (sync_trap_taken_m),
 
    .din (sync_trap_taken_m),
 
    .q   (local_early_flush_pipe_w),
 
    .q   (local_early_flush_pipe_w),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so ()
 
    .so ()
 
);
 
);
 
 
 
 
 
dffr dffr_local_early_flush_pipe2_w (
 
dffr_s dffr_local_early_flush_pipe2_w (
 
    .din (sync_trap_taken_m),
 
    .din (sync_trap_taken_m),
 
    .q   (local_early_flush_pipe2_w),
 
    .q   (local_early_flush_pipe2_w),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so ()
 
    .so ()
 
);
 
);
 
 
 
 
 
dffr dffr_local_early_flush_pipe3_w (
 
dffr_s dffr_local_early_flush_pipe3_w (
 
    .din (sync_trap_taken_m),
 
    .din (sync_trap_taken_m),
 
    .q   (local_early_flush_pipe3_w),
 
    .q   (local_early_flush_pipe3_w),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so ()
 
    .so ()
 
);
 
);
 
 
 
 
 
dffr dffr_local_early_flush_pipe4_w (
 
dffr_s dffr_local_early_flush_pipe4_w (
 
    .din (sync_trap_taken_m),
 
    .din (sync_trap_taken_m),
 
    .q   (local_early_flush_pipe4_w),
 
    .q   (local_early_flush_pipe4_w),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so ()
 
    .so ()
 
);
 
);
 
 
 
 
 
//=========================================================================================
 
//=========================================================================================
 
//      SFSR/SFAR HANDLING
 
//      SFSR/SFAR HANDLING
Line 6528... Line 6135... 
// va-out-of-range for ldst,branch,call,sequential 
// va-out-of-range for ldst,branch,call,sequential 
// modified for bug 4763
 
// modified for bug 4763
 
// assign       immu_va_oor_brnchetc_m
 
// assign       immu_va_oor_brnchetc_m
 
//      = exu_tlu_va_oor_m & ~pstate_am & ~memref_m;
 
//      = exu_tlu_va_oor_m & ~pstate_am & ~memref_m;
 
 
 
 
 
dffr dffr_immu_va_oor_brnchetc_m (
 
dffr_s dffr_immu_va_oor_brnchetc_m (
 
    .din (ifu_tlu_pc_oor_e),
 
    .din (ifu_tlu_pc_oor_e),
 
    .q   (immu_va_oor_brnchetc_m),
 
    .q   (immu_va_oor_brnchetc_m),
 
    .rst (local_rst),
 
    .rst (local_rst),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_memref_e (
 
dff_s dff_memref_e (
 
    .din (ifu_lsu_memref_d),
 
    .din (ifu_lsu_memref_d),
 
    .q   (memref_e),
 
    .q   (memref_e),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so ()
 
    .so ()
 
);
 
);
 
 
 
 
 
 
 
 
 
dff dff_memref_m (
 
dff_s dff_memref_m (
 
    .din (memref_e),// ifu_tlu_flsh_inst_e
 
    .din (memref_e),// ifu_tlu_flsh_inst_e
 
    .q   (memref_m),// flsh_inst_m
 
    .q   (memref_m),// flsh_inst_m
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
assign isfsr_flt_vld_m =
 
assign isfsr_flt_vld_m =
 
        (thread0_rsel_m & tlu_isfsr_flt_vld[0]) |
 
        (thread0_rsel_m & tlu_isfsr_flt_vld[0]) |
Line 6571... Line 6178... 
        (thread0_rsel_m & tlu_pstate_am[0]) |
 
        (thread0_rsel_m & tlu_pstate_am[0]) |
 
        (thread1_rsel_m & tlu_pstate_am[1]) |
 
        (thread1_rsel_m & tlu_pstate_am[1]) |
 
        (thread2_rsel_m & tlu_pstate_am[2]) |
 
        (thread2_rsel_m & tlu_pstate_am[2]) |
 
        (thread3_rsel_m & tlu_pstate_am[3]);
 
        (thread3_rsel_m & tlu_pstate_am[3]);
 
 
 
 
 
dff #(1) dff_am_stgg (
 
dff_s #(1) dff_am_stgg (
 
    .din (pstate_am),
 
    .din (pstate_am),
 
    .q   (tlu_addr_msk_g),
 
    .q   (tlu_addr_msk_g),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
//
 
//
 
// logic moved to lsu_expctl due to timing
 
// logic moved to lsu_expctl due to timing
 
/*
 
/*
Line 6606... Line 6213... 
           ~isfsr_ftype_sel[0] & exu_tlu_va_oor_jl_ret_m &
 
           ~isfsr_ftype_sel[0] & exu_tlu_va_oor_jl_ret_m &
 
           ~(exu_tlu_ttype_vld_m | ifu_tlu_ttype_vld_m) & ~pstate_am;
 
           ~(exu_tlu_ttype_vld_m | ifu_tlu_ttype_vld_m) & ~pstate_am;
 
 
 
 
 
assign  isfsr_trp_wr_m = |isfsr_ftype_sel[2:0];
 
assign  isfsr_trp_wr_m = |isfsr_ftype_sel[2:0];
 
 
 
 
 
dff #(1) dff_isfsrw_stgg (
 
dff_s #(1) dff_isfsrw_stgg (
 
        .din (isfsr_trp_wr_m),
 
        .din (isfsr_trp_wr_m),
 
        .q   (isfsr_trp_wr_g),
 
        .q   (isfsr_trp_wr_g),
 
        .clk (clk),
 
        .clk (clk),
 
        .se  (se),
 
        .se  (se),
 
        .si  (),
 
        `SIMPLY_RISC_SCANIN,
 
        .so  ()
 
        .so  ()
 
);
 
);
 
 
 
 
 
dff #(1) dff_itag_acc_sel_g (
 
dff_s #(1) dff_itag_acc_sel_g (
 
        .din (isfsr_trp_wr_m | ifu_tlu_immu_miss_m),
 
        .din (isfsr_trp_wr_m | ifu_tlu_immu_miss_m),
 
        .q   (itag_acc_sel_g),
 
        .q   (itag_acc_sel_g),
 
        .clk (clk),
 
        .clk (clk),
 
        .se  (se),
 
        .se  (se),
 
        .si  (),
 
        `SIMPLY_RISC_SCANIN,
 
        .so ()
 
        .so ()
 
);
 
);
 
 
 
 
 
assign tlu_itag_acc_sel_g = itag_acc_sel_g;
 
assign tlu_itag_acc_sel_g = itag_acc_sel_g;
 
 
 
 
Line 6643... Line 6250... 
assign  isfsr_ftype_m[5] = isfsr_ftype_sel[1];
 
assign  isfsr_ftype_m[5] = isfsr_ftype_sel[1];
 
assign  isfsr_ftype_m[4:1] = 4'b0000;
 
assign  isfsr_ftype_m[4:1] = 4'b0000;
 
assign  isfsr_ftype_m[0] = isfsr_ftype_sel[0];
 
assign  isfsr_ftype_m[0] = isfsr_ftype_sel[0];
 
//
 
//
 
// modified due to timing
 
// modified due to timing
 
dff #(8) dff_isfsr_stgg (
 
dff_s #(8) dff_isfsr_stgg (
 
    .din ({isfsr_ftype_m[6:0],isfsr_flt_vld_m}), // pstate_priv, 
    .din ({isfsr_ftype_m[6:0],isfsr_flt_vld_m}), // pstate_priv, 
        .q   ({isfsr_ftype_g[6:0],isfsr_flt_vld_g}), // pstate_priv_g,
 
        .q   ({isfsr_ftype_g[6:0],isfsr_flt_vld_g}), // pstate_priv_g,
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
// Can we remove the excessive bits in isfsr ?
 
// Can we remove the excessive bits in isfsr ?
 
// Do jmpl/rtrn define the asi in i or dsfsr ? seems only jmpl_rtrn mem_addr_not_aligned
 
// Do jmpl/rtrn define the asi in i or dsfsr ? seems only jmpl_rtrn mem_addr_not_aligned
Line 6660... Line 6267... 
// Need to add ctxt !!!
 
// Need to add ctxt !!!
 
 
 
 
 
assign isfsr_ctxt_g[1:0] =
 
assign isfsr_ctxt_g[1:0] =
 
               trp_lvl_zero ? 2'b00 : 2'b10;
 
               trp_lvl_zero ? 2'b00 : 2'b10;
 
 
 
 
 
dff #(1) dff_thread_tl_zero_m (
 
dff_s #(1) dff_thread_tl_zero_m (
 
    .din (thread_tl_zero),
 
    .din (thread_tl_zero),
 
    .q   (thread_tl_zero_m),
 
    .q   (thread_tl_zero_m),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so ()
 
    .so ()
 
);
 
);
 
 
 
 
 
dff #(1) dff_thread_tl_zero_g (
 
dff_s #(1) dff_thread_tl_zero_g (
 
    .din (thread_tl_zero_m),
 
    .din (thread_tl_zero_m),
 
    .q   (thread_tl_zero_g),
 
    .q   (thread_tl_zero_g),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
assign isfsr_asi_g[7:0] =
 
assign isfsr_asi_g[7:0] =
 
           thread_tl_zero_g ? 8'h80 : 8'h04;
 
           thread_tl_zero_g ? 8'h80 : 8'h04;
Line 6687... Line 6294... 
assign  tlu_isfsr_din_g[23:0] =
 
assign  tlu_isfsr_din_g[23:0] =
 
        {isfsr_asi_g[7:0],2'b0,isfsr_ftype_g[6:0],1'b0,isfsr_ctxt_g[1:0],2'b0,isfsr_flt_vld_g,1'b1};
 
        {isfsr_asi_g[7:0],2'b0,isfsr_ftype_g[6:0],1'b0,isfsr_ctxt_g[1:0],2'b0,isfsr_flt_vld_g,1'b1};
 
 
 
 
 
assign  dmmu_va_oor_m = exu_tlu_va_oor_m & ~pstate_am & memref_m & ~lsu_tlu_squash_va_oor_m;
 
assign  dmmu_va_oor_m = exu_tlu_va_oor_m & ~pstate_am & memref_m & ~lsu_tlu_squash_va_oor_m;
 
 
 
 
 
dff #(3) dff_dsfsr_stgg (
 
dff_s #(3) dff_dsfsr_stgg (
 
    .din ({dmmu_va_oor_m,// memref_m,
 
    .din ({dmmu_va_oor_m,// memref_m,
 
           exu_tlu_misalign_addr_jmpl_rtn_m,
 
           exu_tlu_misalign_addr_jmpl_rtn_m,
 
               lsu_tlu_misalign_addr_ldst_atm_m}),
 
               lsu_tlu_misalign_addr_ldst_atm_m}),
 
    .q   ({dmmu_va_oor_g,
 
    .q   ({dmmu_va_oor_g,
 
               misalign_addr_jmpl_rtn_g,
 
               misalign_addr_jmpl_rtn_g,
 
           misalign_addr_ldst_atm_g}),
 
           misalign_addr_ldst_atm_g}),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so ()
 
    .so ()
 
);
 
);
 
 
 
 
 
//=========================================================================================
 
//=========================================================================================
 
//      GLOBAL REGISTER SWITCHING
 
//      GLOBAL REGISTER SWITCHING
Line 6710... Line 6317... 
assign agp_tid_sel =
 
assign agp_tid_sel =
 
           (dnrtry_inst_g) | (tlu_gl_rw_g & wsr_inst_g);
 
           (dnrtry_inst_g) | (tlu_gl_rw_g & wsr_inst_g);
 
assign  agp_tid_g[1:0] =
 
assign  agp_tid_g[1:0] =
 
            agp_tid_sel ? thrid_g[1:0] : trap_tid_g[1:0];
 
            agp_tid_sel ? thrid_g[1:0] : trap_tid_g[1:0];
 
 
 
 
 
dff #(2) dff_tlu_agp_tid_w2 (
 
dff_s #(2) dff_tlu_agp_tid_w2 (
 
    .din (agp_tid_g[1:0]),
 
    .din (agp_tid_g[1:0]),
 
    .q   (agp_tid_w2[1:0]),
 
    .q   (agp_tid_w2[1:0]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
//
 
//
 
// added for timing
 
// added for timing
 
dff #(2) dff_agp_tid_w3 (
 
dff_s #(2) dff_agp_tid_w3 (
 
    .din (agp_tid_w2[1:0]),
 
    .din (agp_tid_w2[1:0]),
 
    .q   (agp_tid_w3[1:0]),
 
    .q   (agp_tid_w3[1:0]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
assign tlu_agp_tid_w2[1:0]  = agp_tid_w2[1:0];
 
assign tlu_agp_tid_w2[1:0]  = agp_tid_w2[1:0];
 
assign tlu_exu_agp_tid[1:0] = agp_tid_w3[1:0];
 
assign tlu_exu_agp_tid[1:0] = agp_tid_w3[1:0];
Line 6737... Line 6344... 
//=========================================================================================
 
//=========================================================================================
 
//      CWP/CCR restoration
 
//      CWP/CCR restoration
 
//=========================================================================================
 
//=========================================================================================
 
// code moved to tlu_misctl
 
// code moved to tlu_misctl
 
/*
 
/*
 
dff #(8) dff_ccr_stgm (
 
dff_s #(8) dff_ccr_stgm (
 
    .din (tsa_rdata_ccr[7:0]),
 
    .din (tsa_rdata_ccr[7:0]),
 
    .q   (tlu_exu_ccr_m[7:0]),
 
    .q   (tlu_exu_ccr_m[7:0]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff #(3) dff_cwp_stgm (
 
dff_s #(3) dff_cwp_stgm (
 
    .din (tsa_rdata_cwp[2:0]),
 
    .din (tsa_rdata_cwp[2:0]),
 
    .q   (tlu_exu_cwp_m[2:0]),
 
    .q   (tlu_exu_cwp_m[2:0]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff #(8) dff_lsu_asi_m (
 
dff_s #(8) dff_lsu_asi_m (
 
    .din (tsa_rdata_asi[7:0]),
 
    .din (tsa_rdata_asi[7:0]),
 
    .q   (tlu_lsu_asi_m[7:0]),
 
    .q   (tlu_lsu_asi_m[7:0]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
    );
 
    );
 
*/
 
*/
 
//
 
//
 
 
 
 
Line 6805... Line 6412... 
                (cwp_cmplt1_pending & pending_thrd1_event_taken & cwp_retry1) |
 
                (cwp_cmplt1_pending & pending_thrd1_event_taken & cwp_retry1) |
 
                (cwp_cmplt2_pending & pending_thrd2_event_taken & cwp_retry2) |
 
                (cwp_cmplt2_pending & pending_thrd2_event_taken & cwp_retry2) |
 
                (cwp_cmplt3_pending & pending_thrd3_event_taken & cwp_retry3);
 
                (cwp_cmplt3_pending & pending_thrd3_event_taken & cwp_retry3);
 
// 
// 
 
 
 
 
dff #(2) dff_ccmplt_stgw2 (
 
dff_s #(2) dff_ccmplt_stgw2 (
 
    .din ({cwp_cmplt_g,cwp_cmplt_rtry_g}),
 
    .din ({cwp_cmplt_g,cwp_cmplt_rtry_g}),
 
    .q   ({cwp_cmplt_w2,cwp_cmplt_rtry_w2}),
 
    .q   ({cwp_cmplt_w2,cwp_cmplt_rtry_w2}),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
//=========================================================================================
 
//=========================================================================================
 
//      Generate SSCAN data 
//      Generate SSCAN data 
//=========================================================================================
 
//=========================================================================================
 
// 
// 
assign sscan_tid_sel[4-1:0] = ctu_sscan_tid[4-1:0];
 
assign sscan_tid_sel[`TLU_THRD_NUM-1:0] = ctu_sscan_tid[`TLU_THRD_NUM-1:0];
 
/*
 
/*
 
// logic moved to tlu_misctl
 
// logic moved to tlu_misctl
 
// generating write indicators of ttype to the tsa
 
// generating write indicators of ttype to the tsa
 
assign sscan_tt_wr_sel[0] =
 
assign sscan_tt_wr_sel[0] =
 
           tsa_ttype_en & tsa_wr_vld[1] & thread0_wtrp_w2;
 
           tsa_ttype_en & tsa_wr_vld[1] & thread0_wtrp_w2;
Line 6863... Line 6470... 
            final_ttype_w2[`TSA_TTYPE_WIDTH-1:0] : tsa_rdata_ttype_m[`TSA_TTYPE_WIDTH-1:0];
 
            final_ttype_w2[`TSA_TTYPE_WIDTH-1:0] : tsa_rdata_ttype_m[`TSA_TTYPE_WIDTH-1:0];
 
assign sscan_tt3_din[`TSA_TTYPE_WIDTH-1:0] =
 
assign sscan_tt3_din[`TSA_TTYPE_WIDTH-1:0] =
 
           (sscan_tt_wr_sel[3]) ?
 
           (sscan_tt_wr_sel[3]) ?
 
            final_ttype_w2[`TSA_TTYPE_WIDTH-1:0] : tsa_rdata_ttype_m[`TSA_TTYPE_WIDTH-1:0];
 
            final_ttype_w2[`TSA_TTYPE_WIDTH-1:0] : tsa_rdata_ttype_m[`TSA_TTYPE_WIDTH-1:0];
 
//
 
//
 
dffe #(`TSA_TTYPE_WIDTH) dffe_sscan_tt0_data (
 
dffe_s #(`TSA_TTYPE_WIDTH) dffe_sscan_tt0_data (
 
    .din (sscan_tt0_din[`TSA_TTYPE_WIDTH-1:0]),
 
    .din (sscan_tt0_din[`TSA_TTYPE_WIDTH-1:0]),
 
    .q   (sscan_tt0_data[`TSA_TTYPE_WIDTH-1:0]),
 
    .q   (sscan_tt0_data[`TSA_TTYPE_WIDTH-1:0]),
 
    .en  (sscan_ttype_en[0]),
 
    .en  (sscan_ttype_en[0]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dffe #(`TSA_TTYPE_WIDTH) dffe_sscan_tt1_data (
 
dffe_s #(`TSA_TTYPE_WIDTH) dffe_sscan_tt1_data (
 
    .din (sscan_tt1_din[`TSA_TTYPE_WIDTH-1:0]),
 
    .din (sscan_tt1_din[`TSA_TTYPE_WIDTH-1:0]),
 
    .q   (sscan_tt1_data[`TSA_TTYPE_WIDTH-1:0]),
 
    .q   (sscan_tt1_data[`TSA_TTYPE_WIDTH-1:0]),
 
    .en  (sscan_ttype_en[1]),
 
    .en  (sscan_ttype_en[1]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dffe #(`TSA_TTYPE_WIDTH) dffe_sscan_tt2_data (
 
dffe_s #(`TSA_TTYPE_WIDTH) dffe_sscan_tt2_data (
 
    .din (sscan_tt2_din[`TSA_TTYPE_WIDTH-1:0]),
 
    .din (sscan_tt2_din[`TSA_TTYPE_WIDTH-1:0]),
 
    .q   (sscan_tt2_data[`TSA_TTYPE_WIDTH-1:0]),
 
    .q   (sscan_tt2_data[`TSA_TTYPE_WIDTH-1:0]),
 
    .en  (sscan_ttype_en[2]),
 
    .en  (sscan_ttype_en[2]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dffe #(`TSA_TTYPE_WIDTH) dffe_sscan_tt3_data (
 
dffe_s #(`TSA_TTYPE_WIDTH) dffe_sscan_tt3_data (
 
    .din (sscan_tt3_din[`TSA_TTYPE_WIDTH-1:0]),
 
    .din (sscan_tt3_din[`TSA_TTYPE_WIDTH-1:0]),
 
    .q   (sscan_tt3_data[`TSA_TTYPE_WIDTH-1:0]),
 
    .q   (sscan_tt3_data[`TSA_TTYPE_WIDTH-1:0]),
 
    .en  (sscan_ttype_en[3]),
 
    .en  (sscan_ttype_en[3]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff #(`TSA_TTYPE_WIDTH) dff_tsa_rdata_ttype_m (
 
dff_s #(`TSA_TTYPE_WIDTH) dff_tsa_rdata_ttype_m (
 
    .din (tsa_rdata_ttype[`TSA_TTYPE_WIDTH-1:0]),
 
    .din (tsa_rdata_ttype[`TSA_TTYPE_WIDTH-1:0]),
 
        .q   (tsa_rdata_ttype_m[`TSA_TTYPE_WIDTH-1:0]),
 
        .q   (tsa_rdata_ttype_m[`TSA_TTYPE_WIDTH-1:0]),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_tsa_rd_vld_e (
 
dff_s dff_tsa_rd_vld_e (
 
    .din (tsa_rd_vld),
 
    .din (tsa_rd_vld),
 
        .q   (tsa_rd_vld_e),
 
        .q   (tsa_rd_vld_e),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
 
 
 
 
dff dff_tsa_rd_vld_m (
 
dff_s dff_tsa_rd_vld_m (
 
    .din (tsa_rd_vld_e),
 
    .din (tsa_rd_vld_e),
 
        .q   (tsa_rd_vld_m),
 
        .q   (tsa_rd_vld_m),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),
 
    .se  (se),
 
    .si  (),
 
    `SIMPLY_RISC_SCANIN,
 
    .so  ()
 
    .so  ()
 
);
 
);
 
//
 
//
 
// modified - due to sscan_tt[0-3]_data moved to tlu_misctl
 
// modified - due to sscan_tt[0-3]_data moved to tlu_misctl
 
mux4ds #(`TCL_SSCAN_WIDTH) mx_sscan_test_data (
 
mux4ds #(`TCL_SSCAN_WIDTH) mx_sscan_test_data (
Line 6944... Line 6551... 
       .sel3 (sscan_tid_sel[3]),
 
       .sel3 (sscan_tid_sel[3]),
 
       .dout (tcl_sscan_test_data[`TCL_SSCAN_WIDTH-1:0])
 
       .dout (tcl_sscan_test_data[`TCL_SSCAN_WIDTH-1:0])
 
);
 
);
 
*/
 
*/
 
 
 
 
 
mux4ds #(3) mx_sscan_test_data (
 
mux4ds #(`TCL_SSCAN_WIDTH) mx_sscan_test_data (
 
       .in0  (trp_lvl0[2:0]),
 
       .in0  (trp_lvl0[2:0]),
 
       .in1  (trp_lvl1[2:0]),
 
       .in1  (trp_lvl1[2:0]),
 
       .in2  (trp_lvl2[2:0]),
 
       .in2  (trp_lvl2[2:0]),
 
       .in3  (trp_lvl3[2:0]),
 
       .in3  (trp_lvl3[2:0]),
 
       .sel0 (sscan_tid_sel[0]),
 
       .sel0 (sscan_tid_sel[0]),
 
       .sel1 (sscan_tid_sel[1]),
 
       .sel1 (sscan_tid_sel[1]),
 
       .sel2 (sscan_tid_sel[2]),
 
       .sel2 (sscan_tid_sel[2]),
 
       .sel3 (sscan_tid_sel[3]),
 
       .sel3 (sscan_tid_sel[3]),
 
       .dout (tcl_sscan_test_data[3-1:0])
 
       .dout (tcl_sscan_test_data[`TCL_SSCAN_WIDTH-1:0])
 
);
 
);
 
 
 
 
 
assign tlu_sscan_tcl_data[3-1:0] =
 
assign tlu_sscan_tcl_data[`TCL_SSCAN_WIDTH-1:0] =
 
           tcl_sscan_test_data[3-1:0];
 
           tcl_sscan_test_data[`TCL_SSCAN_WIDTH-1:0];
 
 
 
 
 
//=========================================================================================
 
//=========================================================================================
 
//      Instrumentation signals created for sas 
//      Instrumentation signals created for sas 
//=========================================================================================
 
//=========================================================================================
 
// 
// 
// synopsys translate_off
 
// synopsys translate_off
 
wire [9-1:0] sas_final_ttype_g;
 
wire [`TSA_TTYPE_WIDTH-1:0] sas_final_ttype_g;
 
wire [9-1:0] sas_adj_lsu_ttype_m2;
 
wire [`TSA_TTYPE_WIDTH-1:0] sas_adj_lsu_ttype_m2;
 
wire [6:0] sas_hwint_swint_ttype;
 
wire [6:0] sas_hwint_swint_ttype;
 
wire [9-3:0] sas_rst_ttype_g;
 
wire [`TSA_TTYPE_WIDTH-3:0] sas_rst_ttype_g;
 
 
 
 
 
mux4ds #(9) mx_sas_final_ttype_g (
 
mux4ds #(`TSA_TTYPE_WIDTH) mx_sas_final_ttype_g (
 
    .sel0 (final_ttype_sel_g[0]),
 
    .sel0 (final_ttype_sel_g[0]),
 
    .sel1 (final_ttype_sel_g[1]),
 
    .sel1 (final_ttype_sel_g[1]),
 
    .sel2 (final_ttype_sel_g[2]),
 
    .sel2 (final_ttype_sel_g[2]),
 
    .sel3 (final_ttype_sel_g[3]),
 
    .sel3 (final_ttype_sel_g[3]),
 
    .in0  ({2'b0,sas_rst_ttype_g[9-3:0]}),
 
    .in0  ({2'b0,sas_rst_ttype_g[`TSA_TTYPE_WIDTH-3:0]}),
 
    .in1  (early_sync_ttype_g[9-1:0]),
 
    .in1  (early_sync_ttype_g[`TSA_TTYPE_WIDTH-1:0]),
 
    .in2  (sas_adj_lsu_ttype_m2[9-1:0]),
 
    .in2  (sas_adj_lsu_ttype_m2[`TSA_TTYPE_WIDTH-1:0]),
 
    .in3  (pending_ttype[9-1:0]),
 
    .in3  (pending_ttype[`TSA_TTYPE_WIDTH-1:0]),
 
    .dout (sas_final_ttype_g[9-1:0])
 
    .dout (sas_final_ttype_g[`TSA_TTYPE_WIDTH-1:0])
 
);
 
);
 
 
 
 
 
mux3ds #(9) mx_sas_adj_lsu_ttype_m2 (
 
mux3ds #(`TSA_TTYPE_WIDTH) mx_sas_adj_lsu_ttype_m2 (
 
    .sel0 (lsu_defr_trap_g),
 
    .sel0 (lsu_defr_trap_g),
 
    .sel1 (va_oor_data_acc_excp_g & ~lsu_defr_trap_g),
 
    .sel1 (va_oor_data_acc_excp_g & ~lsu_defr_trap_g),
 
    .sel2 (~(va_oor_data_acc_excp_g | lsu_defr_trap_g)),
 
    .sel2 (~(va_oor_data_acc_excp_g | lsu_defr_trap_g)),
 
    .in0  (9'h032),
 
    .in0  (9'h032),
 
    .in1  (9'h030),
 
    .in1  (9'h030),
 
    .in2  (lsu_tlu_ttype_m2),
 
    .in2  (lsu_tlu_ttype_m2),
 
    .dout (sas_adj_lsu_ttype_m2[9-1:0])
 
    .dout (sas_adj_lsu_ttype_m2[`TSA_TTYPE_WIDTH-1:0])
 
);
 
);
 
 
 
 
 
assign sas_hwint_swint_ttype[6:0] =
 
assign sas_hwint_swint_ttype[6:0] =
 
       (hwint_g)? 7'h60:
 
       (hwint_g)? `HWINT_INT:
 
       (cpu_mondo_trap_g)? 7'h7c:
 
       (cpu_mondo_trap_g)? `CPU_MONDO_TRAP:
 
       (dev_mondo_trap_g)? 7'h7d:
 
       (dev_mondo_trap_g)? `DEV_MONDO_TRAP:
 
        {3'b100, tlu_sftint_id[3:0]};
 
        {3'b100, tlu_sftint_id[3:0]};
 
 
 
 
 
assign sas_rst_ttype_g[9-3:0] =
 
assign sas_rst_ttype_g[`TSA_TTYPE_WIDTH-3:0] =
 
       (rst_ttype_sel[0])? {4'b00,reset_id_g[2:0]}:
 
       (rst_ttype_sel[0])? {4'b00,reset_id_g[2:0]}:
 
       (rst_ttype_sel[1])? wrap_tlz_ttype[6:0]:
 
       (rst_ttype_sel[1])? wrap_tlz_ttype[6:0]:
 
        sas_hwint_swint_ttype[6:0];
 
        sas_hwint_swint_ttype[6:0];
 
 
 
 
 
// synopsys translate_on
 
// synopsys translate_on

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