| Line 33... |
Line 33... |
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
|
*
|
*
|
* ========== Copyright Header End ============================================
|
* ========== Copyright Header End ============================================
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*/
|
*/
|
|
|
!! Enable L2-ucache: currently unused in S1 Core
|
/* Base address for Power-On Reser is 0xFFF0000020, adding 8 NOPs to artificially create the 0x20 offset */
|
/*
|
nop
|
!! SunStudio version
|
nop
|
setx cregs_l2_ctl_reg_r64, %g1, %l1
|
nop
|
mov 0xa9, %g1
|
nop
|
sllx %g1, 32, %g1
|
nop
|
stx %l1, [%g1 + 0x00]
|
nop
|
stx %l1, [%g1 + 0x40]
|
nop
|
stx %l1, [%g1 + 0x80]
|
nop
|
stx %l1, [%g1 + 0xc0]
|
|
*/
|
|
|
|
/*
|
/* Initialize windowed local, output and input GPRs */
|
!! GCC version
|
wrpr %g0, %g0, %cwp !! CWP = 0
|
wr %g0, 5, %asr26
|
wrpr %g0, 0x6, %cansave !! CANSAVE = 6
|
clr %l1
|
wrpr %g0, %g0, %canrestore !! CANRESTORE = 0
|
mov 0xa9, %g1
|
wrpr %g0, %g0, %otherwin !! OTHERWIN = 0
|
sllx %g1, 32, %g1
|
wrpr %g0, 0x7, %cleanwin !! CLEANWIN = 7
|
stx %l1, [%g1 + 0x00]
|
wrpr %g0, 0x7, %wstate !! WSTATE = (b)000_111
|
stx %l1, [%g1 + 0x40]
|
add %g0, 0x1, %l1 !! l1 = 1
|
stx %l1, [%g1 + 0x80]
|
add %g0, 0x1, %o1 !! o1 = 1
|
stx %l1, [%g1 + 0xc0]
|
add %g0, 0x1, %i1 !! i1 = 1
|
*/
|
add %l1, 0x1, %l2 !! l1 = 2
|
|
add %o1, 0x1, %o2 !! o1 = 2
|
|
add %i1, 0x1, %i2 !! i1 = 2
|
|
add %l2, 0x1, %l3 !! l1 = 3
|
|
add %o2, 0x1, %o3 !! o1 = 3
|
|
add %i2, 0x1, %i3 !! i1 = 3
|
|
nop; nop; nop; nop
|
|
|
!! Set the LSU Diagnostic Register to enable all ways for L1-icache and L1-dcache
|
/* Set the LSU Diagnostic Register to enable all ways for L1-icache and L1-dcache and using the "random replacement" algorithm */
|
!! and using the "random replacement" algorithm
|
clr %l1 !! Clear l1
|
/*
|
|
!! SunStudio version
|
|
setx cregs_lsu_diag_reg_r64, %g1, %l1
|
|
mov 0x10, %g1
|
mov 0x10, %g1
|
stxa %l1, [%g1] ASI_LSU_DIAG_REG
|
stxa %l1, [%g1] (66) !! LSU_DIAG_REG = b00
|
*/
|
|
!! GCC version
|
|
mov 0x10, %g1
|
|
stxa %l1, [%g1] (66)
|
|
|
|
!! Set the LSU Control Register to enable L1-icache and L1-dcache
|
/* Set the LSU Control Register to enable L1-icache and L1-dcache */
|
/*
|
! mov 3, %l1
|
!! SunStudio version
|
! stxa %l1, [%g0] (69)
|
setx (CREGS_LSU_CTL_REG_IC | (CREGS_LSU_CTL_REG_DC << 1)), %g1, %l1
|
|
stxa %l1, [%g0] ASI_LSU_CTL_REG
|
|
*/
|
|
!! GCC version
|
|
mov 3, %l1
|
|
stxa %l1, [%g0] (69)
|
|
|
|
!! Set hpstate.red = 0 and hpstate.enb = 1
|
/* Set hpstate.red = 0 and hpstate.enb = 1 */
|
rdhpr %hpstate, %l1
|
rdhpr %hpstate, %l1
|
wrhpr %l1, 0x820, %hpstate
|
wrhpr %l1, 0x820, %hpstate
|
|
|
!! Initialize Interrupt Queue Registers: currently unused in S1 Core
|
/* Clear L1-icache and L1-dcache SFSR */
|
/*
|
|
wr %g0, 0x25, %asi
|
|
|
|
stxa %g0, [0x3c0] %asi
|
|
stxa %g0, [0x3c8] %asi
|
|
stxa %g0, [0x3d0] %asi
|
|
stxa %g0, [0x3d8] %asi
|
|
|
|
stxa %g0, [0x3e0] %asi
|
|
stxa %g0, [0x3e8] %asi
|
|
stxa %g0, [0x3f0] %asi
|
|
stxa %g0, [0x3f8] %asi
|
|
|
|
wrpr 0, %tl
|
|
wrpr 0, %g0, %gl
|
|
wr %g0, cregs_fprs_imm, %fprs
|
|
wr %g0, cregs_ccr_imm, %ccr
|
|
|
|
wr %g0, cregs_asi_imm, %asi
|
|
setx cregs_tick_r64, %g1, %g2
|
|
!! FIXME set other ticks also
|
|
wrpr %g2, %tick
|
|
setx cregs_stick_r64, %g1, %g2
|
|
|
|
wr %g2, %g0, %sys_tick
|
|
mov 0x1, %g2
|
|
sllx %g2, 63, %g2
|
|
wr %g2, %g0, %tick_cmpr
|
|
|
|
wr %g2, %g0, %sys_tick_cmpr
|
|
wrhpr %g2, %g0, %hsys_tick_cmpr
|
|
mov %g0, %y
|
|
wrpr cregs_pil_imm, %pil
|
|
|
|
wrpr cregs_cwp_imm, %cwp
|
|
wrpr cregs_cansave_imm, %cansave
|
|
wrpr cregs_canrestore_imm, %canrestore
|
|
wrpr cregs_otherwin_imm, %otherwin
|
|
|
|
wrpr cregs_cleanwin_imm, %cleanwin
|
|
wrpr cregs_wstate_imm, %wstate
|
|
*/
|
|
|
|
!! Clear L1-icache and L1-dcache SFSR
|
|
mov 0x18, %g1
|
mov 0x18, %g1
|
stxa %g0, [%g0 + %g1] 0x50 !! IMMU Synchronous Fault Status register=0
|
stxa %g0, [%g0 + %g1] 0x50 !! IMMU Synchronous Fault Status (SFS) register=0
|
stxa %g0, [%g0 + %g1] 0x58 !! DMMU Synchronous Fault Status register=0
|
stxa %g0, [%g0 + %g1] 0x58 !! DMMU Synchronous Fault Status (SFS) register=0
|
|
|
!! Enable error trap
|
/* SPARC Error Enable Reg. */
|
/*
|
|
!! SunStudio version
|
|
setx cregs_sparc_error_en_reg_r64, %g1, %l1
|
|
stxa %l1, [%g0] ASI_SPARC_ERROR_EN_REG
|
|
*/
|
|
!! GCC version
|
|
!! in file defines.h constant cregs_sparc_error_en_reg_r64:=3
|
!! in file defines.h constant cregs_sparc_error_en_reg_r64:=3
|
!! so the effect should be "trap on correctable error" and "trap on uncorrectable error"
|
!! so the effect should be "trap on correctable error" and "trap on uncorrectable error"
|
sethi %hh(0x3),%g1
|
or %g0, 0x3, %l1 !! l1 = 3
|
or %g1,%hm(0x3),%g1
|
stxa %l1, [%g0] (75) !! SPARC_Error_Enable_reg = 3
|
sllx %g1,32,%g1
|
|
sethi %hi(0x3),%l1
|
|
or %l1,%g1,%l1
|
|
or %l1,%lo(0x3),%l1
|
|
stxa %l1, [%g0] (75) !! copy the content of the l1 register into the "SPARC Error Enable reg"
|
|
|
|
!! Enable L2-ucache error trap: currently unused in S1 Core
|
|
/*
|
|
setx cregs_l2_error_en_reg_r64, %g1, %l1
|
|
|
|
mov 0xaa, %g1
|
|
sllx %g1, 32, %g1
|
|
stx %l1, [%g1 + 0x00]
|
|
stx %l1, [%g1 + 0x40]
|
|
|
|
stx %l1, [%g1 + 0x80]
|
|
stx %l1, [%g1 + 0xc0]
|
|
*/
|
|
|
|
!! Load Partition ID (permits to multiple OSs to share the same TLB)
|
|
/*
|
|
!! SunStudio version
|
|
rd %asr26, %l1
|
|
set 0x0300, %g1
|
|
and %l1, %g1, %l1
|
|
srlx %l1, 8, %l1 ! %l1 has thread ID
|
|
setx part_id_list, %g1, %g2
|
|
sllx %l1, 3, %l1 ! offset - partition list
|
|
ldx [%g2 + %l1], %g2 ! %g2 contains partition ID
|
|
mov 0x80, %g1
|
|
stxa %g2, [%g1] 0x58
|
|
*/
|
|
/*
|
|
!! GCC version
|
|
rd %asr26, %l1 !! ASR26 is the Strand Status and Control register
|
|
set 0x0300, %g1
|
|
and %l1, %g1, %l1
|
|
srlx %l1, 8, %l1 !! %l1 has thread ID
|
|
sethi %hi(0), %g1
|
|
sethi %hi(0x4c000), %g2
|
|
mov %g1, %g1
|
|
mov %g2, %g2
|
|
sllx %g1, 0x20, %g1
|
|
or %g2, %g1, %g2
|
|
sllx %l1, 3, %l1 !! offset - partition list
|
|
ldx [%g2 + %l1], %g2 !! %g2 contains partition ID
|
|
mov 0x80, %g1
|
|
stxa %g2, [%g1] 0x58 !! I/DMMU Partition ID=g2
|
|
*/
|
|
!! Set Hypervisor Trap Base Address
|
|
/*
|
|
!! SunStudio version
|
|
setx HV_TRAP_BASE_PA, %l0, %l7
|
|
wrhpr %l7, %g0, %htba
|
|
*/
|
|
!! GCC version
|
|
sethi %hh(0x80000),%g1
|
|
or %g1,%hm(0x80000),%g1
|
|
sllx %g1,32,%g1
|
|
sethi %hi(0x80000),%l1
|
|
or %l1,%g1,%l1
|
|
or %l1,%lo(0x80000),%l1
|
|
wrhpr %l7, %g0, %htba !! bits 63-14 select the trap vector
|
|
|
|
!! Load TSB config/base from memory and write to corresponding ASIs
|
|
!! Set tsb-reg (4 at present) for one partition
|
|
!! 2 i-config, 2-dconfig
|
|
/*
|
|
!! SunStudio version
|
|
setx tsb_config_base_list, %l0, %g1
|
|
*/
|
|
/*
|
|
!! GCC version
|
|
sethi %hi(0), %l0
|
|
sethi %hi(0x4c000), %g1
|
|
mov %l0, %l0
|
|
or %g1, 0x140, %g1
|
|
sllx %l0, 0x20, %l0
|
|
or %g1, %l0, %g1
|
|
|
|
sllx %g2, 7, %g2 !! %g2 contains offset to tsb_config_base_list
|
|
add %g1, %g2, %g1 !! %g1 contains pointer to tsb_config_base_list
|
|
|
|
!! IMMU_CXT_Z_CONFIG (0x37, VA=0x00)
|
|
ldx [%g1], %l1
|
|
stxa %l1, [%g0] 0x37
|
|
|
|
!! IMMU_CXT_NZ_CONFIG (0x3f, VA=0x00)
|
|
ldx [%g1+8], %l1
|
|
stxa %l1, [%g0] 0x3f
|
|
|
|
!! IMMU_CXT_Z_PS0_TSB (0x35, VA=0x0)
|
|
!! IMMU_CXT_Z_PS1_TSB (0x36, VA=0x0)
|
|
ldx [%g1+16], %l1
|
|
stxa %l1, [%g0] 0x35
|
|
ldx [%g1+32], %l1
|
|
stxa %l1, [%g0] 0x36
|
|
|
|
!! IMMU_CXT_NZ_PS0_TSB (0x3d, VA=0x00)
|
|
!! IMMU_CXT_NZ_PS1_TSB (0x3e, VA=0x00)
|
|
ldx [%g1+24], %l1
|
|
stxa %l1, [%g0] 0x3d
|
|
ldx [%g1+40], %l1
|
|
stxa %l1, [%g0] 0x3e
|
|
|
|
!! DMMU_CXT_Z_CONFIG (0x33, VA=0x00)
|
|
ldx [%g1+64], %l1
|
|
stxa %l1, [%g0] 0x33
|
|
|
|
!! DMMU_CXT_NZ_CONFIG (0x3b, VA=0x00)
|
|
ldx [%g1+72], %l1
|
|
stxa %l1, [%g0] 0x3b
|
|
|
|
!! DMMU_CXT_Z_PS0_TSB (0x31, VA=0x00)
|
|
!! DMMU_CXT_Z_PS1_TSB (0x32, VA=0x00)
|
|
ldx [%g1+80], %l1
|
|
stxa %l1, [%g0] 0x31
|
|
ldx [%g1+96], %l1
|
|
stxa %l1, [%g0] 0x32
|
|
|
|
!! DMMU_CXT_NZ_PS0_TSB (0x39, VA=0x00)
|
|
!! DMMU_CXT_NZ_PS0_TSB (0x3a, VA=0x00)
|
|
ldx [%g1+88], %l1
|
|
stxa %l1, [%g0] 0x39
|
|
ldx [%g1+104], %l1
|
|
stxa %l1, [%g0] 0x3a
|
|
|
|
!! Demap all itlb and dtlb
|
|
mov 0x80, %o2
|
|
stxa %g0, [%o2] 0x57 !! register ASI_IMMU_DEMAP=0 (IMMU TLB demap)
|
|
stxa %g0, [%o2] 0x5f !! register ASI_DMMU_DEMAP=0 (DMMU TLB demap)
|
|
*/
|
|
|
|
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
|
/* Set HTBA: HTBA[63:14] = 0x12 */
|
!! Instructions merged from file hboot_tlb_init.s !!
|
mov 1, %g1 !! g1 = 1
|
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
|
sllx %g1, 18, %l1 !! l1 = 40000
|
|
sllx %g1, 15, %g1 !! g1 = 8000
|
|
or %l1, %g1, %l1 !! l1 = 48000
|
|
wrhpr %l1, %g0, %htba !! bits 63-14 select Hpriv trap vector
|
|
|
|
/**************************************************/
|
|
/* Instructions merged from file hboot_tlb_init.s */
|
|
/**************************************************/
|
|
|
!! Init all itlb entries
|
/* Init all itlb entries */
|
mov 0x30, %g1
|
mov 0x30, %g1
|
mov %g0, %g2
|
mov %g0, %g2
|
itlb_init_loop:
|
itlb_init_loop:
|
!! clear data and tag entries of the TLB buffer
|
|
stxa %g0, [%g1] 0x50 !! IMMU TLB Tag Access register=0
|
stxa %g0, [%g1] 0x50 !! IMMU TLB Tag Access register=0
|
stxa %g0, [%g2] 0x55 !! IMMU TLB Data Access register=0, g2 values from 0x000 to 0x7f8
|
stxa %g0, [%g2] 0x55 !! IMMU TLB Data Access register=0, g2 values from 0x000 to 0x7f8
|
|
|
add %g2, 8, %g2 !! increment the g2 register 8 bytes every time (64 bits)
|
add %g2, 8, %g2 !! increment the g2 register 8 bytes every time (64 bits)
|
cmp %g2, 0x200 !! compare g2 with 512 (512*8=4096=0x1000), but max VA=0x7F8
|
cmp %g2, 0x200 !! compare g2 with 512 (512*8=4096=0x1000), but max VA=0x7F8
|
bne itlb_init_loop !! if (g2!=512) then run another loop
|
bne itlb_init_loop !! if (g2!=512) then run another loop
|
nop
|
nop
|
|
|
!! Init all dtlb entries
|
/* Init all dtlb entries */
|
mov 0x30, %g1
|
mov 0x30, %g1
|
mov %g0, %g2
|
mov %g0, %g2
|
dtlb_init_loop:
|
dtlb_init_loop:
|
stxa %g0, [%g1] 0x58 !! DMMU TLB Tag Access register=0
|
stxa %g0, [%g1] 0x58 !! DMMU TLB Tag Access register=0
|
stxa %g0, [%g2] 0x5d !! DMMU TLB Data Access register=0, g2 values from 0x000 to 0x7f8
|
stxa %g0, [%g2] 0x5d !! DMMU TLB Data Access register=0, g2 values from 0x000 to 0x7f8
|
|
|
add %g2, 8, %g2 !! increment the g2 register 64 bits each time
|
add %g2, 8, %g2 !! increment the g2 register 64 bits each time
|
cmp %g2, 0x200 !! compare g2 with 512
|
cmp %g2, 0x200 !! compare g2 with 512
|
bne dtlb_init_loop !! if (g2!=512) then run another loop
|
bne dtlb_init_loop !! if (g2!=512) then run another loop
|
nop
|
nop
|
|
|
!! Clear itlb/dtlb valid
|
/* Clear itlb/dtlb valid */
|
stxa %g0, [%g0] 0x60 !! ASI_ITLB_INVALIDATE_ALL(IMMU TLB Invalidate register)=0
|
stxa %g0, [%g0] 0x60 !! ASI_ITLB_INVALIDATE_ALL(IMMU TLB Invalidate register)=0
|
mov 0x8, %g1
|
mov 0x8, %g1
|
stxa %g0, [%g0 + %g1] 0x60 !! ASI_DTLB_INVALIDATE_ALL(DMMU TLB Invalidate register)=0
|
stxa %g0, [%g0 + %g1] 0x60 !! ASI_DTLB_INVALIDATE_ALL(DMMU TLB Invalidate register)=0
|
|
|
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
|
/********************************/
|
!! End of inserted instructions !!
|
/* End of inserted instructions */
|
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
|
/********************************/
|
|
|
!! Initialize primary context register
|
/* Initialize primary context register = 0 */
|
mov 0x8, %l1
|
mov 0x8, %l1
|
stxa %g0, [%l1] 0x21
|
stxa %g0, [%l1] 0x21
|
|
/* Initialize secondary context register = 0 */
|
!! Initialize secondary context register
|
|
mov 0x10, %l1
|
mov 0x10, %l1
|
stxa %g0, [%l1] 0x21
|
stxa %g0, [%l1] 0x21
|
|
|
!! Initialize dtsb entry for i context zero ps0, ps1
|
/* LSU_CTL_REG[3]=1 (DMMU enabled)
|
!! Set LSU Control Register to enable icache, dcache, immu, dmmu
|
LSU_CTL_REG[2]=1 (IMMU enabled)
|
/*
|
LSU_CTL_REG[1]=0 (L1-dcache disabled)
|
!! SunStudio version
|
LSU_CTL_REG[0]=0 (L1-icache disabled) */
|
setx cregs_lsu_ctl_reg_r64, %g1, %l1
|
mov 0xC, %l1 !! all enabled
|
*/
|
|
!! GCC version
|
|
!! LSU_CTL_REG[3]=1 (DMMU enabled)
|
|
!! LSU_CTL_REG[2]=1 (IMMU enabled)
|
|
!! LSU_CTL_REG[1]=1 (L1-dcache enabled)
|
|
!! LSU_CTL_REG[0]=1 (L1-icache enabled)
|
|
mov 0xF, %l1
|
|
stxa %l1, [%g0] (69)
|
stxa %l1, [%g0] (69)
|
|
|
!! Reset handler
|
/* Jump to program in RAM */
|
/*
|
|
!! SunStudio version
|
|
setx HPriv_Reset_Handler, %g1, %g2
|
|
*/
|
|
!! GCC version
|
|
sethi %hi(0), %g1
|
sethi %hi(0), %g1
|
sethi %hi(0x40000), %g2 !! New jump address in memory (used by last op of this file)
|
sethi %hi(0x40000), %g2 !! Jump address in RAM
|
mov %g1, %g1
|
mov %g1, %g1
|
mov %g2, %g2
|
mov %g2, %g2
|
sllx %g1, 0x20, %g1
|
sllx %g1, 0x20, %g1
|
or %g2, %g1, %g2
|
or %g2, %g1, %g2
|
|
|
|
/* HTSTATE[TL=1] */
|
rdhpr %hpstate, %g3
|
rdhpr %hpstate, %g3
|
wrpr 1, %tl !! current trap level = 1
|
wrpr 1, %tl !! current trap level = 1
|
|
mov 0x0, %l1 !! l1 = 0
|
!! HTSTATE
|
wrhpr %g3, %g0, %htstate !! reset HTSTATE reg that store hyperpriviliged state after a trap
|
/*
|
|
!! SunStudio version
|
|
setx cregs_htstate_r64, %g1, %g4
|
|
*/
|
|
!! GCC version
|
|
sethi %hh(0x0),%g1
|
|
or %g1,%hm(0x0),%g1
|
|
sllx %g1,32,%g1
|
|
sethi %hi(0x0),%l1
|
|
or %l1,%g1,%l1
|
|
or %l1,%lo(0x0),%l1
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wrhpr %g4, %g0, %htstate !! reset HTSTATE reg that store hyperpriviliged state after a trap
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wrpr 0, %tl !! current trap level = 0 (No Trap)
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wrpr 0, %tl !! current trap level = 0 (No Trap)
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mov 0x0, %o0 !! please don't delete since used in customized IMMU miss trap
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mov 0x0, %o0 !! please don’t delete since used in customized IMMU miss trap
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jmp %g2
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!! wrhpr %g0, 0x800, %hpstate !! ensure bit 11 of the HPSTATE register is set
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nop
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nop
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No newline at end of file
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No newline at end of file
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/* Jump in RAM */
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jmp %g2 !! jump to 0x40000
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!! wrhpr %g0, 0x804, %hpstate !! ensure bit 11 of the HPSTATE register is set
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nop
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nop
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No newline at end of file
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