Line 4... |
Line 4... |
* Cutdown version from the original OpenSPARC T1:
|
* Cutdown version from the original OpenSPARC T1:
|
*
|
*
|
* $T1_ROOT/verif/diag/assembly/include/hred_reset_handler.s
|
* $T1_ROOT/verif/diag/assembly/include/hred_reset_handler.s
|
*
|
*
|
* Main changes:
|
* Main changes:
|
* - L2 cache handling commented out since not implemented in S1 Core ;
|
* - L1 and L2 cache handling are not enabled;
|
* - Interrupt Queues handling currently commented out since causes troubles in S1 Core.
|
* - Interrupt Queues handling currently commented out since causes troubles in S1 Core.
|
*
|
*
|
* Sun Microsystems' copyright notices follow:
|
* Sun Microsystems' copyright notices follow:
|
*/
|
*/
|
|
|
Line 50... |
Line 50... |
*/
|
*/
|
|
|
!! Set LSU Diagnostic Register to use all ways for L1-icache and L1-dcache
|
!! Set LSU Diagnostic Register to use all ways for L1-icache and L1-dcache
|
setx cregs_lsu_diag_reg_r64, %g1, %l1 !! aka "clr %l1"
|
setx cregs_lsu_diag_reg_r64, %g1, %l1 !! aka "clr %l1"
|
mov 0x10, %g1
|
mov 0x10, %g1
|
stxa %l1, [%g1] ASI_LSU_DIAG_REG !! aka "stxa %l1, [%g1] (66)"
|
stxa %l1, [%g1] (66) !! aka "stxa %l1, [%g1] ASI_LSU_DIAG_REG"
|
|
|
!! Set LSU Control Register to enable L1-icache and L1-dcache
|
!! Set LSU Control Register to enable L1-icache and L1-dcache: not enabled in S1 Core
|
|
/*
|
setx (CREGS_LSU_CTL_REG_IC | (CREGS_LSU_CTL_REG_DC << 1)), %g1, %l1 !! aka "mov 3, %l1"
|
setx (CREGS_LSU_CTL_REG_IC | (CREGS_LSU_CTL_REG_DC << 1)), %g1, %l1 !! aka "mov 3, %l1"
|
stxa %l1, [%g0] ASI_LSU_CTL_REG !! aka "stxa %l1, [ %g0 ] (69)"
|
stxa %l1, [ %g0 ] (69) !! aka "stxa %l1, [%g0] ASI_LSU_CTL_REG"
|
|
*/
|
!! Set hpstate.red = 0 and hpstate.enb = 1
|
!! Set hpstate.red = 0 and hpstate.enb = 1
|
rdhpr %hpstate, %l1
|
rdhpr %hpstate, %l1
|
wrhpr %l1, 0x820, %hpstate
|
wrhpr %l1, 0x820, %hpstate
|
|
|
!! Initialize Interrupt Queue Registers: Currently disabled in S1 Core
|
!! Initialize Interrupt Queue Registers: Currently disabled in S1 Core
|
Line 111... |
Line 112... |
stxa %g0, [%g0 + %g1] 0x50
|
stxa %g0, [%g0 + %g1] 0x50
|
stxa %g0, [%g0 + %g1] 0x58
|
stxa %g0, [%g0 + %g1] 0x58
|
|
|
!! Enable error trap
|
!! Enable error trap
|
setx cregs_sparc_error_en_reg_r64, %g1, %l1 !! aka "mov 3, %l1"
|
setx cregs_sparc_error_en_reg_r64, %g1, %l1 !! aka "mov 3, %l1"
|
stxa %l1, [%g0] ASI_SPARC_ERROR_EN_REG !! aka "stxa %l1, [%g0] (75)"
|
stxa %l1, [%g0] (75) !! aka "stxa %l1, [%g0] ASI_SPARC_ERROR_EN_REG"
|
|
|
!! Enable L2-ucache error trap: Unused in S1 Core
|
!! Enable L2-ucache error trap: Unused in S1 Core
|
/*
|
/*
|
setx cregs_l2_error_en_reg_r64, %g1, %l1
|
setx cregs_l2_error_en_reg_r64, %g1, %l1
|
|
|
Line 224... |
Line 225... |
!! Initialize secondary context register
|
!! Initialize secondary context register
|
mov 0x10, %l1
|
mov 0x10, %l1
|
stxa %g0, [%l1] 0x21
|
stxa %g0, [%l1] 0x21
|
|
|
!! Initialize dtsb entry for i context zero ps0, ps1
|
!! Initialize dtsb entry for i context zero ps0, ps1
|
|
/*
|
!! Set LSU Control Register to enable icache, dcache, immu, dmmu
|
!! Set LSU Control Register to enable icache, dcache, immu, dmmu
|
setx cregs_lsu_ctl_reg_r64, %g1, %l1 !! aka "mov 0xf, %l1"
|
setx cregs_lsu_ctl_reg_r64, %g1, %l1 !! aka "mov 0xf, %l1"
|
stxa %l1, [%g0] ASI_LSU_CTL_REG !! aka "stxa %l1, [%g0] (69)"
|
*/
|
|
!! Set LSU Control Register to enable immu, dmmu but NOT icache, dcache
|
|
mov 0xc, %l1
|
|
stxa %l1, [%g0] (69) !! aka "stxa %l1, [%g0] ASI_LSU_CTL_REG"
|
|
|
setx HPriv_Reset_Handler, %g1, %g2
|
setx HPriv_Reset_Handler, %g1, %g2
|
!! this instructions expands as
|
!! this instructions expands as
|
!! sethi %hi(0), %g1
|
!! sethi %hi(0), %g1
|
!! sethi %hi(0x144000), %g2
|
!! sethi %hi(0x144000), %g2
|