| Line 4... |
Line 4... |
* Cutdown version from the original OpenSPARC T1:
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* Cutdown version from the original OpenSPARC T1:
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*
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*
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* $T1_ROOT/verif/diag/assembly/include/hred_reset_handler.s
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* $T1_ROOT/verif/diag/assembly/include/hred_reset_handler.s
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*
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*
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* Main changes:
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* Main changes:
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* - L2 cache handling commented out since not implemented in S1 Core ;
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* - L1 and L2 cache handling are not enabled;
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* - Interrupt Queues handling currently commented out since causes troubles in S1 Core.
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* - Interrupt Queues handling currently commented out since causes troubles in S1 Core.
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*
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*
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* Sun Microsystems' copyright notices follow:
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* Sun Microsystems' copyright notices follow:
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*/
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*/
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| Line 50... |
Line 50... |
*/
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*/
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!! Set LSU Diagnostic Register to use all ways for L1-icache and L1-dcache
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!! Set LSU Diagnostic Register to use all ways for L1-icache and L1-dcache
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setx cregs_lsu_diag_reg_r64, %g1, %l1 !! aka "clr %l1"
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setx cregs_lsu_diag_reg_r64, %g1, %l1 !! aka "clr %l1"
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mov 0x10, %g1
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mov 0x10, %g1
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stxa %l1, [%g1] ASI_LSU_DIAG_REG !! aka "stxa %l1, [%g1] (66)"
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stxa %l1, [%g1] (66) !! aka "stxa %l1, [%g1] ASI_LSU_DIAG_REG"
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!! Set LSU Control Register to enable L1-icache and L1-dcache
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!! Set LSU Control Register to enable L1-icache and L1-dcache: not enabled in S1 Core
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/*
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setx (CREGS_LSU_CTL_REG_IC | (CREGS_LSU_CTL_REG_DC << 1)), %g1, %l1 !! aka "mov 3, %l1"
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setx (CREGS_LSU_CTL_REG_IC | (CREGS_LSU_CTL_REG_DC << 1)), %g1, %l1 !! aka "mov 3, %l1"
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stxa %l1, [%g0] ASI_LSU_CTL_REG !! aka "stxa %l1, [ %g0 ] (69)"
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stxa %l1, [ %g0 ] (69) !! aka "stxa %l1, [%g0] ASI_LSU_CTL_REG"
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*/
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!! Set hpstate.red = 0 and hpstate.enb = 1
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!! Set hpstate.red = 0 and hpstate.enb = 1
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rdhpr %hpstate, %l1
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rdhpr %hpstate, %l1
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wrhpr %l1, 0x820, %hpstate
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wrhpr %l1, 0x820, %hpstate
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!! Initialize Interrupt Queue Registers: Currently disabled in S1 Core
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!! Initialize Interrupt Queue Registers: Currently disabled in S1 Core
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| Line 111... |
Line 112... |
stxa %g0, [%g0 + %g1] 0x50
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stxa %g0, [%g0 + %g1] 0x50
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stxa %g0, [%g0 + %g1] 0x58
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stxa %g0, [%g0 + %g1] 0x58
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|
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!! Enable error trap
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!! Enable error trap
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setx cregs_sparc_error_en_reg_r64, %g1, %l1 !! aka "mov 3, %l1"
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setx cregs_sparc_error_en_reg_r64, %g1, %l1 !! aka "mov 3, %l1"
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stxa %l1, [%g0] ASI_SPARC_ERROR_EN_REG !! aka "stxa %l1, [%g0] (75)"
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stxa %l1, [%g0] (75) !! aka "stxa %l1, [%g0] ASI_SPARC_ERROR_EN_REG"
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!! Enable L2-ucache error trap: Unused in S1 Core
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!! Enable L2-ucache error trap: Unused in S1 Core
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/*
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/*
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setx cregs_l2_error_en_reg_r64, %g1, %l1
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setx cregs_l2_error_en_reg_r64, %g1, %l1
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| Line 224... |
Line 225... |
!! Initialize secondary context register
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!! Initialize secondary context register
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mov 0x10, %l1
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mov 0x10, %l1
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stxa %g0, [%l1] 0x21
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stxa %g0, [%l1] 0x21
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|
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!! Initialize dtsb entry for i context zero ps0, ps1
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!! Initialize dtsb entry for i context zero ps0, ps1
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/*
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!! Set LSU Control Register to enable icache, dcache, immu, dmmu
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!! Set LSU Control Register to enable icache, dcache, immu, dmmu
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setx cregs_lsu_ctl_reg_r64, %g1, %l1 !! aka "mov 0xf, %l1"
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setx cregs_lsu_ctl_reg_r64, %g1, %l1 !! aka "mov 0xf, %l1"
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stxa %l1, [%g0] ASI_LSU_CTL_REG !! aka "stxa %l1, [%g0] (69)"
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*/
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!! Set LSU Control Register to enable immu, dmmu but NOT icache, dcache
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mov 0xc, %l1
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stxa %l1, [%g0] (69) !! aka "stxa %l1, [%g0] ASI_LSU_CTL_REG"
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setx HPriv_Reset_Handler, %g1, %g2
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setx HPriv_Reset_Handler, %g1, %g2
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!! this instructions expands as
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!! this instructions expands as
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!! sethi %hi(0), %g1
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!! sethi %hi(0), %g1
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!! sethi %hi(0x144000), %g2
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!! sethi %hi(0x144000), %g2
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