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Line 33... |
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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*
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*
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* ========== Copyright Header End ============================================
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* ========== Copyright Header End ============================================
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*/
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*/
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#include "defines.h"
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!! Enable L2-ucache: Unused in S1 Core
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!! Enable L2-ucache: Unused in S1 Core
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/*
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/*
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setx cregs_l2_ctl_reg_r64, %g1, %l1 !! aka "wr %g0, 5, %asr26" "clr %l1"
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setx cregs_l2_ctl_reg_r64, %g1, %l1 !! aka "wr %g0, 5, %asr26" "clr %l1"
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mov 0xa9, %g1
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mov 0xa9, %g1
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sllx %g1, 32, %g1
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sllx %g1, 32, %g1
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| Line 48... |
Line 46... |
stx %l1, [%g1 + 0x80]
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stx %l1, [%g1 + 0x80]
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stx %l1, [%g1 + 0xc0]
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stx %l1, [%g1 + 0xc0]
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*/
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*/
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!! Set LSU Diagnostic Register to use all ways for L1-icache and L1-dcache
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!! Set LSU Diagnostic Register to use all ways for L1-icache and L1-dcache
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setx cregs_lsu_diag_reg_r64, %g1, %l1 !! aka "clr %l1"
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!!setx cregs_lsu_diag_reg_r64, %g1, %l1 !!ho sostituito questa istruzione con la sua espansione (!! aka "clr %l1")
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sethi %hh(0x0),%g1
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or %g1,%hm(0x0),%g1
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sllx %g1,32,%g1
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sethi %hi(0x0),%l1
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or %l1,%g1,%l1
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or %l1,%lo(0x0),%l1
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mov 0x10, %g1
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mov 0x10, %g1
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stxa %l1, [%g1] (66) !! aka "stxa %l1, [%g1] ASI_LSU_DIAG_REG"
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stxa %l1, [%g1] (66) !! aka "stxa %l1, [%g1] ASI_LSU_DIAG_REG"
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!! Set LSU Control Register to enable L1-icache and L1-dcache: not enabled in S1 Core
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!! Set LSU Control Register to enable L1-icache and L1-dcache: not enabled in S1 Core
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/*
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/*
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setx (CREGS_LSU_CTL_REG_IC | (CREGS_LSU_CTL_REG_DC << 1)), %g1, %l1 !! aka "mov 3, %l1"
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setx (CREGS_LSU_CTL_REG_IC | (CREGS_LSU_CTL_REG_DC << 1)), %g1, %l1 !! aka "mov 3, %l1"
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stxa %l1, [ %g0 ] (69) !! aka "stxa %l1, [%g0] ASI_LSU_CTL_REG"
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stxa %l1, [ %g0 ] (69) !! aka "stxa %l1, [%g0] ASI_LSU_CTL_REG"
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*/
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*/
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!! Set hpstate.red = 0 and hpstate.enb = 1
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!! Set hpstate.red = 0 and hpstate.enb = 1
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rdhpr %hpstate, %l1
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rdhpr %hpstate, %l1
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wrhpr %l1, 0x820, %hpstate
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and %l1,0x820,%l2
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xor %l2,0x800,%l2
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wrhpr %l1,%l2,%hpstate !!questo meccanismo "dovrebbe" assicurarni red=0 enb=1
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!!wrhpr %l1, 0x820, %hpstate !! in questo modo hpstate.red=1 altrimenti dovremmo usare 0x8000 inoltre troviamo red=1 e hpriv=0
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!! cmq dipende da l1, dovrebbe fare l1 xor 100000100000
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!!stiamo presumendo che red=1 e enb=0 precedentemente
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/*!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! !!momentaneamente ho tolto le istruzioni che ho aggiunto
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!!aggiunta dal file hboot_tlb_init.s
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!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
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! init all itlb entries
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!! mov 0x30, %g1
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!!mov %g0, %g2
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!!itlb_init_loop:
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!!stxa %g0, [ %g1 ] 0x50
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!!stxa %g0, [ %g2 ] 0x55 !!pulisce data e tag entry del buffer per TLB
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!!add %g2, 8, %g2 !!g2= somma 8 (byte) alla volta (64 bit)
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!!cmp %g2, 0x200 !!confronta con 512 (512*8=4096=0x1000), ma al max VA=0x7F8
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!!bne itlb_init_loop
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!!nop
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! init all dtlb entries
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!!mov 0x30, %g1
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!!mov %g0, %g2
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!!dtlb_init_loop:
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!!stxa %g0, [ %g1 ] 0x58
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!!stxa %g0, [ %g2 ] 0x5d
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!!add %g2, 8, %g2
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!!cmp %g2, 0x200
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!!bne dtlb_init_loop
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!!nop
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!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
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! Clear itlb/dtlb valid
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!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
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!!stxa %g0, [%g0] 0x60 ! ASI_ITLB_INVALIDATE_ALL
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!!mov 0x8, %g1
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!!stxa %g0, [%g0 + %g1] 0x60 ! ASI_DTLB_INVALIDATE_ALL
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!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
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!!fine aggiunta
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!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!*/
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!! Initialize Interrupt Queue Registers: Currently disabled in S1 Core
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!! Initialize Interrupt Queue Registers: Currently disabled in S1 Core
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/*
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/*
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wr %g0, 0x25, %asi
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wr %g0, 0x25, %asi
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Line 164... |
mov 0x18, %g1
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mov 0x18, %g1
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stxa %g0, [%g0 + %g1] 0x50
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stxa %g0, [%g0 + %g1] 0x50
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stxa %g0, [%g0 + %g1] 0x58
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stxa %g0, [%g0 + %g1] 0x58
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!! Enable error trap
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!! Enable error trap
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setx cregs_sparc_error_en_reg_r64, %g1, %l1 !! aka "mov 3, %l1"
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!!setx cregs_sparc_error_en_reg_r64, %g1, %l1 !!ho sostituito questa istruzione con la sua espansione e costante=3(!!aka "mov 3, %l1")
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sethi %hh(0x3),%g1
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or %g1,%hm(0x3),%g1
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sllx %g1,32,%g1
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sethi %hi(0x3),%l1
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or %l1,%g1,%l1
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or %l1,%lo(0x3),%l1
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stxa %l1, [%g0] (75) !! aka "stxa %l1, [%g0] ASI_SPARC_ERROR_EN_REG"
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stxa %l1, [%g0] (75) !! aka "stxa %l1, [%g0] ASI_SPARC_ERROR_EN_REG"
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!! Enable L2-ucache error trap: Unused in S1 Core
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!! Enable L2-ucache error trap: Unused in S1 Core
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/*
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/*
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setx cregs_l2_error_en_reg_r64, %g1, %l1
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setx cregs_l2_error_en_reg_r64, %g1, %l1
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| Line 131... |
Line 190... |
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!! Load Partition ID
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!! Load Partition ID
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rd %asr26, %l1
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rd %asr26, %l1
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set 0x0300, %g1 !! aka "sethi %hi(0x1c00), %g1" "or %g1, 0x300, %g1"
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set 0x0300, %g1 !! aka "sethi %hi(0x1c00), %g1" "or %g1, 0x300, %g1"
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and %l1, %g1, %l1
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and %l1, %g1, %l1
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srlx %l1, 8, %l1 !! %l1 has thread ID
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srlx %l1, 8, %l1 !! %l1 has thread ID
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setx part_id_list, %g1, %g2
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!!setx part_id_list, %g1, %g2
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!! this instruction expands as
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!! this instruction expands as
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!! "sethi %hi(0), %g1"
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sethi %hi(0), %g1
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!! "sethi %hi(0x4c000), %g2"
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sethi %hi(0x4c000), %g2 !! THIS INSTRUCTION CONTAINS THE ADDRESS IN MEMORY
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!! "mov %g1, %g1"
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mov %g1, %g1
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!! "mov %g2, %g2"
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mov %g2, %g2
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!! "sllx %g1, 0x20, %g1"
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sllx %g1, 0x20, %g1
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!! "or %g2, %g1, %g2"
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or %g2, %g1, %g2
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sllx %l1, 3, %l1 !! offset - partition list
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sllx %l1, 3, %l1 !! offset - partition list
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ldx [%g2 + %l1], %g2 !! %g2 contains partition ID
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ldx [%g2 + %l1], %g2 !! %g2 contains partition ID
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mov 0x80, %g1
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mov 0x80, %g1
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stxa %g2, [%g1] 0x58
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stxa %g2, [%g1] 0x58 !! BY FF - AFTER THIS INSTRUCTION WE GET TWO CONSECUTIVE ACCESSES
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!! Set Hypervisor Trap Base Address
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!! Set Hypervisor Trap Base Address
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setx HV_TRAP_BASE_PA, %l0, %l7 !! sethi %hi(0x80000), %l7
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!!setx HV_TRAP_BASE_PA, %l0, %l7 !!sostituita con la sua espansione e costante=0x80000(!!sethi %hi(0x80000), %l7)
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sethi %hh(0x80000),%g1
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or %g1,%hm(0x80000),%g1
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sllx %g1,32,%g1
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sethi %hi(0x80000),%l1
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or %l1,%g1,%l1
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or %l1,%lo(0x80000),%l1
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wrhpr %l7, %g0, %htba
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wrhpr %l7, %g0, %htba
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!! Load TSB config/base from memory and write to corresponding ASI's
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!! Load TSB config/base from memory and write to corresponding ASI's
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!! set tsb-reg (4 at present) for one partition
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!! set tsb-reg (4 at present) for one partition
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!! 2 i-config, 2-dconfig
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!! 2 i-config, 2-dconfig
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setx tsb_config_base_list, %l0, %g1
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!!setx tsb_config_base_list, %l0, %g1 !!sostituita con le successive istruzioni
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!! this instructions expands as
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!! this instructions expands as
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!! sethi %hi(0), %l0
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sethi %hi(0), %l0
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!! sethi %hi(0x4c000), %g1
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sethi %hi(0x4c000), %g1
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!! mov %l0, %l0
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mov %l0, %l0
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!! or %g1, 0x140, %g1
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or %g1, 0x140, %g1
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!! sllx %l0, 0x20, %l0
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sllx %l0, 0x20, %l0
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!! or %g1, %l0, %g1
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or %g1, %l0, %g1
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sllx %g2, 7, %g2 !! %g2 contains offset to tsb_config_base_list
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sllx %g2, 7, %g2 !! %g2 contains offset to tsb_config_base_list
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add %g1, %g2, %g1 !! %g1 contains pointer to tsb_config_base_list
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add %g1, %g2, %g1 !! %g1 contains pointer to tsb_config_base_list
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!! IMMU_CXT_Z_CONFIG (0x37, VA=0x00)
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!! IMMU_CXT_Z_CONFIG (0x37, VA=0x00)
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| Line 216... |
Line 283... |
!! Demap all itlb and dtlb
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!! Demap all itlb and dtlb
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mov 0x80, %o2
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mov 0x80, %o2
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stxa %g0, [%o2] 0x57
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stxa %g0, [%o2] 0x57
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stxa %g0, [%o2] 0x5f
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stxa %g0, [%o2] 0x5f
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!! Initialize primary context register
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!! Initialize primary context register
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mov 0x8, %l1
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mov 0x8, %l1
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stxa %g0, [%l1] 0x21
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stxa %g0, [%l1] 0x21
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!! Initialize secondary context register
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!! Initialize secondary context register
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| Line 233... |
Line 302... |
*/
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*/
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!! Set LSU Control Register to enable immu, dmmu but NOT icache, dcache
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!! Set LSU Control Register to enable immu, dmmu but NOT icache, dcache
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mov 0xc, %l1
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mov 0xc, %l1
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stxa %l1, [%g0] (69) !! aka "stxa %l1, [%g0] ASI_LSU_CTL_REG"
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stxa %l1, [%g0] (69) !! aka "stxa %l1, [%g0] ASI_LSU_CTL_REG"
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setx HPriv_Reset_Handler, %g1, %g2
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!!setx HPriv_Reset_Handler, %g1, %g2
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!! this instructions expands as
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!! this instructions expands as
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!! sethi %hi(0), %g1
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sethi %hi(0), %g1
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!! sethi %hi(0x144000), %g2
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sethi %hi(0x144000), %g2
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!! mov %g1, %g1
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mov %g1, %g1
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!! mov %g2, %g2
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mov %g2, %g2
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!! sllx %g1, 0x20, %g1
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sllx %g1, 0x20, %g1
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!! or %g2, %g1, %g2
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or %g2, %g1, %g2
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rdhpr %hpstate, %g3
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rdhpr %hpstate, %g3
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wrpr 1, %tl
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wrpr 1, %tl
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setx cregs_htstate_r64, %g1, %g4 !! aka "clr %g4"
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!!setx cregs_htstate_r64, %g1, %g4 !!sostituita con la successiva istruzione (!! aka "clr %g4")
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sethi %hh(0x0),%g1
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or %g1,%hm(0x0),%g1
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sllx %g1,32,%g1
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sethi %hi(0x0),%l1
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or %l1,%g1,%l1
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or %l1,%lo(0x0),%l1
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wrhpr %g4, %g0, %htstate
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wrhpr %g4, %g0, %htstate
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wrpr 0, %tl
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wrpr 0, %tl
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mov 0x0, %o0 !! aka "clr %o0", don't delete since used in customized IMMU miss trap
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mov 0x0, %o0 !! aka "clr %o0", don't delete since used in customized IMMU miss trap
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jmp %g2
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jmp %g2
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wrhpr %g0, 0x800, %hpstate
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wrhpr %g0, 0x800, %hpstate
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