Line 3... |
Line 3... |
# Set source and destination directories
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# Set source and destination directories
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SRC_DIR=$T1_ROOT/design/sys/iop
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SRC_DIR=$T1_ROOT/design/sys/iop
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DST_DIR=$S1_ROOT/hdl/rtl/sparc_core
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DST_DIR=$S1_ROOT/hdl/rtl/sparc_core
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|
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# Clean destination directory
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# Clean destination directory
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rm -rf $DST_DIR/*
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rm -f $DST_DIR/*.*
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mkdir $DST_DIR/include
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rm -f $DST_DIR/include/*.*
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|
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# Copy all the Verilog files of the SPARC Core into destination directory
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# Copy all the Verilog files of the SPARC Core into destination directory
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cp $SRC_DIR/include/*.h $DST_DIR/include
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cp $SRC_DIR/include/*.h $DST_DIR/include
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cp $SRC_DIR/srams/rtl/*.v $DST_DIR
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cp $SRC_DIR/srams/rtl/*.v $DST_DIR
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cp $SRC_DIR/analog/bw_clk/rtl/*.v $DST_DIR
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cp $SRC_DIR/analog/bw_clk/rtl/*.v $DST_DIR
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Line 42... |
Line 42... |
sed -e 's/assign all_stallreq = ifq_fcl_stallreq/assign all_stallreq = ifq_fcl_stallreq | wbm_spc_stallreq/g' > $DST_DIR/sparc_ifu_fcl_TMP.v
|
sed -e 's/assign all_stallreq = ifq_fcl_stallreq/assign all_stallreq = ifq_fcl_stallreq | wbm_spc_stallreq/g' > $DST_DIR/sparc_ifu_fcl_TMP.v
|
mv -f $DST_DIR/sparc_ifu_fcl_TMP.v $DST_DIR/sparc_ifu_fcl.v
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mv -f $DST_DIR/sparc_ifu_fcl_TMP.v $DST_DIR/sparc_ifu_fcl.v
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# Copy also behavioral libraries used for RTL simulations
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# Copy also behavioral libraries used for RTL simulations
|
DST_DIR=$S1_ROOT/hdl/behav/sparc_libs
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DST_DIR=$S1_ROOT/hdl/behav/sparc_libs
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rm -f $DST_DIR/*
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rm -f $DST_DIR/*.*
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cp $SRC_DIR/../../../lib/m1/m1.behV $DST_DIR/m1_lib.v
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cp $SRC_DIR/../../../lib/m1/m1.behV $DST_DIR/m1_lib.v
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cp $SRC_DIR/../../../lib/u1/u1.behV $DST_DIR/u1_lib.v
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cp $SRC_DIR/../../../lib/u1/u1.behV $DST_DIR/u1_lib.v
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