| Line 3... |
Line 3... |
# Set source and destination directories
|
# Set source and destination directories
|
SRC_DIR=$T1_ROOT/design/sys/iop
|
SRC_DIR=$T1_ROOT/design/sys/iop
|
DST_DIR=$S1_ROOT/hdl/rtl/sparc_core
|
DST_DIR=$S1_ROOT/hdl/rtl/sparc_core
|
|
|
# Clean destination directory
|
# Clean destination directory
|
rm -rf $DST_DIR/*
|
rm -f $DST_DIR/*.*
|
mkdir $DST_DIR/include
|
rm -f $DST_DIR/include/*.*
|
|
|
# Copy all the Verilog files of the SPARC Core into destination directory
|
# Copy all the Verilog files of the SPARC Core into destination directory
|
cp $SRC_DIR/include/*.h $DST_DIR/include
|
cp $SRC_DIR/include/*.h $DST_DIR/include
|
cp $SRC_DIR/srams/rtl/*.v $DST_DIR
|
cp $SRC_DIR/srams/rtl/*.v $DST_DIR
|
cp $SRC_DIR/analog/bw_clk/rtl/*.v $DST_DIR
|
cp $SRC_DIR/analog/bw_clk/rtl/*.v $DST_DIR
|
| Line 42... |
Line 42... |
sed -e 's/assign all_stallreq = ifq_fcl_stallreq/assign all_stallreq = ifq_fcl_stallreq | wbm_spc_stallreq/g' > $DST_DIR/sparc_ifu_fcl_TMP.v
|
sed -e 's/assign all_stallreq = ifq_fcl_stallreq/assign all_stallreq = ifq_fcl_stallreq | wbm_spc_stallreq/g' > $DST_DIR/sparc_ifu_fcl_TMP.v
|
mv -f $DST_DIR/sparc_ifu_fcl_TMP.v $DST_DIR/sparc_ifu_fcl.v
|
mv -f $DST_DIR/sparc_ifu_fcl_TMP.v $DST_DIR/sparc_ifu_fcl.v
|
|
|
# Copy also behavioral libraries used for RTL simulations
|
# Copy also behavioral libraries used for RTL simulations
|
DST_DIR=$S1_ROOT/hdl/behav/sparc_libs
|
DST_DIR=$S1_ROOT/hdl/behav/sparc_libs
|
rm -f $DST_DIR/*
|
rm -f $DST_DIR/*.*
|
cp $SRC_DIR/../../../lib/m1/m1.behV $DST_DIR/m1_lib.v
|
cp $SRC_DIR/../../../lib/m1/m1.behV $DST_DIR/m1_lib.v
|
cp $SRC_DIR/../../../lib/u1/u1.behV $DST_DIR/u1_lib.v
|
cp $SRC_DIR/../../../lib/u1/u1.behV $DST_DIR/u1_lib.v
|
|
|
