| Line 36... |
Line 36... |
//
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//
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//
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//
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//
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//
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`include "builddate.v"
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`include "builddate.v"
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//
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//
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`define IMPLEMENT_ONCHIP_RAM
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// `define IMPLEMENT_ONCHIP_RAM
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`ifndef VERILATOR
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`ifndef VERILATOR
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`define FANCY_ICAP_ACCESS
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`define FANCY_ICAP_ACCESS
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`endif
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`endif
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`define FLASH_ACCESS
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`define FLASH_ACCESS
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`define DBG_SCOPE // About 204 LUTs, at 2^6 addresses
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`define DBG_SCOPE // About 204 LUTs, at 2^6 addresses
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`define INCLUDE_RTC // About 90 LUTs
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`define INCLUDE_RTC // About 90 LUTs
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`define WBUBUS
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module altbusmaster(i_clk, i_rst,
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module altbusmaster(i_clk, i_rst,
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// DEPP I/O Control
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// DEPP I/O Control
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i_depp_astb_n, i_depp_dstb_n, i_depp_write_n,
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i_depp_astb_n, i_depp_dstb_n, i_depp_write_n,
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i_depp_data, o_depp_data, o_depp_wait,
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i_depp_data, o_depp_data, o_depp_wait,
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// External UART interface
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// External UART interface
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| Line 121... |
Line 122... |
//
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//
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//
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//
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// The BUS master (source): The WB to UART conversion bus
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// The BUS master (source): The WB to UART conversion bus
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//
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//
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//
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//
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wbubus busbdriver(i_clk, i_rx_stb, i_rx_data,
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wire dep_rx_stb, dep_tx_stb, dep_tx_busy;
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wire [7:0] dep_rx_data, dep_tx_data;
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deppbyte deppdrive(i_clk,
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i_depp_astb_n, i_depp_dstb_n, i_depp_write_n,
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i_depp_data, o_depp_data, o_depp_wait,
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dep_rx_stb, dep_rx_data,
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dep_tx_stb, dep_tx_data, dep_tx_busy);
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wbubus busbdriver(i_clk,
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// i_rx_stb, i_rx_data, // UART control
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dep_rx_stb, dep_rx_data, // DEPP control
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// The wishbone interface
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// The wishbone interface
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wb_cyc, wb_stb, wb_we, w_wbu_addr, wb_data,
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wb_cyc, wb_stb, wb_we, w_wbu_addr, wb_data,
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wb_ack, wb_stall, wb_err, wb_idata,
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wb_ack, wb_stall, wb_err, wb_idata,
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w_interrupt,
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w_interrupt,
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// Provide feedback to the UART
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// Provide feedback to the DEPP interface
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o_tx_stb, o_tx_data, i_tx_busy);
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dep_tx_stb, dep_tx_data, dep_tx_busy);
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assign o_uart_rts = (~rx_rdy);
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// // Provide feedback to the UART
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// o_tx_stb, o_tx_data, i_tx_busy
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// assign o_uart_rts = (~rx_rdy);
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`else
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`else
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//
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//
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//
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//
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// Another BUS master (source): A conversion from DEPP to busmaster
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// Another BUS master (source): A conversion from DEPP to busmaster
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//
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//
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| Line 237... |
Line 250... |
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//
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//
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//
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//
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//
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//
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reg rx_rdy;
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reg rx_rdy;
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wire [10:0] int_vector;
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wire [11:0] int_vector;
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assign int_vector = { gpio_int, pwm_int, keypad_int,
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assign int_vector = { flash_interrupt, gpio_int, pwm_int, keypad_int,
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~i_tx_busy, rx_rdy, tmrb_int, tmra_int,
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~i_tx_busy, rx_rdy, tmrb_int, tmra_int,
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rtc_interrupt, scop_interrupt,
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rtc_interrupt, scop_interrupt,
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wb_err, button_int };
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wb_err, button_int };
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wire [31:0] pic_data;
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wire [31:0] pic_data;
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icontrol #(11) pic(i_clk, 1'b0, (wb_stb)&&(io_sel)
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icontrol #(12) pic(i_clk, 1'b0, (wb_stb)&&(io_sel)
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&&(wb_addr[3:0]==4'h0)&&(wb_we),
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&&(wb_addr[3:0]==4'h0)&&(wb_we),
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wb_data, pic_data, int_vector, w_interrupt);
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wb_data, pic_data, int_vector, w_interrupt);
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initial bus_err_addr = 0; // `DATESTAMP;
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initial bus_err_addr = 0; // `DATESTAMP;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (wb_err)
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if (wb_err)
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bus_err_addr <= wb_addr;
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bus_err_addr <= wb_addr;
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wire zta_ack, zta_stall, ztb_ack, ztb_stall;
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wire [31:0] timer_a, timer_b;
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wire [31:0] timer_a, timer_b;
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wire zta_ack, zta_stall, ztb_ack, ztb_stall;
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ziptimer #(32,20)
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ziptimer #(32,20)
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zipt_a(i_clk, 1'b0, 1'b1, wb_cyc,
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zipt_a(i_clk, 1'b0, 1'b1, wb_cyc,
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(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h2),
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(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h2),
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wb_we, wb_data, zta_ack, zta_stall, timer_a,
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wb_we, wb_data, zta_ack, zta_stall, timer_a,
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tmra_int);
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tmra_int);
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| Line 378... |
Line 391... |
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//
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//
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// FLASH MEMORY CONFIGURATION ACCESS
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// FLASH MEMORY CONFIGURATION ACCESS
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//
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//
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wire flash_cs_n, flash_sck, flash_mosi;
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wbqspiflashp #(24) flashmem(i_clk,
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wbqspiflashp #(24) flashmem(i_clk,
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wb_cyc,(wb_stb&&flash_sel),(wb_stb)&&(flctl_sel),wb_we,
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wb_cyc,(wb_stb)&&(flash_sel),(wb_stb)&&(flctl_sel),wb_we,
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wb_addr[(24-3):0], wb_data,
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wb_addr[(24-3):0], wb_data,
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flash_ack, flash_stall, flash_data,
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flash_ack, flash_stall, flash_data,
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o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
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o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
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flash_interrupt);
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flash_interrupt);
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