| Line 42... |
Line 42... |
`ifndef VERILATOR
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`ifndef VERILATOR
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`define FANCY_ICAP_ACCESS
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`define FANCY_ICAP_ACCESS
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`endif
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`endif
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`define FLASH_ACCESS
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`define FLASH_ACCESS
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`define DBG_SCOPE // About 204 LUTs, at 2^6 addresses
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`define DBG_SCOPE // About 204 LUTs, at 2^6 addresses
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// `define COMPRESSED_SCOPE
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`define INCLUDE_SECOND_TIMER
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`define SECOND_TIMER_IS_WATCHDOG
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`define INCLUDE_RTC // About 90 LUTs
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`define INCLUDE_RTC // About 90 LUTs
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`define FULL_BUSERR_CALCULATION
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`define WBUBUS
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`define WBUBUS
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module altbusmaster(i_clk, i_rst,
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module altbusmaster(i_clk, i_rst,
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// DEPP I/O Control
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// DEPP I/O Control
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i_depp_astb_n, i_depp_dstb_n, i_depp_write_n,
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i_depp_astb_n, i_depp_dstb_n, i_depp_write_n,
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i_depp_data, o_depp_data, o_depp_wait,
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i_depp_data, o_depp_data, o_depp_wait,
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| Line 165... |
Line 169... |
assign wb_addr = w_wbu_addr;
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assign wb_addr = w_wbu_addr;
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endgenerate
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endgenerate
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wire io_sel, flash_sel, flctl_sel, scop_sel, cfg_sel, mem_sel,
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wire io_sel, flash_sel, flctl_sel, scop_sel, cfg_sel, mem_sel,
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rtc_sel, none_sel, many_sel;
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rtc_sel, none_sel, many_sel;
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wire flash_ack, scop_ack, cfg_ack, mem_ack;
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wire flash_ack, scop_ack, cfg_ack, mem_ack, many_ack;
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wire rtc_ack, rtc_stall;
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wire rtc_ack, rtc_stall;
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`ifdef INCLUDE_RTC
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`ifdef INCLUDE_RTC
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assign rtc_stall = 1'b0;
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assign rtc_stall = 1'b0;
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`endif
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`endif
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wire io_stall, flash_stall, scop_stall, cfg_stall, mem_stall;
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wire io_stall, flash_stall, scop_stall, cfg_stall, mem_stall;
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| Line 220... |
Line 224... |
assign rtc_sel =((wb_cyc)&&(io_addr[5:3]==3'h1));
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assign rtc_sel =((wb_cyc)&&(io_addr[5:3]==3'h1));
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`endif
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`endif
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assign mem_sel =((wb_cyc)&&(io_addr[5:4]==2'h1));
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assign mem_sel =((wb_cyc)&&(io_addr[5:4]==2'h1));
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assign flash_sel=((wb_cyc)&&(io_addr[5]));
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assign flash_sel=((wb_cyc)&&(io_addr[5]));
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assign none_sel =((wb_cyc)&&(wb_stb)&&(io_addr==6'h0));
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`ifdef FULL_BUSERR_CALCULATION
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assign none_sel =((wb_cyc)&&(wb_stb)&&
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((io_addr==6'h0)
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||((~io_addr[5])&&(|wb_addr[22:14]))
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||((io_addr[5:4]==2'b00)&&(|wb_addr[12])))
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);
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assign many_sel =((wb_cyc)&&(wb_stb)&&(
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assign many_sel =((wb_cyc)&&(wb_stb)&&(
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{3'h0, io_sel}
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{3'h0, io_sel}
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+{3'h0, flctl_sel}
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+{3'h0, flctl_sel}
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+{3'h0, scop_sel}
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+{3'h0, scop_sel}
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+{3'h0, cfg_sel}
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+{3'h0, cfg_sel}
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+{3'h0, rtc_sel}
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+{3'h0, rtc_sel}
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+{3'h0, mem_sel}
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+{3'h0, mem_sel}
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+{3'h0, flash_sel} > 1));
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+{3'h0, flash_sel} > 1));
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// assign many_sel = 1'b0;
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wire many_ack;
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assign many_ack =((wb_cyc)&&(
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assign many_ack =((wb_cyc)&&(
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{3'h0, io_ack}
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{3'h0, io_ack}
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+{3'h0, scop_ack}
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+{3'h0, scop_ack}
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+{3'h0, cfg_ack}
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+{3'h0, cfg_ack}
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`ifdef INCLUDE_RTC
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`ifdef INCLUDE_RTC
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+{3'h0, rtc_ack}
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+{3'h0, rtc_ack}
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`endif
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`endif
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+{3'h0, mem_ack}
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+{3'h0, mem_ack}
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+{3'h0, flash_ack} > 1));
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+{3'h0, flash_ack} > 1));
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`else
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assign many_ack = 1'b0;
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assign many_sel = 1'b0;
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assign none_sel =((wb_cyc)&&(wb_stb)&&(io_addr==6'h0));
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`endif
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wire flash_interrupt, scop_interrupt, tmra_int, tmrb_int,
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wire flash_interrupt, scop_interrupt, tmra_int, tmrb_int,
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rtc_interrupt, gpio_int, pwm_int, keypad_int,button_int;
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rtc_interrupt, gpio_int, pwm_int, keypad_int,button_int;
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//
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//
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//
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//
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//
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//
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reg rx_rdy;
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reg rx_rdy;
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wire [11:0] int_vector;
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wire [11:0] int_vector;
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assign int_vector = { flash_interrupt, gpio_int, pwm_int, keypad_int,
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assign int_vector = {
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flash_interrupt, gpio_int, pwm_int, keypad_int,
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(~o_tx_stb), rx_rdy,
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(~o_tx_stb), rx_rdy,
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tmrb_int, tmra_int,
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tmrb_int, tmra_int,
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rtc_interrupt, scop_interrupt,
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rtc_interrupt, scop_interrupt,
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wb_err, button_int };
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wb_err, button_int };
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| Line 269... |
Line 281... |
if (wb_err)
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if (wb_err)
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bus_err_addr <= wb_addr;
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bus_err_addr <= wb_addr;
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wire [31:0] timer_a, timer_b;
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wire [31:0] timer_a, timer_b;
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wire zta_ack, zta_stall, ztb_ack, ztb_stall;
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wire zta_ack, zta_stall, ztb_ack, ztb_stall;
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ziptimer #(32,31)
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ziptimer #(32,31,1)
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zipt_a(i_clk, 1'b0, 1'b1, wb_cyc,
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zipt_a(i_clk, 1'b0, 1'b1, wb_cyc,
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`ifdef INCLUDE_SECOND_TIMER
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(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h2),
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(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h2),
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`else
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(wb_stb)&&(io_sel)&&(wb_addr[3:1]==3'h1),
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`endif
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wb_we, wb_data, zta_ack, zta_stall, timer_a,
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wb_we, wb_data, zta_ack, zta_stall, timer_a,
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tmra_int);
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tmra_int);
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ziptimer #(32,31)
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`ifdef INCLUDE_SECOND_TIMER
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`ifdef SECOND_TIMER_IS_WATCHDOG
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ziptimer #(32,31,0)
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zipt_b(i_clk, 1'b0, 1'b1, wb_cyc,
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zipt_b(i_clk, 1'b0, 1'b1, wb_cyc,
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(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h3),
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(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h3),
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wb_we, wb_data, ztb_ack, ztb_stall, timer_b,
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wb_we, wb_data, ztb_ack, ztb_stall, timer_b,
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tmrb_int);
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tmrb_int);
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`else
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ziptimer #(32,31,1)
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zipt_b(i_clk, 1'b0, 1'b1, wb_cyc,
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(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h3),
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wb_we, wb_data, ztb_ack, ztb_stall, timer_b,
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tmrb_int);
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`endif
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`else
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// assign timer_b = 32'h000;
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assign timer_b = timer_a;
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assign tmrb_int = 1'b0;
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`endif
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wire [31:0] rtc_data;
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wire [31:0] rtc_data;
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`ifdef INCLUDE_RTC
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`ifdef INCLUDE_RTC
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wire rtcd_ack, rtcd_stall, ppd;
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wire rtcd_ack, rtcd_stall, ppd;
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// rtcdate thedate(i_clk, ppd, wb_cyc, (wb_stb)&&(io_sel), wb_we,
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// rtcdate thedate(i_clk, ppd, wb_cyc, (wb_stb)&&(io_sel), wb_we,
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| Line 332... |
Line 362... |
pwm_int);
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pwm_int);
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//
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//
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// Special Purpose I/O: Keypad, button, LED status and control
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// Special Purpose I/O: Keypad, button, LED status and control
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//
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//
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wire [3:0] w_led;
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spio thespio(i_clk, wb_cyc,(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h5),wb_we,
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spio thespio(i_clk, wb_cyc,(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h5),wb_we,
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wb_data, spio_data, o_kp_col, i_kp_row, i_btn, o_led,
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wb_data, spio_data, o_kp_col, i_kp_row, i_btn, w_led,
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keypad_int, button_int);
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keypad_int, button_int);
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assign o_led = { w_led[3]|w_interrupt,w_led[2]|zip_cpu_int,w_led[1:0] };
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//
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//
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// General purpose (sort of) I/O: (Bottom two bits robbed in each
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// General purpose (sort of) I/O: (Bottom two bits robbed in each
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// direction for an I2C link at the toplevel.v design)
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// direction for an I2C link at the toplevel.v design)
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//
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//
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| Line 448... |
Line 480... |
wire [31:0] scop_cfg_data;
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wire [31:0] scop_cfg_data;
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wire scop_cfg_ack, scop_cfg_stall, scop_cfg_interrupt;
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wire scop_cfg_ack, scop_cfg_stall, scop_cfg_interrupt;
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`ifdef DBG_SCOPE
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`ifdef DBG_SCOPE
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wire scop_cfg_trigger;
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wire scop_cfg_trigger;
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assign scop_cfg_trigger = (wb_cyc)&&(wb_stb)&&(cfg_sel);
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assign scop_cfg_trigger = (wb_cyc)&&(wb_stb)&&(cfg_sel);
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wbscope #(5'ha) wbcfgscope(i_clk, 1'b1, scop_cfg_trigger, cfg_scope,
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wire scop_trigger = scop_cfg_trigger;
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`ifdef COMPRESSED_SCOPE
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wbscopc #(5'ha)
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`else
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wbscope #(5'ha)
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`endif
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wbcfgscope(i_clk, 1'b1, scop_trigger,
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cfg_scope,
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// Wishbone interface
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// Wishbone interface
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i_clk, wb_cyc, (wb_stb)&&(scop_sel),
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i_clk, wb_cyc, (wb_stb)&&(scop_sel),
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wb_we, wb_addr[0], wb_data,
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wb_we, wb_addr[0], wb_data,
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scop_cfg_ack, scop_cfg_stall, scop_cfg_data,
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scop_cfg_ack, scop_cfg_stall, scop_cfg_data,
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scop_cfg_interrupt);
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scop_cfg_interrupt);
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