OpenCores
URL https://opencores.org/ocsvn/s6soc/s6soc/trunk

Subversion Repositories s6soc

[/] [s6soc/] [trunk/] [rtl/] [altbusmaster.v] - Diff between revs 46 and 51

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 46 Rev 51
Line 41... Line 41...
//
//
`include "builddate.v"
`include "builddate.v"
//
//
// `define      IMPLEMENT_ONCHIP_RAM
// `define      IMPLEMENT_ONCHIP_RAM
`define FLASH_ACCESS
`define FLASH_ACCESS
// `define      DBG_SCOPE       // About 204 LUTs, at 2^6 addresses
`define DBG_SCOPE       // About 204 LUTs, at 2^6 addresses
// `define      COMPRESSED_SCOPE
// `define      COMPRESSED_SCOPE
`define WBUBUS
`define WBUBUS
 
// `define      LOWLOGIC_FLASH
module  altbusmaster(i_clk, i_rst,
module  altbusmaster(i_clk, i_rst,
                // DEPP I/O Control
                // DEPP I/O Control
                i_depp_astb_n, i_depp_dstb_n, i_depp_write_n,
                i_depp_astb_n, i_depp_dstb_n, i_depp_write_n,
                        i_depp_data, o_depp_data, o_depp_wait,
                        i_depp_data, o_depp_data, o_depp_wait,
                // External UART interface
                // External UART interface
Line 61... Line 62...
                i_kp_row, o_kp_col,
                i_kp_row, o_kp_col,
                // UART control
                // UART control
                o_uart_setup,
                o_uart_setup,
                // GPIO lines
                // GPIO lines
                i_gpio, o_gpio);
                i_gpio, o_gpio);
        parameter       BUS_ADDRESS_WIDTH=23,
        parameter       BUS_ADDRESS_WIDTH=23;
                        BAW=BUS_ADDRESS_WIDTH; // 24bits->2,258,23b->2181
        localparam      BAW=BUS_ADDRESS_WIDTH; // 24bits->2,258,23b->2181
        // 2^14 bytes requires a LGMEMSZ of 14, and 12 address bits ranging from
        // 2^14 bytes requires a LGMEMSZ of 14, and 12 address bits ranging from
        // 0 to 11.  As with many other devices, the wb_cyc line is more for
        // 0 to 11.  As with many other devices, the wb_cyc line is more for
        // form than anything else--it is ignored by the memory itself.
        // form than anything else--it is ignored by the memory itself.
        localparam      LGMEMSZ=14;     // Takes 8 BLKRAM16 elements for LGMEMSZ=14
        localparam      LGMEMSZ=14;     // Takes 8 BLKRAM16 elements for LGMEMSZ=14
        // As with the memory size, the flash size is also measured in log_2 of
        // As with the memory size, the flash size is also measured in log_2 of
Line 84... Line 85...
        output  reg             o_tx_stb;
        output  reg             o_tx_stb;
        output  reg     [7:0]    o_tx_data;
        output  reg     [7:0]    o_tx_data;
        input                   i_tx_busy;
        input                   i_tx_busy;
        output  wire            o_uart_rts_n;
        output  wire            o_uart_rts_n;
        // SPI flash control
        // SPI flash control
        output  wire            o_qspi_cs_n, o_qspi_sck;
        output  wire            o_qspi_cs_n;
 
`ifdef  LOWLOGIC_FLASH
 
        output  wire    [1:0]    o_qspi_sck;
 
`else   // LOWLOGIC_FLASH
 
        output  wire            o_qspi_sck;
 
`endif  // LOWLOGIC_FLASH
        output  wire    [3:0]    o_qspi_dat;
        output  wire    [3:0]    o_qspi_dat;
        input           [3:0]    i_qspi_dat;
        input           [3:0]    i_qspi_dat;
        output  wire    [1:0]    o_qspi_mod;
        output  wire    [1:0]    o_qspi_mod;
        // Board I/O
        // Board I/O
        input           [1:0]    i_btn;
        input           [1:0]    i_btn;
Line 171... Line 177...
 
 
        // Signals to build/detect bus errors
        // Signals to build/detect bus errors
        wire    none_sel, many_sel;
        wire    none_sel, many_sel;
 
 
        wire    io_sel, flash_sel, flctl_sel, scop_sel, mem_sel;
        wire    io_sel, flash_sel, flctl_sel, scop_sel, mem_sel;
        wire    flash_ack, scop_ack, cfg_ack, mem_ack, many_ack;
        wire    flash_ack, scop_ack, mem_ack, many_ack;
        wire    io_stall, flash_stall, scop_stall, cfg_stall, mem_stall;
        wire    io_stall, flash_stall, scop_stall, mem_stall;
        reg     io_ack;
        reg     io_ack;
 
 
        wire    [31:0]   flash_data, scop_data, cfg_data, mem_data, pwm_data,
        wire    [31:0]   flash_data, scop_data, mem_data, pwm_data,
                        spio_data, gpio_data, uart_data;
                        spio_data, gpio_data, uart_data;
        reg     [31:0]   io_data;
        reg     [31:0]   io_data;
        reg     [(BAW-1):0]      bus_err_addr;
        reg     [(BAW-1):0]      bus_err_addr;
        //
        //
        // wb_ack
        // wb_ack
Line 307... Line 313...
`ifdef  ZERO_ON_IDLE
`ifdef  ZERO_ON_IDLE
        assign  idle_n = (wb_cyc)&&(wb_stb);
        assign  idle_n = (wb_cyc)&&(wb_stb);
`else
`else
        assign  idle_n = 1'b1;
        assign  idle_n = 1'b1;
`endif
`endif
        assign  io_sel   =((idle_n)&&(skipaddr[3:0]==4'h1));
        assign  io_sel   = ((idle_n)&&(skipaddr[3:0]==4'b00_01));
        assign  scop_sel =((idle_n)&&(skipaddr[3:1]==3'h1)); // = 4'h2
`ifdef  LOWLOGIC_FLASH
        assign  flctl_sel= 1'b0; // ((wb_cyc)&&(skipaddr[3:0]==4'h3));
        assign  scop_sel = ((idle_n)&&(skipaddr[3:1]==3'b00_1)); // = 4'h2
        assign  mem_sel  =((idle_n)&&(skipaddr[3:2]==2'h1));
        assign  flctl_sel= 1'b0; // The lowlogic flash has no control registers
 
`else   // LOWLOGIC_FLASH
 
        assign  scop_sel = ((idle_n)&&(skipaddr[3:0]==4'b00_10)); // = 4'h2
 
        assign  flctl_sel= ((wb_cyc)&&(skipaddr[3:0]==4'b00_11));
 
`endif  // LOWLOGIC_FLASH
 
        assign  mem_sel  = ((idle_n)&&(skipaddr[3:2]==2'b01));
        assign  flash_sel=((idle_n)&&(skipaddr[3]));
        assign  flash_sel=((idle_n)&&(skipaddr[3]));
 
 
        //
        //
        // none_sel
        // none_sel
        //
        //
Line 503... Line 514...
 
 
        //
        //
        //      FLASH MEMORY CONFIGURATION ACCESS
        //      FLASH MEMORY CONFIGURATION ACCESS
        //
        //
`ifdef  FLASH_ACCESS
`ifdef  FLASH_ACCESS
        wbqspiflash #(LGFLASHSZ)        flashmem(i_clk,
`ifdef  LOWLOGIC_FLASH
 
        wire    w_flash_ack;
 
        qflashxpress    flashmem(i_clk,
 
                wb_cyc,(wb_stb)&&(flash_sel),
 
                        wb_addr[(LGFLASHSZ-3):0],
 
                w_flash_ack, flash_stall, flash_data,
 
                o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat);
 
 
 
        assign  flash_interrupt = 1'b0;
 
        reg     r_flash_ack;
 
        initial r_flash_ack = 1'b0;
 
        always @(posedge i_clk)
 
                r_flash_ack <= (wb_stb)&&(flctl_sel);
 
        assign  flash_ack = (w_flash_ack)||(r_flash_ack);
 
`else   // LOWLOGIC_FLASH
 
        wbqspiflashp #(LGFLASHSZ)       // Use the writable interface
 
                flashmem(i_clk,
                wb_cyc,(wb_stb)&&(flash_sel),(wb_stb)&&(flctl_sel),wb_we,
                wb_cyc,(wb_stb)&&(flash_sel),(wb_stb)&&(flctl_sel),wb_we,
                        wb_addr[(LGFLASHSZ-3):0], wb_data,
                        wb_addr[(LGFLASHSZ-3):0], wb_data,
                flash_ack, flash_stall, flash_data,
                flash_ack, flash_stall, flash_data,
                o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
                o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
                flash_interrupt);
                flash_interrupt);
`else
`endif  // LOWLOGIC_FLASH
 
`else   // FLASH_ACCESS
        reg     r_flash_ack;
        reg     r_flash_ack;
        initial r_flash_ack = 1'b0;
        initial r_flash_ack = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                r_flash_ack <= (wb_stb)&&((flash_sel)||(flctl_sel));
                r_flash_ack <= (wb_stb)&&((flash_sel)||(flctl_sel));
 
 
Line 524... Line 552...
 
 
        assign  o_qspi_sck   = 1'b1;
        assign  o_qspi_sck   = 1'b1;
        assign  o_qspi_cs_n  = 1'b1;
        assign  o_qspi_cs_n  = 1'b1;
        assign  o_qspi_mod   = 2'b01;
        assign  o_qspi_mod   = 2'b01;
        assign  o_qspi_dat   = 4'b1111;
        assign  o_qspi_dat   = 4'b1111;
`endif
`endif  // FLASH_ACCESS
 
 
        //
        //
        //      ON-CHIP RAM MEMORY ACCESS
        //      ON-CHIP RAM MEMORY ACCESS
        //
        //
`ifdef  IMPLEMENT_ONCHIP_RAM
`ifdef  IMPLEMENT_ONCHIP_RAM
Line 550... Line 578...
        //      WISHBONE SCOPE
        //      WISHBONE SCOPE
        //
        //
        //
        //
        //
        //
        //
        //
        wire    [31:0]   scop_cfg_data;
 
        wire            scop_cfg_ack, scop_cfg_stall, scop_cfg_interrupt;
 
`ifdef  DBG_SCOPE
`ifdef  DBG_SCOPE
        wire            scop_cfg_trigger;
        wire    scop_trigger;
        assign  scop_cfg_trigger = (wb_stb)&&(cfg_sel);
        // assign scop_trigger = (flash_sel)&&(wb_stb); // bus_dbg;
        wire    scop_trigger = bus_dbg;
        assign scop_trigger = (wb_stb)&&(wb_we)&&(flctl_sel);
 
        wire    [31:0]   flash_debug;
 
        wire    [1:0]    sck;
 
`ifdef  LOWLOGIC_FLASH
 
        assign  sck = o_qspi_sck;
 
`else   // LOWLOGIC_FLASH
 
        assign  sck = { o_qspi_sck, o_qspi_sck };
 
`endif  // LOWLOGIC_FLASH
 
        assign  flash_debug = {
 
                        wb_cyc, wb_stb,
 
                                flash_sel, flctl_sel, flash_ack, flash_stall,
 
                                o_qspi_cs_n, sck, o_qspi_mod, 1'b0,
 
                        o_qspi_dat, i_qspi_dat, flash_data[11:0]
 
                };
`ifdef  COMPRESSED_SCOPE
`ifdef  COMPRESSED_SCOPE
        wbscopc #(5'ha)
        wbscopc #(5'ha)
`else
`else
        wbscope #(5'ha)
        wbscope #(5'ha)
`endif
`endif
        wbcfgscope(i_clk, 1'b1, scop_trigger, bus_debug,
        thescope(i_clk, 1'b1, scop_trigger, flash_debug,
                // Wishbone interface
                // Wishbone interface
                i_clk, wb_cyc, (wb_stb)&&(scop_sel),
                i_clk, wb_cyc, (wb_stb)&&(scop_sel),
                                wb_we, wb_addr[0], wb_data,
                                wb_we, wb_addr[0], wb_data,
                        scop_cfg_ack, scop_cfg_stall, scop_cfg_data,
                        scop_ack, scop_stall, scop_data,
                scop_cfg_interrupt);
                scop_interrupt);
`else
`else
        reg     r_scop_cfg_ack;
        reg     r_scop_ack;
        always @(posedge i_clk)
        always @(posedge i_clk)
                r_scop_cfg_ack <= (wb_stb)&&(scop_sel);
                r_scop_ack <= (wb_stb)&&(scop_sel);
        assign  scop_cfg_ack = r_scop_cfg_ack;
        assign  scop_ack = r_scop_ack;
        assign  scop_cfg_data = 32'h000;
        assign  scop_data = 32'h000;
        assign  scop_cfg_stall= 1'b0;
        assign  scop_stall= 1'b0;
`endif
`endif
 
 
        assign  scop_interrupt = scop_cfg_interrupt;
 
        assign  scop_ack   = scop_cfg_ack;
 
        assign  scop_stall = scop_cfg_stall;
 
        assign  scop_data  = scop_cfg_data;
 
 
 
endmodule
endmodule
 
 
 
 
 No newline at end of file
 No newline at end of file

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.