| Line 41... |
Line 41... |
//
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//
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`include "builddate.v"
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`include "builddate.v"
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//
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//
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// `define IMPLEMENT_ONCHIP_RAM
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// `define IMPLEMENT_ONCHIP_RAM
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`define FLASH_ACCESS
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`define FLASH_ACCESS
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// `define DBG_SCOPE // About 204 LUTs, at 2^6 addresses
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`define DBG_SCOPE // About 204 LUTs, at 2^6 addresses
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// `define COMPRESSED_SCOPE
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// `define COMPRESSED_SCOPE
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`define WBUBUS
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`define WBUBUS
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// `define LOWLOGIC_FLASH
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module altbusmaster(i_clk, i_rst,
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module altbusmaster(i_clk, i_rst,
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// DEPP I/O Control
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// DEPP I/O Control
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i_depp_astb_n, i_depp_dstb_n, i_depp_write_n,
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i_depp_astb_n, i_depp_dstb_n, i_depp_write_n,
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i_depp_data, o_depp_data, o_depp_wait,
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i_depp_data, o_depp_data, o_depp_wait,
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// External UART interface
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// External UART interface
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i_kp_row, o_kp_col,
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i_kp_row, o_kp_col,
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// UART control
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// UART control
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o_uart_setup,
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o_uart_setup,
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// GPIO lines
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// GPIO lines
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i_gpio, o_gpio);
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i_gpio, o_gpio);
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parameter BUS_ADDRESS_WIDTH=23,
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parameter BUS_ADDRESS_WIDTH=23;
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BAW=BUS_ADDRESS_WIDTH; // 24bits->2,258,23b->2181
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localparam BAW=BUS_ADDRESS_WIDTH; // 24bits->2,258,23b->2181
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// 2^14 bytes requires a LGMEMSZ of 14, and 12 address bits ranging from
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// 2^14 bytes requires a LGMEMSZ of 14, and 12 address bits ranging from
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// 0 to 11. As with many other devices, the wb_cyc line is more for
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// 0 to 11. As with many other devices, the wb_cyc line is more for
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// form than anything else--it is ignored by the memory itself.
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// form than anything else--it is ignored by the memory itself.
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localparam LGMEMSZ=14; // Takes 8 BLKRAM16 elements for LGMEMSZ=14
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localparam LGMEMSZ=14; // Takes 8 BLKRAM16 elements for LGMEMSZ=14
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// As with the memory size, the flash size is also measured in log_2 of
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// As with the memory size, the flash size is also measured in log_2 of
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| Line 84... |
Line 85... |
output reg o_tx_stb;
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output reg o_tx_stb;
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output reg [7:0] o_tx_data;
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output reg [7:0] o_tx_data;
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input i_tx_busy;
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input i_tx_busy;
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output wire o_uart_rts_n;
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output wire o_uart_rts_n;
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// SPI flash control
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// SPI flash control
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output wire o_qspi_cs_n, o_qspi_sck;
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output wire o_qspi_cs_n;
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`ifdef LOWLOGIC_FLASH
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output wire [1:0] o_qspi_sck;
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`else // LOWLOGIC_FLASH
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output wire o_qspi_sck;
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`endif // LOWLOGIC_FLASH
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output wire [3:0] o_qspi_dat;
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output wire [3:0] o_qspi_dat;
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input [3:0] i_qspi_dat;
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input [3:0] i_qspi_dat;
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output wire [1:0] o_qspi_mod;
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output wire [1:0] o_qspi_mod;
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// Board I/O
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// Board I/O
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input [1:0] i_btn;
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input [1:0] i_btn;
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Line 177... |
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// Signals to build/detect bus errors
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// Signals to build/detect bus errors
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wire none_sel, many_sel;
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wire none_sel, many_sel;
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wire io_sel, flash_sel, flctl_sel, scop_sel, mem_sel;
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wire io_sel, flash_sel, flctl_sel, scop_sel, mem_sel;
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wire flash_ack, scop_ack, cfg_ack, mem_ack, many_ack;
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wire flash_ack, scop_ack, mem_ack, many_ack;
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wire io_stall, flash_stall, scop_stall, cfg_stall, mem_stall;
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wire io_stall, flash_stall, scop_stall, mem_stall;
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reg io_ack;
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reg io_ack;
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wire [31:0] flash_data, scop_data, cfg_data, mem_data, pwm_data,
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wire [31:0] flash_data, scop_data, mem_data, pwm_data,
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spio_data, gpio_data, uart_data;
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spio_data, gpio_data, uart_data;
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reg [31:0] io_data;
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reg [31:0] io_data;
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reg [(BAW-1):0] bus_err_addr;
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reg [(BAW-1):0] bus_err_addr;
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//
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//
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// wb_ack
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// wb_ack
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Line 313... |
`ifdef ZERO_ON_IDLE
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`ifdef ZERO_ON_IDLE
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assign idle_n = (wb_cyc)&&(wb_stb);
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assign idle_n = (wb_cyc)&&(wb_stb);
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`else
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`else
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assign idle_n = 1'b1;
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assign idle_n = 1'b1;
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`endif
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`endif
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assign io_sel =((idle_n)&&(skipaddr[3:0]==4'h1));
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assign io_sel = ((idle_n)&&(skipaddr[3:0]==4'b00_01));
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assign scop_sel =((idle_n)&&(skipaddr[3:1]==3'h1)); // = 4'h2
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`ifdef LOWLOGIC_FLASH
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assign flctl_sel= 1'b0; // ((wb_cyc)&&(skipaddr[3:0]==4'h3));
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assign scop_sel = ((idle_n)&&(skipaddr[3:1]==3'b00_1)); // = 4'h2
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assign mem_sel =((idle_n)&&(skipaddr[3:2]==2'h1));
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assign flctl_sel= 1'b0; // The lowlogic flash has no control registers
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`else // LOWLOGIC_FLASH
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assign scop_sel = ((idle_n)&&(skipaddr[3:0]==4'b00_10)); // = 4'h2
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assign flctl_sel= ((wb_cyc)&&(skipaddr[3:0]==4'b00_11));
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`endif // LOWLOGIC_FLASH
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assign mem_sel = ((idle_n)&&(skipaddr[3:2]==2'b01));
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assign flash_sel=((idle_n)&&(skipaddr[3]));
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assign flash_sel=((idle_n)&&(skipaddr[3]));
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//
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//
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// none_sel
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// none_sel
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//
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//
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Line 514... |
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//
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//
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// FLASH MEMORY CONFIGURATION ACCESS
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// FLASH MEMORY CONFIGURATION ACCESS
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//
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//
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`ifdef FLASH_ACCESS
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`ifdef FLASH_ACCESS
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wbqspiflash #(LGFLASHSZ) flashmem(i_clk,
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`ifdef LOWLOGIC_FLASH
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wire w_flash_ack;
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qflashxpress flashmem(i_clk,
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wb_cyc,(wb_stb)&&(flash_sel),
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wb_addr[(LGFLASHSZ-3):0],
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w_flash_ack, flash_stall, flash_data,
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o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat);
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assign flash_interrupt = 1'b0;
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reg r_flash_ack;
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initial r_flash_ack = 1'b0;
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always @(posedge i_clk)
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r_flash_ack <= (wb_stb)&&(flctl_sel);
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assign flash_ack = (w_flash_ack)||(r_flash_ack);
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`else // LOWLOGIC_FLASH
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wbqspiflashp #(LGFLASHSZ) // Use the writable interface
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flashmem(i_clk,
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wb_cyc,(wb_stb)&&(flash_sel),(wb_stb)&&(flctl_sel),wb_we,
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wb_cyc,(wb_stb)&&(flash_sel),(wb_stb)&&(flctl_sel),wb_we,
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wb_addr[(LGFLASHSZ-3):0], wb_data,
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wb_addr[(LGFLASHSZ-3):0], wb_data,
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flash_ack, flash_stall, flash_data,
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flash_ack, flash_stall, flash_data,
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o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
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o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
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flash_interrupt);
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flash_interrupt);
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`else
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`endif // LOWLOGIC_FLASH
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`else // FLASH_ACCESS
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reg r_flash_ack;
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reg r_flash_ack;
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initial r_flash_ack = 1'b0;
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initial r_flash_ack = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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r_flash_ack <= (wb_stb)&&((flash_sel)||(flctl_sel));
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r_flash_ack <= (wb_stb)&&((flash_sel)||(flctl_sel));
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Line 552... |
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assign o_qspi_sck = 1'b1;
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assign o_qspi_sck = 1'b1;
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assign o_qspi_cs_n = 1'b1;
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assign o_qspi_cs_n = 1'b1;
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assign o_qspi_mod = 2'b01;
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assign o_qspi_mod = 2'b01;
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assign o_qspi_dat = 4'b1111;
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assign o_qspi_dat = 4'b1111;
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`endif
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`endif // FLASH_ACCESS
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//
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//
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// ON-CHIP RAM MEMORY ACCESS
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// ON-CHIP RAM MEMORY ACCESS
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//
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//
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`ifdef IMPLEMENT_ONCHIP_RAM
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`ifdef IMPLEMENT_ONCHIP_RAM
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Line 578... |
// WISHBONE SCOPE
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// WISHBONE SCOPE
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//
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//
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//
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//
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//
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//
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//
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//
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wire [31:0] scop_cfg_data;
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wire scop_cfg_ack, scop_cfg_stall, scop_cfg_interrupt;
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`ifdef DBG_SCOPE
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`ifdef DBG_SCOPE
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wire scop_cfg_trigger;
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wire scop_trigger;
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assign scop_cfg_trigger = (wb_stb)&&(cfg_sel);
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// assign scop_trigger = (flash_sel)&&(wb_stb); // bus_dbg;
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wire scop_trigger = bus_dbg;
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assign scop_trigger = (wb_stb)&&(wb_we)&&(flctl_sel);
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wire [31:0] flash_debug;
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wire [1:0] sck;
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`ifdef LOWLOGIC_FLASH
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assign sck = o_qspi_sck;
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`else // LOWLOGIC_FLASH
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assign sck = { o_qspi_sck, o_qspi_sck };
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`endif // LOWLOGIC_FLASH
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assign flash_debug = {
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wb_cyc, wb_stb,
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flash_sel, flctl_sel, flash_ack, flash_stall,
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o_qspi_cs_n, sck, o_qspi_mod, 1'b0,
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o_qspi_dat, i_qspi_dat, flash_data[11:0]
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};
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`ifdef COMPRESSED_SCOPE
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`ifdef COMPRESSED_SCOPE
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wbscopc #(5'ha)
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wbscopc #(5'ha)
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`else
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`else
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wbscope #(5'ha)
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wbscope #(5'ha)
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`endif
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`endif
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wbcfgscope(i_clk, 1'b1, scop_trigger, bus_debug,
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thescope(i_clk, 1'b1, scop_trigger, flash_debug,
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// Wishbone interface
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// Wishbone interface
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i_clk, wb_cyc, (wb_stb)&&(scop_sel),
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i_clk, wb_cyc, (wb_stb)&&(scop_sel),
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wb_we, wb_addr[0], wb_data,
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wb_we, wb_addr[0], wb_data,
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scop_cfg_ack, scop_cfg_stall, scop_cfg_data,
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scop_ack, scop_stall, scop_data,
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scop_cfg_interrupt);
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scop_interrupt);
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`else
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`else
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reg r_scop_cfg_ack;
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reg r_scop_ack;
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always @(posedge i_clk)
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always @(posedge i_clk)
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r_scop_cfg_ack <= (wb_stb)&&(scop_sel);
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r_scop_ack <= (wb_stb)&&(scop_sel);
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assign scop_cfg_ack = r_scop_cfg_ack;
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assign scop_ack = r_scop_ack;
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assign scop_cfg_data = 32'h000;
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assign scop_data = 32'h000;
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assign scop_cfg_stall= 1'b0;
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assign scop_stall= 1'b0;
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`endif
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`endif
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assign scop_interrupt = scop_cfg_interrupt;
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assign scop_ack = scop_cfg_ack;
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assign scop_stall = scop_cfg_stall;
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assign scop_data = scop_cfg_data;
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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