| Line 41... |
Line 41... |
//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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// `define LOWLOGIC_FLASH
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module alttop(i_clk_8mhz,
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module alttop(i_clk_8mhz,
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o_qspi_cs_n, o_qspi_sck, io_qspi_dat,
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o_qspi_cs_n, o_qspi_sck, io_qspi_dat,
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i_btn, o_led, o_pwm, o_pwm_shutdown_n, o_pwm_gain,
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i_btn, o_led, o_pwm, o_pwm_shutdown_n, o_pwm_gain,
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i_uart, o_uart, o_uart_rts_n, i_uart_cts_n,
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i_uart, o_uart, o_uart_rts_n, i_uart_cts_n,
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i_kp_row, o_kp_col,
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i_kp_row, o_kp_col,
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| Line 87... |
Line 88... |
//
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//
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// Clock management
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// Clock management
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//
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//
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// Generate a usable clock for the rest of the board to run at.
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// Generate a usable clock for the rest of the board to run at.
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//
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//
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wire ck_zero_0, clk_s;
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wire ck_zero_0, clk_s, clk_sn;
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// Clock frequency = (20 / 2) * 8Mhz = 80 MHz
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// Clock frequency = (20 / 2) * 8Mhz = 80 MHz
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// Clock period = 12.5 ns
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// Clock period = 12.5 ns
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DCM_SP #(
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DCM_SP #(
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.CLKDV_DIVIDE(2.0),
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.CLKDV_DIVIDE(2.0),
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| Line 108... |
Line 109... |
.STARTUP_WAIT("TRUE")
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.STARTUP_WAIT("TRUE")
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) u0( .CLKIN(i_clk_8mhz),
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) u0( .CLKIN(i_clk_8mhz),
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.CLK0(ck_zero_0),
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.CLK0(ck_zero_0),
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.CLKFB(ck_zero_0),
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.CLKFB(ck_zero_0),
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.CLKFX(clk_s),
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.CLKFX(clk_s),
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.CLKFX180(clk_sn),
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.PSEN(1'b0),
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.PSEN(1'b0),
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.RST(1'b0));
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.RST(1'b0));
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//
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//
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// The UART serial interface
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// The UART serial interface
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| Line 157... |
Line 159... |
// to be changed: either to add more devices, or to remove them.
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// to be changed: either to add more devices, or to remove them.
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//
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//
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// This is an alternate version of the busmaster interface,
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// This is an alternate version of the busmaster interface,
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// offering no ZipCPU and access to reprogramming via the flash.
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// offering no ZipCPU and access to reprogramming via the flash.
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//
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//
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`ifdef LOWLOGIC_FLASH
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wire [1:0] qspi_sck;
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`else
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wire qspi_sck;
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`endif
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wire qspi_cs_n;
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wire [3:0] qspi_dat;
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wire [3:0] qspi_dat;
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wire [1:0] qspi_bmod;
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wire [1:0] qspi_bmod;
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wire [15:0] w_gpio;
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wire [15:0] w_gpio;
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wire [7:0] w_depp_data;
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wire [7:0] w_depp_data;
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Line 180... |
i_depp_astb_n, i_depp_dstb_n, i_depp_write_n,
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i_depp_astb_n, i_depp_dstb_n, i_depp_write_n,
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io_depp_data, w_depp_data, o_depp_wait,
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io_depp_data, w_depp_data, o_depp_wait,
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// External UART interface
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// External UART interface
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rx_stb, rx_data, tx_stb, tx_data, tx_busy, w_uart_rts_n,
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rx_stb, rx_data, tx_stb, tx_data, tx_busy, w_uart_rts_n,
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// SPI/SD-card flash
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// SPI/SD-card flash
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o_qspi_cs_n, o_qspi_sck, qspi_dat, io_qspi_dat, qspi_bmod,
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qspi_cs_n, qspi_sck, qspi_dat, io_qspi_dat, qspi_bmod,
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// Board lights and switches
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// Board lights and switches
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i_btn, o_led, o_pwm, { o_pwm_shutdown_n, o_pwm_gain },
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i_btn, o_led, o_pwm, { o_pwm_shutdown_n, o_pwm_gain },
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// Keypad connections
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// Keypad connections
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i_kp_row, o_kp_col,
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i_kp_row, o_kp_col,
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// UART control
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// UART control
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Line 201... |
// wires are going at each instant, whether the device is in full
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// wires are going at each instant, whether the device is in full
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// Quad mode in, full quad mode out, or simply the normal SPI
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// Quad mode in, full quad mode out, or simply the normal SPI
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// port with one wire in and one wire out. This utilizes our
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// port with one wire in and one wire out. This utilizes our
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// control wires (qspi_bmod) to set the output lines appropriately.
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// control wires (qspi_bmod) to set the output lines appropriately.
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//
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//
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assign io_qspi_dat = (~qspi_bmod[1])?({2'b11,1'bz,qspi_dat[0]})
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//
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// 2'b0? -- Normal SPI
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// 2'b10 -- Quad Output
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// 2'b11 -- Quad Input
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`ifdef LOWLOGIC_FLASH
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reg r_qspi_cs_n;
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reg [1:0] r_qspi_bmod;
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reg [3:0] r_qspi_dat, r_qspi_z;
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reg [1:0] r_qspi_sck;
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always @(posedge clk_s)
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r_qspi_sck <= qspi_sck;
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xoddr xqspi_sck({clk_s, clk_sn}, r_qspi_sck, o_qspi_sck);
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initial r_qspi_cs_n = 1'b1;
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initial r_qspi_z = 4'b1101;
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always @(posedge clk_s)
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begin
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r_qspi_dat <= (qspi_bmod[1]) ? qspi_dat:{ 3'b111, qspi_dat[0]};
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r_qspi_z <= (!qspi_bmod[1])? 4'b1101
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: ((qspi_bmod[0]) ? 4'h0 : 4'hf);
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r_qspi_cs_n <= qspi_cs_n;
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end
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assign o_qspi_cs_n = r_qspi_cs_n;
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assign io_qspi_dat[0] = (r_qspi_z[0]) ? r_qspi_dat[0] : 1'bz;
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assign io_qspi_dat[1] = (r_qspi_z[1]) ? r_qspi_dat[1] : 1'bz;
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assign io_qspi_dat[2] = (r_qspi_z[2]) ? r_qspi_dat[2] : 1'bz;
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assign io_qspi_dat[3] = (r_qspi_z[3]) ? r_qspi_dat[3] : 1'bz;
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`else
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assign io_qspi_dat = (!qspi_bmod[1])?({2'b11,1'bz,qspi_dat[0]})
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:((qspi_bmod[0])?(4'bzzzz):(qspi_dat[3:0]));
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:((qspi_bmod[0])?(4'bzzzz):(qspi_dat[3:0]));
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`else
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assign o_qspi_cs_n = qspi_cs_n;
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assign o_qspi_sck = qspi_sck;
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`endif // LOWLOGIC_FLASH
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`else // BYPASS_LOGIC
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reg [26:0] r_counter;
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reg [26:0] r_counter;
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always @(posedge clk_s)
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always @(posedge clk_s)
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r_counter <= r_counter+1;
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r_counter <= r_counter+1;
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assign o_led[0] = r_counter[26];
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assign o_led[0] = r_counter[26];
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assign o_led[1] = r_counter[25];
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assign o_led[1] = r_counter[25];
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| Line 223... |
Line 263... |
assign o_qspi_sck = 1'b1;
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assign o_qspi_sck = 1'b1;
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assign uart_setup = 30'h080002b6;
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assign uart_setup = 30'h080002b6;
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assign o_uart_rts_n = 1'b0;
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assign o_uart_rts_n = 1'b0;
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`endif
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`endif // BYPASS_LOGIC
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//
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//
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// I2C support
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// I2C support
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//
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//
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// Supporting I2C requires a couple quick adjustments to our
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// Supporting I2C requires a couple quick adjustments to our
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// GPIO lines. Specifically, we'll allow that when the output
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// GPIO lines. Specifically, we'll allow that when the output
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