| Line 302... |
Line 302... |
// PIPELINE STAGE #4 :: ALU / Memory
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// PIPELINE STAGE #4 :: ALU / Memory
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// Variable declarations
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// Variable declarations
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//
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//
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//
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//
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reg [(AW-1):0] alu_pc;
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reg [(AW-1):0] alu_pc;
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reg alu_pc_valid, mem_pc_valid;
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reg r_alu_pc_valid, mem_pc_valid;
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wire alu_pc_valid;
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wire alu_phase;
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wire alu_phase;
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wire alu_ce, alu_stall;
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wire alu_ce, alu_stall;
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wire [31:0] alu_result;
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wire [31:0] alu_result;
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wire [3:0] alu_flags;
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wire [3:0] alu_flags;
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wire alu_valid, alu_busy;
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wire alu_valid, alu_busy;
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| Line 373... |
Line 374... |
//
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//
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|
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//
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//
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// PIPELINE STAGE #2 :: Instruction Decode
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// PIPELINE STAGE #2 :: Instruction Decode
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// Calculate stall conditions
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// Calculate stall conditions
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`ifdef OPT_PIPELINED
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assign dcd_ce = ((~dcdvalid)||(~dcd_stalled))&&(~clear_pipeline);
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assign dcd_ce = ((~dcdvalid)||(~dcd_stalled))&&(~clear_pipeline);
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`else
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assign dcd_ce = 1'b1;
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`endif
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`ifdef OPT_PIPELINED
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`ifdef OPT_PIPELINED
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assign dcd_stalled = (dcdvalid)&&(op_stall);
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assign dcd_stalled = (dcdvalid)&&(op_stall);
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`else
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`else
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// If not pipelined, there will be no opvalid_ anything, and the
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// If not pipelined, there will be no opvalid_ anything, and the
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// op_stall will be false, dcdX_stall will be false, thus we can simply
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// op_stall will be false, dcdX_stall will be false, thus we can simply
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| Line 426... |
Line 424... |
||(dcdF_stall)
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||(dcdF_stall)
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);
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);
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assign op_ce = ((dcdvalid)||(dcd_illegal))&&(~op_stall)&&(~clear_pipeline);
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assign op_ce = ((dcdvalid)||(dcd_illegal))&&(~op_stall)&&(~clear_pipeline);
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`else
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`else
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assign op_stall = (opvalid)&&(~master_ce);
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assign op_stall = (opvalid)&&(~master_ce);
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assign op_ce = ((dcdvalid)||(dcd_illegal));
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assign op_ce = ((dcdvalid)||(dcd_illegal))&&(~clear_pipeline);
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`endif
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`endif
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//
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//
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// PIPELINE STAGE #4 :: ALU / Memory
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// PIPELINE STAGE #4 :: ALU / Memory
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// Calculate stall conditions
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// Calculate stall conditions
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| Line 456... |
Line 454... |
&&(~alu_stall)
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&&(~alu_stall)
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&&(~clear_pipeline);
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&&(~clear_pipeline);
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`else
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`else
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assign alu_stall = ((~master_ce)&&(opvalid_alu))
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assign alu_stall = ((~master_ce)&&(opvalid_alu))
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||((opvalid_alu)&&(op_break));
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||((opvalid_alu)&&(op_break));
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assign alu_ce = (master_ce)&&((opvalid_alu)||(op_illegal))&&(~alu_stall);
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assign alu_ce = (master_ce)&&((opvalid_alu)||(op_illegal))&&(~alu_stall)&&(~clear_pipeline);
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`endif
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`endif
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//
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//
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//
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//
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// Note: if you change the conditions for mem_ce, you must also change
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// Note: if you change the conditions for mem_ce, you must also change
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| Line 471... |
Line 469... |
&&(~clear_pipeline);
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&&(~clear_pipeline);
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`else
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`else
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// If we aren't pipelined, then no one will be changing what's in the
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// If we aren't pipelined, then no one will be changing what's in the
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// pipeline (i.e. clear_pipeline), while our only instruction goes
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// pipeline (i.e. clear_pipeline), while our only instruction goes
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// through the ... pipeline.
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// through the ... pipeline.
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assign mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled);
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assign mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled)&&(~clear_pipeline);
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`endif
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`endif
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`ifdef OPT_PIPELINED_BUS_ACCESS
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`ifdef OPT_PIPELINED_BUS_ACCESS
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assign mem_stalled = (~master_ce)||(alu_busy)||((opvalid_mem)&&(
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assign mem_stalled = (~master_ce)||(alu_busy)||((opvalid_mem)&&(
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(mem_pipe_stalled)
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(mem_pipe_stalled)
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||((~op_pipe)&&(mem_busy))
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||((~op_pipe)&&(mem_busy))
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| Line 510... |
Line 508... |
`ifdef OPT_SINGLE_FETCH
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`ifdef OPT_SINGLE_FETCH
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wire pf_ce;
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wire pf_ce;
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assign pf_ce = (~pf_valid)&&(~dcdvalid)&&(~opvalid)&&(~alu_valid);
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assign pf_ce = (~pf_valid)&&(~dcdvalid)&&(~opvalid)&&(~alu_valid);
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prefetch #(ADDRESS_WIDTH)
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prefetch #(ADDRESS_WIDTH)
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pf(i_clk, i_rst, (pf_ce), (~dcd_stalled), pf_pc, gie,
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pf(i_clk, (i_rst), (pf_ce), (~dcd_stalled), pf_pc, gie,
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instruction, instruction_pc, instruction_gie,
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instruction, instruction_pc, instruction_gie,
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pf_valid, pf_illegal,
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pf_valid, pf_illegal,
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pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
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pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
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pf_ack, pf_stall, pf_err, i_wb_data);
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pf_ack, pf_stall, pf_err, i_wb_data);
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initial r_dcdvalid = 1'b0;
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initial r_dcdvalid = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if ((i_rst)||(clear_pipeline))
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r_dcdvalid <= 1'b0;
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r_dcdvalid <= 1'b0;
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else if (dcd_ce)
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else if (dcd_ce)
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r_dcdvalid <= (pf_valid);
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r_dcdvalid <= (pf_valid);
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else if (op_ce)
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else if (op_ce)
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r_dcdvalid <= 1'b0;
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r_dcdvalid <= 1'b0;
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| Line 563... |
Line 561... |
initial r_dcdvalid = 1'b0;
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initial r_dcdvalid = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((i_rst)||(clear_pipeline))
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if ((i_rst)||(clear_pipeline))
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r_dcdvalid <= 1'b0;
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r_dcdvalid <= 1'b0;
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else if (dcd_ce)
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else if (dcd_ce)
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r_dcdvalid <= (pf_valid)&&(~clear_pipeline)&&(~dcd_ljmp)&&((~r_dcdvalid)||(~dcd_early_branch));
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r_dcdvalid <= (pf_valid)&&(~dcd_ljmp)&&((~r_dcdvalid)||(~dcd_early_branch));
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else if (op_ce)
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else if (op_ce)
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r_dcdvalid <= 1'b0;
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r_dcdvalid <= 1'b0;
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assign dcdvalid = r_dcdvalid;
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assign dcdvalid = r_dcdvalid;
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`endif
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`endif
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| Line 1158... |
Line 1156... |
else if ((alu_ce)||(mem_ce))
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else if ((alu_ce)||(mem_ce))
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r_alu_illegal <= op_illegal;
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r_alu_illegal <= op_illegal;
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assign alu_illegal = (alu_illegal_op)||(r_alu_illegal);
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assign alu_illegal = (alu_illegal_op)||(r_alu_illegal);
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`endif
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`endif
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initial alu_pc_valid = 1'b0;
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initial r_alu_pc_valid = 1'b0;
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initial mem_pc_valid = 1'b0;
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initial mem_pc_valid = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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alu_pc_valid <= 1'b0;
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r_alu_pc_valid <= 1'b0;
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else
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else if (alu_ce) // Includes && (~alu_clear_pipeline)
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alu_pc_valid <= (alu_ce);
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r_alu_pc_valid <= 1'b1;
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else if ((~alu_busy)||(clear_pipeline))
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r_alu_pc_valid <= 1'b0;
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assign alu_pc_valid = (r_alu_pc_valid)&&(~alu_busy);
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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mem_pc_valid <= 1'b0;
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mem_pc_valid <= 1'b0;
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else
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else
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mem_pc_valid <= (mem_ce);
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mem_pc_valid <= (mem_ce);
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| Line 1636... |
Line 1637... |
else if ((dcd_early_branch)&&(~clear_pipeline))
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else if ((dcd_early_branch)&&(~clear_pipeline))
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pf_pc <= dcd_branch_pc + 1;
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pf_pc <= dcd_branch_pc + 1;
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else if ((new_pc)||((~dcd_stalled)&&(pf_valid)))
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else if ((new_pc)||((~dcd_stalled)&&(pf_valid)))
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pf_pc <= pf_pc + {{(AW-1){1'b0}},1'b1};
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pf_pc <= pf_pc + {{(AW-1){1'b0}},1'b1};
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`else
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`else
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else if (((alu_pc_valid)&&(~clear_pipeline))||(mem_pc_valid))
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else if ((alu_gie==gie)&&(
|
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((alu_pc_valid)&&(~clear_pipeline))
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||(mem_pc_valid)))
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pf_pc <= alu_pc;
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pf_pc <= alu_pc;
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`endif
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`endif
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initial new_pc = 1'b1;
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initial new_pc = 1'b1;
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always @(posedge i_clk)
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always @(posedge i_clk)
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| Line 1705... |
Line 1708... |
assign o_i_count = (alu_pc_valid)&&(~clear_pipeline);
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assign o_i_count = (alu_pc_valid)&&(~clear_pipeline);
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`ifdef DEBUG_SCOPE
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`ifdef DEBUG_SCOPE
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_debug <= {
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o_debug <= {
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o_break, i_wb_err, pf_pc[1:0],
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/*
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flags,
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o_break, i_wb_err, pf_pc[1:0],
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pf_valid, dcdvalid, opvalid, alu_valid, mem_valid,
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//
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op_ce, alu_ce, mem_ce,
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flags,
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//
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//
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master_ce, opvalid_alu, opvalid_mem,
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pf_valid, dcdvalid, opvalid, alu_valid,
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//
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//
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alu_stall, mem_busy, op_pipe, mem_pipe_stalled,
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mem_valid,
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mem_we,
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op_ce, alu_ce, mem_ce,
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// ((opvalid_alu)&&(alu_stall))
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//
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// ||((opvalid_mem)&&(~op_pipe)&&(mem_busy))
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master_ce,
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// ||((opvalid_mem)&&( op_pipe)&&(mem_pipe_stalled)));
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opvalid_alu, opvalid_mem, alu_stall,
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// opA[23:20], opA[3:0],
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//
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gie, sleep, wr_reg_ce, wr_reg_vl[4:0]
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mem_busy, op_pipe,
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`ifdef OPT_PIPELINED_BUS_ACCESS
|
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mem_pipe_stalled,
|
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`else
|
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1'b0,
|
|
`endif
|
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mem_we,
|
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//
|
|
// ((opvalid_alu)&&(alu_stall))
|
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// ||((opvalid_mem)&&(~op_pipe)&&(mem_busy))
|
|
// ||((opvalid_mem)&&( op_pipe)&&(mem_pipe_stalled)));
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// opA[23:20], opA[3:0],
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gie, sleep, wr_reg_ce, wr_reg_vl[4:0]
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*/
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|
|
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o_break, i_wb_err, o_wb_gbl_cyc, o_wb_gbl_stb,
|
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pf_valid, dcdvalid, opvalid, alu_valid,
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mem_valid, dcd_ce, op_ce, alu_ce,
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mem_ce,
|
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dcd_illegal, gie, sleep,
|
|
{ ((o_wb_gbl_cyc)&&(o_wb_gbl_stb)&&(o_wb_we))
|
|
? o_wb_data[15:0]
|
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: ((o_wb_gbl_cyc)&&(o_wb_gbl_stb)&&(~o_wb_we)&&(i_wb_ack))
|
|
? i_wb_data[15:0]
|
|
: o_wb_addr[15:0]
|
|
}
|
/*
|
/*
|
i_rst, master_ce, (new_pc),
|
i_rst, master_ce, (new_pc),
|
((dcd_early_branch)&&(dcdvalid)),
|
((dcd_early_branch)&&(dcdvalid)),
|
pf_valid, pf_illegal,
|
pf_valid, pf_illegal,
|
op_ce, dcd_ce, dcdvalid, dcd_stalled,
|
op_ce, dcd_ce, dcdvalid, dcd_stalled,
|
