| Line 506... |
Line 506... |
//
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//
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//
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//
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`ifdef OPT_SINGLE_FETCH
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`ifdef OPT_SINGLE_FETCH
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wire pf_ce;
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wire pf_ce;
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|
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assign pf_ce = (~pf_valid)&&(~dcdvalid)&&(~opvalid)&&(~alu_valid);
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assign pf_ce = (~pf_valid)&&(~dcdvalid)&&(~opvalid)&&(~alu_busy)&&(~mem_busy)&&(~alu_pc_valid)&&(~mem_pc_valid);
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prefetch #(ADDRESS_WIDTH)
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prefetch #(ADDRESS_WIDTH)
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pf(i_clk, (i_rst), (pf_ce), (~dcd_stalled), pf_pc, gie,
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pf(i_clk, (i_rst), (pf_ce), (~dcd_stalled), pf_pc, gie,
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instruction, instruction_pc, instruction_gie,
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instruction, instruction_pc, instruction_gie,
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pf_valid, pf_illegal,
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pf_valid, pf_illegal,
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pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
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pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
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| Line 1740... |
Line 1740... |
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o_break, i_wb_err, o_wb_gbl_cyc, o_wb_gbl_stb,
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o_break, i_wb_err, o_wb_gbl_cyc, o_wb_gbl_stb,
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pf_valid, dcdvalid, opvalid, alu_valid,
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pf_valid, dcdvalid, opvalid, alu_valid,
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mem_valid, dcd_ce, op_ce, alu_ce,
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mem_valid, dcd_ce, op_ce, alu_ce,
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mem_ce,
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mem_ce,
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dcd_illegal, gie, sleep,
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pf_ce, gie, sleep,
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{ ((o_wb_gbl_cyc)&&(o_wb_gbl_stb)&&(o_wb_we))
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{ ((o_wb_gbl_cyc)&&(o_wb_gbl_stb)&&(o_wb_we))
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? o_wb_data[15:0]
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? o_wb_data[15:0]
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: ((o_wb_gbl_cyc)&&(o_wb_gbl_stb)&&(~o_wb_we)&&(i_wb_ack))
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: ((o_wb_gbl_cyc)&&(~o_wb_we)&&(i_wb_ack))
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? i_wb_data[15:0]
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? i_wb_data[15:0]
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: o_wb_addr[15:0]
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: o_wb_addr[15:0]
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}
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}
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/*
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/*
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i_rst, master_ce, (new_pc),
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i_rst, master_ce, (new_pc),
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