| Line 1... |
Line 1... |
///////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: zipcpu.v
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// Filename: zipcpu.v
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//
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//
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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//
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// Purpose: This is the top level module holding the core of the Zip CPU
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// Purpose: This is the top level module holding the core of the Zip CPU
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// together. The Zip CPU is designed to be as simple as possible.
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// together. The Zip CPU is designed to be as simple as possible.
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// (actual implementation aside ...) The instruction set is about as
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// (actual implementation aside ...) The instruction set is about as
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// RISC as you can get, there are only 16 instruction types supported.
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// RISC as you can get, with only 26 instruction types currently supported.
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// (There are still 8-instruction Op-Codes reserved for floating point,
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// and 5 which can be used for transactions not requiring registers.)
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// Please see the accompanying spec.pdf file for a description of these
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// Please see the accompanying spec.pdf file for a description of these
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// instructions.
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// instructions.
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//
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//
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// All instructions are 32-bits wide. All bus accesses, both address and
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// All instructions are 32-bits wide. All bus accesses, both address and
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// data, are 32-bits over a wishbone bus.
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// data, are 32-bits over a wishbone bus.
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| Line 24... |
Line 26... |
//
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//
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// 4. Apply Instruction
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// 4. Apply Instruction
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//
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//
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// 4. Write-back Results
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// 4. Write-back Results
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//
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//
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// Further information about the inner workings of this CPU may be
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// Further information about the inner workings of this CPU, such as
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// found in the spec.pdf file. (The documentation within this file
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// what causes pipeline stalls, may be found in the spec.pdf file. (The
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// had become out of date and out of sync with the spec.pdf, so look
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// documentation within this file had become out of date and out of sync
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// to the spec.pdf for accurate and up to date information.)
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// with the spec.pdf, so look to the spec.pdf for accurate and up to date
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// information.)
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//
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//
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//
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//
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// In general, the pipelining is controlled by three pieces of logic
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// In general, the pipelining is controlled by three pieces of logic
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// per stage: _ce, _stall, and _valid. _valid means that the stage
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// per stage: _ce, _stall, and _valid. _valid means that the stage
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// holds a valid instruction. _ce means that the instruction from the
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// holds a valid instruction. _ce means that the instruction from the
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| Line 67... |
Line 70... |
//
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//
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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///////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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// Copyright (C) 2015-2017, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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| Line 81... |
Line 84... |
// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory. Run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
|
///////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
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//
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|
// We can either pipeline our fetches, or issue one fetch at a time. Pipelined
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// fetches are more complicated and therefore use more FPGA resources, while
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// single fetches will cause the CPU to stall for about 5 stalls each
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// instruction cycle, effectively reducing the instruction count per clock to
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// about 0.2. However, the area cost may be worth it. Consider:
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//
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|
// Slice LUTs ZipSystem ZipCPU
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// Single Fetching 2521 1734
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// Pipelined fetching 2796 2046
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|
//
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//
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//
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//
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//
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//
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`define CPU_CC_REG 4'he
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`define CPU_CC_REG 4'he
|
`define CPU_PC_REG 4'hf
|
`define CPU_PC_REG 4'hf
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|
`define CPU_CLRCACHE_BIT 14 // Set to clear the I-cache, automatically clears
|
|
`define CPU_PHASE_BIT 13 // Set if we are executing the latter half of a CIS
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`define CPU_FPUERR_BIT 12 // Floating point error flag, set on error
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`define CPU_FPUERR_BIT 12 // Floating point error flag, set on error
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`define CPU_DIVERR_BIT 11 // Divide error flag, set on divide by zero
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`define CPU_DIVERR_BIT 11 // Divide error flag, set on divide by zero
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`define CPU_BUSERR_BIT 10 // Bus error flag, set on error
|
`define CPU_BUSERR_BIT 10 // Bus error flag, set on error
|
`define CPU_TRAP_BIT 9 // User TRAP has taken place
|
`define CPU_TRAP_BIT 9 // User TRAP has taken place
|
`define CPU_ILL_BIT 8 // Illegal instruction
|
`define CPU_ILL_BIT 8 // Illegal instruction
|
`define CPU_BREAK_BIT 7
|
`define CPU_BREAK_BIT 7
|
`define CPU_STEP_BIT 6 // Will step one or two (VLIW) instructions
|
`define CPU_STEP_BIT 6 // Will step one (or two CIS) instructions
|
`define CPU_GIE_BIT 5
|
`define CPU_GIE_BIT 5
|
`define CPU_SLEEP_BIT 4
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`define CPU_SLEEP_BIT 4
|
// Compile time defines
|
// Compile time defines
|
//
|
//
|
`include "cpudefs.v"
|
`include "cpudefs.v"
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| Line 123... |
Line 123... |
o_dbg_stall, o_dbg_reg, o_dbg_cc,
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o_dbg_stall, o_dbg_reg, o_dbg_cc,
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o_break,
|
o_break,
|
// CPU interface to the wishbone bus
|
// CPU interface to the wishbone bus
|
o_wb_gbl_cyc, o_wb_gbl_stb,
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o_wb_gbl_cyc, o_wb_gbl_stb,
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o_wb_lcl_cyc, o_wb_lcl_stb,
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o_wb_lcl_cyc, o_wb_lcl_stb,
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o_wb_we, o_wb_addr, o_wb_data,
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o_wb_we, o_wb_addr, o_wb_data, o_wb_sel,
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i_wb_ack, i_wb_stall, i_wb_data,
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i_wb_ack, i_wb_stall, i_wb_data,
|
i_wb_err,
|
i_wb_err,
|
// Accounting/CPU usage interface
|
// Accounting/CPU usage interface
|
o_op_stall, o_pf_stall, o_i_count
|
o_op_stall, o_pf_stall, o_i_count
|
`ifdef DEBUG_SCOPE
|
`ifdef DEBUG_SCOPE
|
, o_debug
|
, o_debug
|
`endif
|
`endif
|
);
|
);
|
parameter RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=24,
|
parameter [31:0] RESET_ADDRESS=32'h0100000;
|
LGICACHE=6;
|
parameter ADDRESS_WIDTH=30,
|
|
LGICACHE=8;
|
`ifdef OPT_MULTIPLY
|
`ifdef OPT_MULTIPLY
|
parameter IMPLEMENT_MPY = `OPT_MULTIPLY;
|
parameter IMPLEMENT_MPY = `OPT_MULTIPLY;
|
`else
|
`else
|
parameter IMPLEMENT_MPY = 0;
|
parameter IMPLEMENT_MPY = 0;
|
`endif
|
`endif
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| Line 155... |
Line 156... |
`ifdef OPT_EARLY_BRANCHING
|
`ifdef OPT_EARLY_BRANCHING
|
parameter EARLY_BRANCHING = 1;
|
parameter EARLY_BRANCHING = 1;
|
`else
|
`else
|
parameter EARLY_BRANCHING = 0;
|
parameter EARLY_BRANCHING = 0;
|
`endif
|
`endif
|
parameter AW=ADDRESS_WIDTH;
|
parameter WITH_LOCAL_BUS = 1;
|
|
localparam AW=ADDRESS_WIDTH;
|
|
localparam [(AW-1):0] RESET_BUS_ADDRESS = RESET_ADDRESS[(AW+1):2];
|
input i_clk, i_rst, i_interrupt;
|
input i_clk, i_rst, i_interrupt;
|
// Debug interface -- inputs
|
// Debug interface -- inputs
|
input i_halt, i_clear_pf_cache;
|
input i_halt, i_clear_pf_cache;
|
input [4:0] i_dbg_reg;
|
input [4:0] i_dbg_reg;
|
input i_dbg_we;
|
input i_dbg_we;
|
input [31:0] i_dbg_data;
|
input [31:0] i_dbg_data;
|
// Debug interface -- outputs
|
// Debug interface -- outputs
|
output reg o_dbg_stall;
|
output wire o_dbg_stall;
|
output reg [31:0] o_dbg_reg;
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output reg [31:0] o_dbg_reg;
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output reg [3:0] o_dbg_cc;
|
output reg [3:0] o_dbg_cc;
|
output wire o_break;
|
output wire o_break;
|
// Wishbone interface -- outputs
|
// Wishbone interface -- outputs
|
output wire o_wb_gbl_cyc, o_wb_gbl_stb;
|
output wire o_wb_gbl_cyc, o_wb_gbl_stb;
|
output wire o_wb_lcl_cyc, o_wb_lcl_stb, o_wb_we;
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output wire o_wb_lcl_cyc, o_wb_lcl_stb, o_wb_we;
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output wire [(AW-1):0] o_wb_addr;
|
output wire [(AW-1):0] o_wb_addr;
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output wire [31:0] o_wb_data;
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output wire [31:0] o_wb_data;
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|
output wire [3:0] o_wb_sel;
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// Wishbone interface -- inputs
|
// Wishbone interface -- inputs
|
input i_wb_ack, i_wb_stall;
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input i_wb_ack, i_wb_stall;
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input [31:0] i_wb_data;
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input [31:0] i_wb_data;
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input i_wb_err;
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input i_wb_err;
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// Accounting outputs ... to help us count stalls and usage
|
// Accounting outputs ... to help us count stalls and usage
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| Line 196... |
Line 200... |
// optimizes logic away, to where it no longer works. The logic
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// optimizes logic away, to where it no longer works. The logic
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// as described herein will work, this just makes sure XST implements
|
// as described herein will work, this just makes sure XST implements
|
// that logic.
|
// that logic.
|
//
|
//
|
(* ram_style = "distributed" *)
|
(* ram_style = "distributed" *)
|
|
`ifdef OPT_NO_USERMODE
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|
reg [31:0] regset [0:15];
|
|
`else
|
reg [31:0] regset [0:31];
|
reg [31:0] regset [0:31];
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|
`endif
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|
|
// Condition codes
|
// Condition codes
|
// (BUS, TRAP,ILL,BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z
|
// (BUS, TRAP,ILL,BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z
|
reg [3:0] flags, iflags;
|
reg [3:0] flags, iflags;
|
wire [13:0] w_uflags, w_iflags;
|
wire [14:0] w_uflags, w_iflags;
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reg trap, break_en, step, gie, sleep;
|
reg break_en, step, sleep, r_halted;
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
wire break_pending, trap, gie, ubreak;
|
reg ill_err_u, ill_err_i;
|
wire w_clear_icache, ill_err_u;
|
`else
|
reg ill_err_i;
|
wire ill_err_u, ill_err_i;
|
reg ibus_err_flag;
|
`endif
|
wire ubus_err_flag;
|
reg ibus_err_flag, ubus_err_flag;
|
|
wire idiv_err_flag, udiv_err_flag;
|
wire idiv_err_flag, udiv_err_flag;
|
wire ifpu_err_flag, ufpu_err_flag;
|
wire ifpu_err_flag, ufpu_err_flag;
|
wire ihalt_phase, uhalt_phase;
|
wire ihalt_phase, uhalt_phase;
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|
|
// The master chip enable
|
// The master chip enable
|
| Line 221... |
Line 228... |
//
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//
|
//
|
//
|
// PIPELINE STAGE #1 :: Prefetch
|
// PIPELINE STAGE #1 :: Prefetch
|
// Variable declarations
|
// Variable declarations
|
//
|
//
|
reg [(AW-1):0] pf_pc;
|
reg [(AW+1):0] pf_pc;
|
reg new_pc;
|
reg new_pc;
|
wire clear_pipeline;
|
wire clear_pipeline;
|
assign clear_pipeline = new_pc || i_clear_pf_cache;
|
assign clear_pipeline = new_pc;
|
|
|
wire dcd_stalled;
|
wire dcd_stalled;
|
wire pf_cyc, pf_stb, pf_we, pf_busy, pf_ack, pf_stall, pf_err;
|
wire pf_cyc, pf_stb, pf_we, pf_busy, pf_ack, pf_stall, pf_err;
|
wire [(AW-1):0] pf_addr;
|
wire [(AW-1):0] pf_addr;
|
wire [31:0] pf_data;
|
wire [31:0] pf_data;
|
wire [31:0] instruction;
|
wire [31:0] pf_instruction;
|
wire [(AW-1):0] instruction_pc;
|
wire [(AW-1):0] pf_instruction_pc;
|
wire pf_valid, instruction_gie, pf_illegal;
|
wire pf_valid, pf_gie, pf_illegal;
|
|
|
//
|
//
|
//
|
//
|
// PIPELINE STAGE #2 :: Instruction Decode
|
// PIPELINE STAGE #2 :: Instruction Decode
|
// Variable declarations
|
// Variable declarations
|
//
|
//
|
//
|
//
|
reg opvalid, opvalid_mem, opvalid_alu;
|
reg op_valid /* verilator public_flat */,
|
reg opvalid_div, opvalid_fpu;
|
op_valid_mem, op_valid_alu;
|
|
reg op_valid_div, op_valid_fpu;
|
wire op_stall, dcd_ce, dcd_phase;
|
wire op_stall, dcd_ce, dcd_phase;
|
wire [3:0] dcdOp;
|
wire [3:0] dcd_opn;
|
wire [4:0] dcdA, dcdB, dcdR;
|
wire [4:0] dcd_A, dcd_B, dcd_R;
|
wire dcdA_cc, dcdB_cc, dcdA_pc, dcdB_pc, dcdR_cc, dcdR_pc;
|
wire dcd_Acc, dcd_Bcc, dcd_Apc, dcd_Bpc, dcd_Rcc, dcd_Rpc;
|
wire [3:0] dcdF;
|
wire [3:0] dcd_F;
|
wire dcdR_wr, dcdA_rd, dcdB_rd,
|
wire dcd_wR, dcd_rA, dcd_rB,
|
dcdALU, dcdM, dcdDV, dcdFP,
|
dcd_ALU, dcd_M, dcd_DIV, dcd_FP,
|
dcdF_wr, dcd_gie, dcd_break, dcd_lock,
|
dcd_wF, dcd_gie, dcd_break, dcd_lock,
|
dcd_pipe, dcd_ljmp;
|
dcd_pipe, dcd_ljmp;
|
reg r_dcdvalid;
|
reg r_dcd_valid;
|
wire dcdvalid;
|
wire dcd_valid;
|
wire [(AW-1):0] dcd_pc;
|
wire [AW:0] dcd_pc /* verilator public_flat */;
|
wire [31:0] dcdI;
|
wire [31:0] dcd_I;
|
wire dcd_zI; // true if dcdI == 0
|
wire dcd_zI; // true if dcd_I == 0
|
wire dcdA_stall, dcdB_stall, dcdF_stall;
|
wire dcd_A_stall, dcd_B_stall, dcd_F_stall;
|
|
|
wire dcd_illegal;
|
wire dcd_illegal;
|
wire dcd_early_branch;
|
wire dcd_early_branch;
|
wire [(AW-1):0] dcd_branch_pc;
|
wire [(AW-1):0] dcd_branch_pc;
|
|
|
|
wire dcd_sim;
|
|
wire [22:0] dcd_sim_immv;
|
|
|
|
|
//
|
//
|
//
|
//
|
// PIPELINE STAGE #3 :: Read Operands
|
// PIPELINE STAGE #3 :: Read Operands
|
// Variable declarations
|
// Variable declarations
|
//
|
//
|
//
|
//
|
//
|
//
|
// Now, let's read our operands
|
// Now, let's read our operands
|
reg [4:0] alu_reg;
|
reg [4:0] alu_reg;
|
reg [3:0] opn;
|
wire [3:0] op_opn;
|
reg [4:0] opR;
|
wire [4:0] op_R;
|
reg [31:0] r_opA, r_opB;
|
reg [31:0] r_op_Av, r_op_Bv;
|
reg [(AW-1):0] op_pc;
|
reg [(AW-1):0] op_pc;
|
wire [31:0] w_opA, w_opB;
|
wire [31:0] w_op_Av, w_op_Bv;
|
wire [31:0] opA_nowait, opB_nowait, opA, opB;
|
wire [31:0] op_A_nowait, op_B_nowait, op_Av, op_Bv;
|
reg opR_wr, opR_cc, opF_wr, op_gie;
|
reg op_wR, op_wF;
|
wire [13:0] opFl;
|
wire op_gie, op_Rcc;
|
reg [5:0] r_opF;
|
wire [14:0] op_Fl;
|
wire [7:0] opF;
|
reg [6:0] r_op_F;
|
wire op_ce, op_phase, op_pipe;
|
wire [7:0] op_F;
|
|
wire op_ce, op_phase, op_pipe, op_change_data_ce;
|
// Some pipeline control wires
|
// Some pipeline control wires
|
`ifdef OPT_PIPELINED
|
`ifdef OPT_PIPELINED
|
reg opA_alu, opA_mem;
|
reg op_A_alu, op_A_mem;
|
reg opB_alu, opB_mem;
|
reg op_B_alu, op_B_mem;
|
`endif
|
`endif
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
|
reg op_illegal;
|
reg op_illegal;
|
`endif
|
wire op_break;
|
reg op_break;
|
|
wire op_lock;
|
wire op_lock;
|
|
|
|
`ifdef VERILATOR
|
|
reg op_sim /* verilator public_flat */;
|
|
reg [22:0] op_sim_immv /* verilator public_flat */;
|
|
`endif
|
|
|
|
|
//
|
//
|
//
|
//
|
// PIPELINE STAGE #4 :: ALU / Memory
|
// PIPELINE STAGE #4 :: ALU / Memory
|
// Variable declarations
|
// Variable declarations
|
//
|
//
|
//
|
//
|
reg [(AW-1):0] alu_pc;
|
wire [(AW-1):0] alu_pc;
|
reg r_alu_pc_valid, mem_pc_valid;
|
reg r_alu_pc_valid, mem_pc_valid;
|
wire alu_pc_valid;
|
wire alu_pc_valid;
|
wire alu_phase;
|
wire alu_phase;
|
wire alu_ce, alu_stall;
|
wire alu_ce /* verilator public_flat */, alu_stall;
|
wire [31:0] alu_result;
|
wire [31:0] alu_result;
|
wire [3:0] alu_flags;
|
wire [3:0] alu_flags;
|
wire alu_valid, alu_busy;
|
wire alu_valid, alu_busy;
|
wire set_cond;
|
wire set_cond;
|
reg alu_wr, alF_wr, alu_gie;
|
reg alu_wR, alu_wF;
|
wire alu_illegal_op;
|
wire alu_gie, alu_illegal;
|
wire alu_illegal;
|
|
|
|
|
|
|
|
wire mem_ce, mem_stalled;
|
wire mem_ce, mem_stalled;
|
`ifdef OPT_PIPELINED_BUS_ACCESS
|
|
wire mem_pipe_stalled;
|
wire mem_pipe_stalled;
|
`endif
|
|
wire mem_valid, mem_ack, mem_stall, mem_err, bus_err,
|
wire mem_valid, mem_ack, mem_stall, mem_err, bus_err,
|
mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl, mem_we;
|
mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl, mem_we;
|
wire [4:0] mem_wreg;
|
wire [4:0] mem_wreg;
|
|
|
wire mem_busy, mem_rdbusy;
|
wire mem_busy, mem_rdbusy;
|
wire [(AW-1):0] mem_addr;
|
wire [(AW-1):0] mem_addr;
|
wire [31:0] mem_data, mem_result;
|
wire [31:0] mem_data, mem_result;
|
|
wire [3:0] mem_sel;
|
|
|
wire div_ce, div_error, div_busy, div_valid;
|
wire div_ce, div_error, div_busy, div_valid;
|
wire [31:0] div_result;
|
wire [31:0] div_result;
|
wire [3:0] div_flags;
|
wire [3:0] div_flags;
|
|
|
assign div_ce = (master_ce)&&(~clear_pipeline)&&(opvalid_div)
|
assign div_ce = (master_ce)&&(~clear_pipeline)&&(op_valid_div)
|
&&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy)
|
&&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy)
|
&&(set_cond);
|
&&(set_cond);
|
|
|
wire fpu_ce, fpu_error, fpu_busy, fpu_valid;
|
wire fpu_ce, fpu_error, fpu_busy, fpu_valid;
|
wire [31:0] fpu_result;
|
wire [31:0] fpu_result;
|
wire [3:0] fpu_flags;
|
wire [3:0] fpu_flags;
|
|
|
assign fpu_ce = (master_ce)&&(~clear_pipeline)&&(opvalid_fpu)
|
assign fpu_ce = (master_ce)&&(~clear_pipeline)&&(op_valid_fpu)
|
&&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy)
|
&&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy)
|
&&(set_cond);
|
&&(set_cond);
|
|
|
|
wire adf_ce_unconditional;
|
|
|
//
|
//
|
//
|
//
|
// PIPELINE STAGE #5 :: Write-back
|
// PIPELINE STAGE #5 :: Write-back
|
// Variable declarations
|
// Variable declarations
|
//
|
//
|
wire wr_reg_ce, wr_flags_ce, wr_write_pc, wr_write_cc;
|
wire wr_reg_ce, wr_flags_ce, wr_write_pc, wr_write_cc,
|
|
wr_write_scc, wr_write_ucc;
|
wire [4:0] wr_reg_id;
|
wire [4:0] wr_reg_id;
|
wire [31:0] wr_reg_vl;
|
wire [31:0] wr_gpreg_vl, wr_spreg_vl;
|
wire w_switch_to_interrupt, w_release_from_interrupt;
|
wire w_switch_to_interrupt, w_release_from_interrupt;
|
reg [(AW-1):0] upc, ipc;
|
reg [(AW+1):0] ipc;
|
|
wire [(AW+1):0] upc;
|
|
|
|
|
|
|
//
|
//
|
// MASTER: clock enable.
|
// MASTER: clock enable.
|
//
|
//
|
assign master_ce = (~i_halt)&&(~o_break)&&(~sleep);
|
assign master_ce = ((~i_halt)||(alu_phase))&&(~o_break)&&(~sleep);
|
|
|
|
|
//
|
//
|
// PIPELINE STAGE #1 :: Prefetch
|
// PIPELINE STAGE #1 :: Prefetch
|
// Calculate stall conditions
|
// Calculate stall conditions
|
| Line 374... |
Line 390... |
//
|
//
|
|
|
//
|
//
|
// PIPELINE STAGE #2 :: Instruction Decode
|
// PIPELINE STAGE #2 :: Instruction Decode
|
// Calculate stall conditions
|
// Calculate stall conditions
|
assign dcd_ce = ((~dcdvalid)||(~dcd_stalled))&&(~clear_pipeline);
|
assign dcd_ce = ((~dcd_valid)||(~dcd_stalled))&&(~clear_pipeline);
|
|
|
`ifdef OPT_PIPELINED
|
`ifdef OPT_PIPELINED
|
assign dcd_stalled = (dcdvalid)&&(op_stall);
|
assign dcd_stalled = (dcd_valid)&&(op_stall);
|
`else
|
`else
|
// If not pipelined, there will be no opvalid_ anything, and the
|
// If not pipelined, there will be no op_valid_ anything, and the
|
// op_stall will be false, dcdX_stall will be false, thus we can simply
|
// op_stall will be false, dcd_X_stall will be false, thus we can simply
|
// do a ...
|
// do a ...
|
assign dcd_stalled = 1'b0;
|
assign dcd_stalled = 1'b0;
|
`endif
|
`endif
|
//
|
//
|
// PIPELINE STAGE #3 :: Read Operands
|
// PIPELINE STAGE #3 :: Read Operands
|
// Calculate stall conditions
|
// Calculate stall conditions
|
wire op_lock_stall;
|
wire prelock_stall;
|
`ifdef OPT_PIPELINED
|
`ifdef OPT_PIPELINED
|
assign op_stall = (opvalid)&&( // Only stall if we're loaded w/validins
|
reg cc_invalid_for_dcd;
|
|
always @(posedge i_clk)
|
|
cc_invalid_for_dcd <= (wr_flags_ce)
|
|
||(wr_reg_ce)&&(wr_reg_id[3:0] == `CPU_CC_REG)
|
|
||(op_valid)&&((op_wF)||((op_wR)&&(op_R[3:0] == `CPU_CC_REG)))
|
|
||((alu_wF)||((alu_wR)&&(alu_reg[3:0] == `CPU_CC_REG)))
|
|
||(mem_busy)||(div_busy)||(fpu_busy);
|
|
|
|
assign op_stall = (op_valid)&&( // Only stall if we're loaded w/validins
|
// Stall if we're stopped, and not allowed to execute
|
// Stall if we're stopped, and not allowed to execute
|
// an instruction
|
// an instruction
|
// (~master_ce) // Already captured in alu_stall
|
// (~master_ce) // Already captured in alu_stall
|
//
|
//
|
// Stall if going into the ALU and the ALU is stalled
|
// Stall if going into the ALU and the ALU is stalled
|
| Line 402... |
Line 426... |
// op_break and op_lock, so we don't need to
|
// op_break and op_lock, so we don't need to
|
// include those as well here.
|
// include those as well here.
|
// This also includes whether or not the divide or
|
// This also includes whether or not the divide or
|
// floating point units are busy.
|
// floating point units are busy.
|
(alu_stall)
|
(alu_stall)
|
|
||(((op_valid_div)||(op_valid_fpu))
|
|
&&(!adf_ce_unconditional))
|
//
|
//
|
// Stall if we are going into memory with an operation
|
// Stall if we are going into memory with an operation
|
// that cannot be pipelined, and the memory is
|
// that cannot be pipelined, and the memory is
|
// already busy
|
// already busy
|
||(mem_stalled) // &&(opvalid_mem) part of mem_stalled
|
||(mem_stalled) // &&(op_valid_mem) part of mem_stalled
|
|
||(op_Rcc)
|
)
|
)
|
||(dcdvalid)&&(
|
||(dcd_valid)&&(
|
// Stall if we need to wait for an operand A
|
// Stall if we need to wait for an operand A
|
// to be ready to read
|
// to be ready to read
|
(dcdA_stall)
|
(dcd_A_stall)
|
// Likewise for B, also includes logic
|
// Likewise for B, also includes logic
|
// regarding immediate offset (register must
|
// regarding immediate offset (register must
|
// be in register file if we need to add to
|
// be in register file if we need to add to
|
// an immediate)
|
// an immediate)
|
||(dcdB_stall)
|
||(dcd_B_stall)
|
// Or if we need to wait on flags to work on the
|
// Or if we need to wait on flags to work on the
|
// CC register
|
// CC register
|
||(dcdF_stall)
|
||(dcd_F_stall)
|
);
|
);
|
assign op_ce = ((dcdvalid)||(dcd_illegal))&&(~op_stall)&&(~clear_pipeline);
|
assign op_ce = ((dcd_valid)||(dcd_illegal)||(dcd_early_branch))&&(!op_stall);
|
`else
|
|
assign op_stall = (opvalid)&&(~master_ce);
|
|
assign op_ce = ((dcdvalid)||(dcd_illegal))&&(~clear_pipeline);
|
// BUT ... op_ce is too complex for many of the data operations. So
|
|
// let's make their circuit enable code simpler. In particular, if
|
|
// op_ doesn't need to be preserved, we can change it all we want
|
|
// ... right? The clear_pipeline code, for example, really only needs
|
|
// to determine whether op_valid is true.
|
|
assign op_change_data_ce = (~op_stall);
|
|
`else
|
|
assign op_stall = (op_valid)&&(~master_ce);
|
|
assign op_ce = ((dcd_valid)||(dcd_illegal)||(dcd_early_branch))&&(~clear_pipeline);
|
|
assign op_change_data_ce = 1'b1;
|
`endif
|
`endif
|
|
|
//
|
//
|
// PIPELINE STAGE #4 :: ALU / Memory
|
// PIPELINE STAGE #4 :: ALU / Memory
|
// Calculate stall conditions
|
// Calculate stall conditions
|
| Line 441... |
Line 477... |
// since we don't know if it'll put us to sleep or not.
|
// since we don't know if it'll put us to sleep or not.
|
// 4. Last case: Stall if we would otherwise move a break instruction
|
// 4. Last case: Stall if we would otherwise move a break instruction
|
// through the ALU. Break instructions are not allowed through
|
// through the ALU. Break instructions are not allowed through
|
// the ALU.
|
// the ALU.
|
`ifdef OPT_PIPELINED
|
`ifdef OPT_PIPELINED
|
assign alu_stall = (((~master_ce)||(mem_rdbusy)||(alu_busy))&&(opvalid_alu)) //Case 1&2
|
assign alu_stall = (((~master_ce)||(mem_rdbusy)||(alu_busy))&&(op_valid_alu)) //Case 1&2
|
// Old case #3--this isn't an ALU stall though ...
|
||(prelock_stall)
|
||((opvalid_alu)&&(wr_reg_ce)&&(wr_reg_id[4] == op_gie)
|
||((op_valid)&&(op_break))
|
&&(wr_write_cc)) // Case 3
|
||(wr_reg_ce)&&(wr_write_cc)
|
||((opvalid)&&(op_lock)&&(op_lock_stall))
|
|
||((opvalid)&&(op_break))
|
|
||(div_busy)||(fpu_busy);
|
||(div_busy)||(fpu_busy);
|
assign alu_ce = (master_ce)&&((opvalid_alu)||(op_illegal))
|
assign alu_ce = (master_ce)&&(op_valid_alu)&&(~alu_stall)
|
&&(~alu_stall)
|
|
&&(~clear_pipeline);
|
&&(~clear_pipeline);
|
`else
|
`else
|
assign alu_stall = ((~master_ce)&&(opvalid_alu))
|
assign alu_stall = (op_valid_alu)&&((~master_ce)||(op_break));
|
||((opvalid_alu)&&(op_break));
|
assign alu_ce = (master_ce)&&(op_valid_alu)&&(~alu_stall)&&(~clear_pipeline);
|
assign alu_ce = (master_ce)&&((opvalid_alu)||(op_illegal))&&(~alu_stall)&&(~clear_pipeline);
|
|
`endif
|
`endif
|
//
|
//
|
|
|
//
|
//
|
// Note: if you change the conditions for mem_ce, you must also change
|
// Note: if you change the conditions for mem_ce, you must also change
|
// alu_pc_valid.
|
// alu_pc_valid.
|
//
|
//
|
`ifdef OPT_PIPELINED
|
`ifdef OPT_PIPELINED
|
assign mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled)
|
assign mem_ce = (master_ce)&&(op_valid_mem)&&(~mem_stalled)
|
&&(~clear_pipeline);
|
&&(~clear_pipeline);
|
`else
|
`else
|
// If we aren't pipelined, then no one will be changing what's in the
|
// If we aren't pipelined, then no one will be changing what's in the
|
// pipeline (i.e. clear_pipeline), while our only instruction goes
|
// pipeline (i.e. clear_pipeline), while our only instruction goes
|
// through the ... pipeline.
|
// through the ... pipeline.
|
//
|
//
|
// However, in hind sight this logic didn't work. What happens when
|
// However, in hind sight this logic didn't work. What happens when
|
// something gets in the pipeline and then (due to interrupt or some
|
// something gets in the pipeline and then (due to interrupt or some
|
// such) needs to be voided? Thus we avoid simplification and keep
|
// such) needs to be voided? Thus we avoid simplification and keep
|
// what worked here.
|
// what worked here.
|
assign mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled)
|
assign mem_ce = (master_ce)&&(op_valid_mem)&&(~mem_stalled)
|
&&(~clear_pipeline);
|
&&(~clear_pipeline);
|
`endif
|
`endif
|
`ifdef OPT_PIPELINED_BUS_ACCESS
|
`ifdef OPT_PIPELINED_BUS_ACCESS
|
assign mem_stalled = (~master_ce)||(alu_busy)||((opvalid_mem)&&(
|
assign mem_stalled = (~master_ce)||(alu_busy)||((op_valid_mem)&&(
|
(mem_pipe_stalled)
|
(mem_pipe_stalled)
|
|
||(prelock_stall)
|
||((~op_pipe)&&(mem_busy))
|
||((~op_pipe)&&(mem_busy))
|
||(div_busy)
|
||(div_busy)
|
||(fpu_busy)
|
||(fpu_busy)
|
// Stall waiting for flags to be valid
|
// Stall waiting for flags to be valid
|
// Or waiting for a write to the PC register
|
// Or waiting for a write to the PC register
|
| Line 491... |
Line 524... |
// PC as well
|
// PC as well
|
||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)
|
||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)
|
&&((wr_write_pc)||(wr_write_cc)))));
|
&&((wr_write_pc)||(wr_write_cc)))));
|
`else
|
`else
|
`ifdef OPT_PIPELINED
|
`ifdef OPT_PIPELINED
|
assign mem_stalled = (mem_busy)||((opvalid_mem)&&(
|
assign mem_stalled = (mem_busy)||((op_valid_mem)&&(
|
(~master_ce)
|
(~master_ce)
|
// Stall waiting for flags to be valid
|
// Stall waiting for flags to be valid
|
// Or waiting for a write to the PC register
|
// Or waiting for a write to the PC register
|
// Or CC register, since that can change the
|
// Or CC register, since that can change the
|
// PC as well
|
// PC as well
|
||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)&&((wr_write_pc)||(wr_write_cc)))));
|
||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)&&((wr_write_pc)||(wr_write_cc)))));
|
`else
|
`else
|
assign mem_stalled = (opvalid_mem)&&(~master_ce);
|
assign mem_stalled = (op_valid_mem)&&(~master_ce);
|
`endif
|
`endif
|
`endif
|
`endif
|
|
|
|
// ALU, DIV, or FPU CE ... equivalent to the OR of all three of these
|
|
assign adf_ce_unconditional = (master_ce)&&(~clear_pipeline)&&(op_valid)
|
|
&&(~op_valid_mem)&&(~mem_rdbusy)
|
|
&&((~op_valid_alu)||(~alu_stall))&&(~op_break)
|
|
&&(~div_busy)&&(~fpu_busy)&&(~clear_pipeline);
|
|
|
//
|
//
|
//
|
//
|
// PIPELINE STAGE #1 :: Prefetch
|
// PIPELINE STAGE #1 :: Prefetch
|
//
|
//
|
//
|
//
|
`ifdef OPT_SINGLE_FETCH
|
`ifdef OPT_SINGLE_FETCH
|
wire pf_ce;
|
wire pf_ce;
|
|
|
assign pf_ce = (~pf_valid)&&(~dcdvalid)&&(~opvalid)&&(~alu_busy)&&(~mem_busy)&&(~alu_pc_valid)&&(~mem_pc_valid);
|
assign pf_ce = (~pf_valid)&&(~dcd_valid)&&(~op_valid)&&(~alu_busy)&&(~mem_busy)&&(~alu_pc_valid)&&(~mem_pc_valid);
|
prefetch #(ADDRESS_WIDTH)
|
prefetch #(ADDRESS_WIDTH)
|
pf(i_clk, (i_rst), (pf_ce), (~dcd_stalled), pf_pc, gie,
|
pf(i_clk, (i_rst), (pf_ce), (~dcd_stalled), pf_pc[(AW+1):2], gie,
|
instruction, instruction_pc, instruction_gie,
|
pf_instruction, pf_instruction_pc, pf_gie,
|
pf_valid, pf_illegal,
|
pf_valid, pf_illegal,
|
pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
|
pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
|
pf_ack, pf_stall, pf_err, i_wb_data);
|
pf_ack, pf_stall, pf_err, i_wb_data);
|
|
|
initial r_dcdvalid = 1'b0;
|
initial r_dcd_valid = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((i_rst)||(clear_pipeline))
|
if (clear_pipeline)
|
r_dcdvalid <= 1'b0;
|
r_dcd_valid <= 1'b0;
|
else if (dcd_ce)
|
else if (dcd_ce)
|
r_dcdvalid <= (pf_valid);
|
r_dcd_valid <= (pf_valid)||(pf_illegal);
|
else if (op_ce)
|
else if (op_ce)
|
r_dcdvalid <= 1'b0;
|
r_dcd_valid <= 1'b0;
|
assign dcdvalid = r_dcdvalid;
|
assign dcd_valid = r_dcd_valid;
|
|
|
`else // Pipe fetch
|
`else // Pipe fetch
|
|
|
|
wire pf_stalled;
|
|
assign pf_stalled = (dcd_stalled)||(dcd_phase);
|
`ifdef OPT_TRADITIONAL_PFCACHE
|
`ifdef OPT_TRADITIONAL_PFCACHE
|
|
wire [(AW-1):0] pf_request_address;
|
|
assign pf_request_address = ((dcd_early_branch)&&(!clear_pipeline))
|
|
? dcd_branch_pc:pf_pc[(AW+1):2];
|
pfcache #(LGICACHE, ADDRESS_WIDTH)
|
pfcache #(LGICACHE, ADDRESS_WIDTH)
|
pf(i_clk, i_rst, (new_pc)||((dcd_early_branch)&&(~clear_pipeline)),
|
pf(i_clk, i_rst, (new_pc)||((dcd_early_branch)&&(~clear_pipeline)),
|
i_clear_pf_cache,
|
w_clear_icache,
|
// dcd_pc,
|
// dcd_pc,
|
~dcd_stalled,
|
(!pf_stalled),
|
((dcd_early_branch)&&(~clear_pipeline))
|
pf_request_address,
|
? dcd_branch_pc:pf_pc,
|
pf_instruction, pf_instruction_pc, pf_valid,
|
instruction, instruction_pc, pf_valid,
|
|
pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
|
pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
|
pf_ack, pf_stall, pf_err, i_wb_data,
|
pf_ack, pf_stall, pf_err, i_wb_data,
|
pf_illegal);
|
pf_illegal);
|
`else
|
`else
|
pipefetch #(RESET_ADDRESS, LGICACHE, ADDRESS_WIDTH)
|
pipefetch #(RESET_BUS_ADDRESS, LGICACHE, ADDRESS_WIDTH)
|
pf(i_clk, i_rst, (new_pc)||((dcd_early_branch)&&(~clear_pipeline)),
|
pf(i_clk, i_rst, (new_pc)||(dcd_early_branch),
|
i_clear_pf_cache, ~dcd_stalled,
|
w_clear_icache, (!pf_stalled),
|
(new_pc)?pf_pc:dcd_branch_pc,
|
(new_pc)?pf_pc[(AW+1):2]:dcd_branch_pc,
|
instruction, instruction_pc, pf_valid,
|
pf_instruction, pf_instruction_pc, pf_valid,
|
pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
|
pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
|
pf_ack, pf_stall, pf_err, i_wb_data,
|
pf_ack, pf_stall, pf_err, i_wb_data,
|
//`ifdef OPT_PRECLEAR_BUS
|
|
//((dcd_clear_bus)&&(dcdvalid))
|
|
//||((op_clear_bus)&&(opvalid))
|
|
//||
|
|
//`endif
|
|
(mem_cyc_lcl)||(mem_cyc_gbl),
|
(mem_cyc_lcl)||(mem_cyc_gbl),
|
pf_illegal);
|
pf_illegal);
|
`endif
|
`endif
|
assign instruction_gie = gie;
|
`ifdef OPT_NO_USERMODE
|
|
assign pf_gie = 1'b0;
|
|
`else
|
|
assign pf_gie = gie;
|
|
`endif
|
|
|
initial r_dcdvalid = 1'b0;
|
initial r_dcd_valid = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((i_rst)||(clear_pipeline))
|
if ((clear_pipeline)||(w_clear_icache))
|
r_dcdvalid <= 1'b0;
|
r_dcd_valid <= 1'b0;
|
else if (dcd_ce)
|
else if (dcd_ce)
|
r_dcdvalid <= (pf_valid)&&(~dcd_ljmp)&&((~r_dcdvalid)||(~dcd_early_branch));
|
r_dcd_valid <= ((dcd_phase)||(pf_valid))
|
|
&&(~dcd_ljmp)&&(~dcd_early_branch);
|
else if (op_ce)
|
else if (op_ce)
|
r_dcdvalid <= 1'b0;
|
r_dcd_valid <= 1'b0;
|
assign dcdvalid = r_dcdvalid;
|
assign dcd_valid = r_dcd_valid;
|
`endif
|
`endif
|
|
|
`ifdef OPT_NEW_INSTRUCTION_SET
|
// If not pipelined, there will be no op_valid_ anything, and the
|
idecode #(AW, IMPLEMENT_MPY, EARLY_BRANCHING, IMPLEMENT_DIVIDE,
|
idecode #(AW, IMPLEMENT_MPY, EARLY_BRANCHING, IMPLEMENT_DIVIDE,
|
IMPLEMENT_FPU)
|
IMPLEMENT_FPU)
|
instruction_decoder(i_clk, (i_rst)||(clear_pipeline),
|
instruction_decoder(i_clk, (clear_pipeline),
|
dcd_ce, dcd_stalled, instruction, instruction_gie,
|
(~dcd_valid)||(~op_stall), dcd_stalled, pf_instruction, pf_gie,
|
instruction_pc, pf_valid, pf_illegal, dcd_phase,
|
pf_instruction_pc, pf_valid, pf_illegal, dcd_phase,
|
dcd_illegal, dcd_pc, dcd_gie,
|
dcd_illegal, dcd_pc, dcd_gie,
|
{ dcdR_cc, dcdR_pc, dcdR },
|
{ dcd_Rcc, dcd_Rpc, dcd_R },
|
{ dcdA_cc, dcdA_pc, dcdA },
|
{ dcd_Acc, dcd_Apc, dcd_A },
|
{ dcdB_cc, dcdB_pc, dcdB },
|
{ dcd_Bcc, dcd_Bpc, dcd_B },
|
dcdI, dcd_zI, dcdF, dcdF_wr, dcdOp,
|
dcd_I, dcd_zI, dcd_F, dcd_wF, dcd_opn,
|
dcdALU, dcdM, dcdDV, dcdFP, dcd_break, dcd_lock,
|
dcd_ALU, dcd_M, dcd_DIV, dcd_FP, dcd_break, dcd_lock,
|
dcdR_wr,dcdA_rd, dcdB_rd,
|
dcd_wR,dcd_rA, dcd_rB,
|
dcd_early_branch,
|
dcd_early_branch,
|
dcd_branch_pc, dcd_ljmp,
|
dcd_branch_pc, dcd_ljmp,
|
dcd_pipe);
|
dcd_pipe,
|
`else
|
dcd_sim, dcd_sim_immv);
|
idecode_deprecated
|
|
#(AW, IMPLEMENT_MPY, EARLY_BRANCHING, IMPLEMENT_DIVIDE,
|
|
IMPLEMENT_FPU)
|
|
instruction_decoder(i_clk, (i_rst)||(clear_pipeline),
|
|
dcd_ce, dcd_stalled, instruction, instruction_gie,
|
|
instruction_pc, pf_valid, pf_illegal, dcd_phase,
|
|
dcd_illegal, dcd_pc, dcd_gie,
|
|
{ dcdR_cc, dcdR_pc, dcdR },
|
|
{ dcdA_cc, dcdA_pc, dcdA },
|
|
{ dcdB_cc, dcdB_pc, dcdB },
|
|
dcdI, dcd_zI, dcdF, dcdF_wr, dcdOp,
|
|
dcdALU, dcdM, dcdDV, dcdFP, dcd_break, dcd_lock,
|
|
dcdR_wr,dcdA_rd, dcdB_rd,
|
|
dcd_early_branch,
|
|
dcd_branch_pc,
|
|
dcd_pipe);
|
|
assign dcd_ljmp = 1'b0;
|
|
`endif
|
|
|
|
`ifdef OPT_PIPELINED_BUS_ACCESS
|
`ifdef OPT_PIPELINED_BUS_ACCESS
|
reg r_op_pipe;
|
reg r_op_pipe;
|
|
|
initial r_op_pipe = 1'b0;
|
initial r_op_pipe = 1'b0;
|
| Line 623... |
Line 647... |
// or at least a single (one) increment above that address
|
// or at least a single (one) increment above that address
|
//
|
//
|
// However ... we need to know this before this clock, hence this is
|
// However ... we need to know this before this clock, hence this is
|
// calculated in the instruction decoder.
|
// calculated in the instruction decoder.
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (op_ce)
|
if (clear_pipeline)
|
|
r_op_pipe <= 1'b0;
|
|
else if (op_ce)
|
r_op_pipe <= dcd_pipe;
|
r_op_pipe <= dcd_pipe;
|
else if (mem_ce) // Clear us any time an op_ is clocked in
|
else if (mem_ce) // Clear us any time an op_ is clocked in
|
r_op_pipe <= 1'b0;
|
r_op_pipe <= 1'b0;
|
assign op_pipe = r_op_pipe;
|
assign op_pipe = r_op_pipe;
|
`else
|
`else
|
| Line 637... |
Line 663... |
//
|
//
|
//
|
//
|
// PIPELINE STAGE #3 :: Read Operands (Registers)
|
// PIPELINE STAGE #3 :: Read Operands (Registers)
|
//
|
//
|
//
|
//
|
assign w_opA = regset[dcdA];
|
`ifdef OPT_NO_USERMODE
|
assign w_opB = regset[dcdB];
|
assign w_op_Av = regset[dcd_A[3:0]];
|
|
assign w_op_Bv = regset[dcd_B[3:0]];
|
|
`else
|
|
assign w_op_Av = regset[dcd_A];
|
|
assign w_op_Bv = regset[dcd_B];
|
|
`endif
|
|
|
wire [8:0] w_cpu_info;
|
wire [8:0] w_cpu_info;
|
assign w_cpu_info = {
|
assign w_cpu_info = {
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
|
1'b1,
|
1'b1,
|
`else
|
(IMPLEMENT_MPY >0)? 1'b1:1'b0,
|
1'b0,
|
(IMPLEMENT_DIVIDE >0)? 1'b1:1'b0,
|
`endif
|
(IMPLEMENT_FPU >0)? 1'b1:1'b0,
|
`ifdef OPT_MULTIPLY
|
|
1'b1,
|
|
`else
|
|
1'b0,
|
|
`endif
|
|
`ifdef OPT_DIVIDE
|
|
1'b1,
|
|
`else
|
|
1'b0,
|
|
`endif
|
|
`ifdef OPT_IMPLEMENT_FPU
|
|
1'b1,
|
|
`else
|
|
1'b0,
|
|
`endif
|
|
`ifdef OPT_PIPELINED
|
`ifdef OPT_PIPELINED
|
1'b1,
|
1'b1,
|
`else
|
`else
|
1'b0,
|
1'b0,
|
`endif
|
`endif
|
| Line 682... |
Line 697... |
`ifdef OPT_PIPELINED_BUS_ACCESS
|
`ifdef OPT_PIPELINED_BUS_ACCESS
|
1'b1,
|
1'b1,
|
`else
|
`else
|
1'b0,
|
1'b0,
|
`endif
|
`endif
|
`ifdef OPT_VLIW
|
`ifdef OPT_CIS
|
1'b1
|
1'b1
|
`else
|
`else
|
1'b0
|
1'b0
|
`endif
|
`endif
|
};
|
};
|
|
|
wire [31:0] w_pcA_v;
|
wire [31:0] w_pcA_v;
|
|
assign w_pcA_v[(AW+1):0] = { (dcd_A[4] == dcd_gie)
|
|
? { dcd_pc[AW:1], 2'b00 }
|
|
: { upc[(AW+1):2], uhalt_phase, 1'b0 } };
|
generate
|
generate
|
if (AW < 32)
|
if (AW < 30)
|
assign w_pcA_v = {{(32-AW){1'b0}}, (dcdA[4] == dcd_gie)?dcd_pc:upc };
|
assign w_pcA_v[31:(AW+2)] = 0;
|
else
|
|
assign w_pcA_v = (dcdA[4] == dcd_gie)?dcd_pc:upc;
|
|
endgenerate
|
endgenerate
|
|
|
`ifdef OPT_PIPELINED
|
`ifdef OPT_PIPELINED
|
reg [4:0] opA_id, opB_id;
|
reg [4:0] op_Aid, op_Bid;
|
reg opA_rd, opB_rd;
|
reg op_rA, op_rB;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (op_ce)
|
if (op_ce)
|
begin
|
begin
|
opA_id <= dcdA;
|
op_Aid <= dcd_A;
|
opB_id <= dcdB;
|
op_Bid <= dcd_B;
|
opA_rd <= dcdA_rd;
|
op_rA <= dcd_rA;
|
opB_rd <= dcdB_rd;
|
op_rB <= dcd_rB;
|
end
|
end
|
`endif
|
`endif
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (op_ce) // &&(dcdvalid))
|
`ifdef OPT_PIPELINED
|
|
if (op_ce)
|
|
`endif
|
begin
|
begin
|
if ((wr_reg_ce)&&(wr_reg_id == dcdA))
|
`ifdef OPT_PIPELINED
|
r_opA <= wr_reg_vl;
|
if ((wr_reg_ce)&&(wr_reg_id == dcd_A))
|
else if (dcdA_pc)
|
r_op_Av <= wr_gpreg_vl;
|
r_opA <= w_pcA_v;
|
else
|
else if (dcdA_cc)
|
`endif
|
r_opA <= { w_cpu_info, w_opA[22:14], (dcdA[4])?w_uflags:w_iflags };
|
if (dcd_Apc)
|
|
r_op_Av <= w_pcA_v;
|
|
else if (dcd_Acc)
|
|
r_op_Av <= { w_cpu_info, w_op_Av[22:16], 1'b0, (dcd_A[4])?w_uflags:w_iflags };
|
else
|
else
|
r_opA <= w_opA;
|
r_op_Av <= w_op_Av;
|
`ifdef OPT_PIPELINED
|
`ifdef OPT_PIPELINED
|
end else
|
end else
|
begin // We were going to pick these up when they became valid,
|
begin // We were going to pick these up when they became valid,
|
// but for some reason we're stuck here as they became
|
// but for some reason we're stuck here as they became
|
// valid. Pick them up now anyway
|
// valid. Pick them up now anyway
|
// if (((opA_alu)&&(alu_wr))||((opA_mem)&&(mem_valid)))
|
// if (((op_A_alu)&&(alu_wR))||((op_A_mem)&&(mem_valid)))
|
// r_opA <= wr_reg_vl;
|
// r_op_Av <= wr_gpreg_vl;
|
if ((wr_reg_ce)&&(wr_reg_id == opA_id)&&(opA_rd))
|
if ((wr_reg_ce)&&(wr_reg_id == op_Aid)&&(op_rA))
|
r_opA <= wr_reg_vl;
|
r_op_Av <= wr_gpreg_vl;
|
`endif
|
`endif
|
end
|
end
|
|
|
wire [31:0] w_opBnI, w_pcB_v;
|
wire [31:0] w_op_BnI, w_pcB_v;
|
|
assign w_pcB_v[(AW+1):0] = { (dcd_B[4] == dcd_gie)
|
|
? { dcd_pc[AW:1], 2'b00 }
|
|
: { upc[(AW+1):2], uhalt_phase, 1'b0 } };
|
generate
|
generate
|
if (AW < 32)
|
if (AW < 30)
|
assign w_pcB_v = {{(32-AW){1'b0}}, (dcdB[4] == dcd_gie)?dcd_pc:upc };
|
assign w_pcB_v[31:(AW+2)] = 0;
|
else
|
|
assign w_pcB_v = (dcdB[4] == dcd_gie)?dcd_pc:upc;
|
|
endgenerate
|
endgenerate
|
|
|
assign w_opBnI = (~dcdB_rd) ? 32'h00
|
assign w_op_BnI = (!dcd_rB) ? 32'h00
|
: (((wr_reg_ce)&&(wr_reg_id == dcdB)) ? wr_reg_vl
|
`ifdef OPT_PIPELINED
|
: ((dcdB_pc) ? w_pcB_v
|
: ((wr_reg_ce)&&(wr_reg_id == dcd_B)) ? wr_gpreg_vl
|
: ((dcdB_cc) ? { w_cpu_info, w_opB[22:14], // w_opB[31:14],
|
`endif
|
(dcdB[4])?w_uflags:w_iflags}
|
: ((dcd_Bcc) ? { w_cpu_info, w_op_Bv[22:16], // w_op_B[31:14],
|
: w_opB)));
|
1'b0, (dcd_B[4])?w_uflags:w_iflags}
|
|
: w_op_Bv);
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (op_ce) // &&(dcdvalid))
|
|
r_opB <= w_opBnI + dcdI;
|
|
`ifdef OPT_PIPELINED
|
`ifdef OPT_PIPELINED
|
else if ((wr_reg_ce)&&(opB_id == wr_reg_id)&&(opB_rd))
|
if ((op_ce)&&(dcd_Bpc)&&(dcd_rB))
|
r_opB <= wr_reg_vl;
|
r_op_Bv <= w_pcB_v + { dcd_I[29:0], 2'b00 };
|
|
else if (op_ce)
|
|
r_op_Bv <= w_op_BnI + dcd_I;
|
|
else if ((wr_reg_ce)&&(op_Bid == wr_reg_id)&&(op_rB))
|
|
r_op_Bv <= wr_gpreg_vl;
|
|
`else
|
|
if ((dcd_Bpc)&&(dcd_rB))
|
|
r_op_Bv <= w_pcB_v + { dcd_I[29:0], 2'b00 };
|
|
else
|
|
r_op_Bv <= w_op_BnI + dcd_I;
|
`endif
|
`endif
|
|
|
// The logic here has become more complex than it should be, no thanks
|
// The logic here has become more complex than it should be, no thanks
|
// to Xilinx's Vivado trying to help. The conditions are supposed to
|
// to Xilinx's Vivado trying to help. The conditions are supposed to
|
// be two sets of four bits: the top bits specify what bits matter, the
|
// be two sets of four bits: the top bits specify what bits matter, the
|
// bottom specify what those top bits must equal. However, two of
|
// bottom specify what those top bits must equal. However, two of
|
// conditions check whether bits are on, and those are the only two
|
// conditions check whether bits are on, and those are the only two
|
// conditions checking those bits. Therefore, Vivado complains that
|
// conditions checking those bits. Therefore, Vivado complains that
|
// these two bits are redundant. Hence the convoluted expression
|
// these two bits are redundant. Hence the convoluted expression
|
// below, arriving at what we finally want in the (now wire net)
|
// below, arriving at what we finally want in the (now wire net)
|
// opF.
|
// op_F.
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (op_ce)
|
`ifdef OPT_PIPELINED
|
begin // Set the flag condition codes, bit order is [3:0]=VNCZ
|
if (op_ce) // Cannot do op_change_data_ce here since op_F depends
|
case(dcdF[2:0])
|
// upon being either correct for a valid op, or correct
|
3'h0: r_opF <= 6'h00; // Always
|
// for the last valid op
|
`ifdef OPT_NEW_INSTRUCTION_SET
|
|
// These were remapped as part of the new instruction
|
|
// set in order to make certain that the low order
|
|
// two bits contained the most commonly used
|
|
// conditions: Always, LT, Z, and NZ.
|
|
3'h1: r_opF <= 6'h24; // LT
|
|
3'h2: r_opF <= 6'h11; // Z
|
|
3'h3: r_opF <= 6'h10; // NE
|
|
3'h4: r_opF <= 6'h30; // GT (!N&!Z)
|
|
3'h5: r_opF <= 6'h20; // GE (!N)
|
|
`else
|
|
3'h1: r_opF <= 6'h11; // Z
|
|
3'h2: r_opF <= 6'h10; // NE
|
|
3'h3: r_opF <= 6'h20; // GE (!N)
|
|
3'h4: r_opF <= 6'h30; // GT (!N&!Z)
|
|
3'h5: r_opF <= 6'h24; // LT
|
|
`endif
|
`endif
|
3'h6: r_opF <= 6'h02; // C
|
begin // Set the flag condition codes, bit order is [3:0]=VNCZ
|
3'h7: r_opF <= 6'h08; // V
|
case(dcd_F[2:0])
|
|
3'h0: r_op_F <= 7'h00; // Always
|
|
3'h1: r_op_F <= 7'h11; // Z
|
|
3'h2: r_op_F <= 7'h44; // LT
|
|
3'h3: r_op_F <= 7'h22; // C
|
|
3'h4: r_op_F <= 7'h08; // V
|
|
3'h5: r_op_F <= 7'h10; // NE
|
|
3'h6: r_op_F <= 7'h40; // GE (!N)
|
|
3'h7: r_op_F <= 7'h20; // NC
|
endcase
|
endcase
|
end // Bit order is { (flags_not_used), VNCZ mask, VNCZ value }
|
end // Bit order is { (flags_not_used), VNCZ mask, VNCZ value }
|
assign opF = { r_opF[3], r_opF[5], r_opF[1], r_opF[4:0] };
|
assign op_F = { r_op_F[3], r_op_F[6:0] };
|
|
|
wire w_opvalid;
|
wire w_op_valid;
|
assign w_opvalid = (~clear_pipeline)&&(dcdvalid)&&(~dcd_ljmp);
|
assign w_op_valid = (~clear_pipeline)&&(dcd_valid)&&(~dcd_ljmp)&&(!dcd_early_branch);
|
initial opvalid = 1'b0;
|
initial op_valid = 1'b0;
|
initial opvalid_alu = 1'b0;
|
initial op_valid_alu = 1'b0;
|
initial opvalid_mem = 1'b0;
|
initial op_valid_mem = 1'b0;
|
initial opvalid_div = 1'b0;
|
initial op_valid_div = 1'b0;
|
initial opvalid_fpu = 1'b0;
|
initial op_valid_fpu = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (clear_pipeline)
|
begin
|
begin
|
opvalid <= 1'b0;
|
op_valid <= 1'b0;
|
opvalid_alu <= 1'b0;
|
op_valid_alu <= 1'b0;
|
opvalid_mem <= 1'b0;
|
op_valid_mem <= 1'b0;
|
|
op_valid_div <= 1'b0;
|
|
op_valid_fpu <= 1'b0;
|
end else if (op_ce)
|
end else if (op_ce)
|
begin
|
begin
|
// Do we have a valid instruction?
|
// Do we have a valid instruction?
|
// The decoder may vote to stall one of its
|
// The decoder may vote to stall one of its
|
// instructions based upon something we currently
|
// instructions based upon something we currently
|
// have in our queue. This instruction must then
|
// have in our queue. This instruction must then
|
// move forward, and get a stall cycle inserted.
|
// move forward, and get a stall cycle inserted.
|
// Hence, the test on dcd_stalled here. If we must
|
// Hence, the test on dcd_stalled here. If we must
|
// wait until our operands are valid, then we aren't
|
// wait until our operands are valid, then we aren't
|
// valid yet until then.
|
// valid yet until then.
|
opvalid<= w_opvalid;
|
op_valid<= (w_op_valid)||(dcd_illegal)&&(dcd_valid)||(dcd_early_branch);
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
op_valid_alu <= (w_op_valid)&&((dcd_ALU)||(dcd_illegal)
|
opvalid_alu <= ((dcdALU)||(dcd_illegal))&&(w_opvalid);
|
||(dcd_early_branch));
|
opvalid_mem <= (dcdM)&&(~dcd_illegal)&&(w_opvalid);
|
op_valid_mem <= (dcd_M)&&(~dcd_illegal)&&(w_op_valid);
|
opvalid_div <= (dcdDV)&&(~dcd_illegal)&&(w_opvalid);
|
op_valid_div <= (dcd_DIV)&&(~dcd_illegal)&&(w_op_valid);
|
opvalid_fpu <= (dcdFP)&&(~dcd_illegal)&&(w_opvalid);
|
op_valid_fpu <= (dcd_FP)&&(~dcd_illegal)&&(w_op_valid);
|
`else
|
end else if ((adf_ce_unconditional)||(mem_ce))
|
opvalid_alu <= (dcdALU)&&(w_opvalid);
|
begin
|
opvalid_mem <= (dcdM)&&(w_opvalid);
|
op_valid <= 1'b0;
|
opvalid_div <= (dcdDV)&&(w_opvalid);
|
op_valid_alu <= 1'b0;
|
opvalid_fpu <= (dcdFP)&&(w_opvalid);
|
op_valid_mem <= 1'b0;
|
`endif
|
op_valid_div <= 1'b0;
|
end else if ((clear_pipeline)||(alu_ce)||(mem_ce)||(div_ce)||(fpu_ce))
|
op_valid_fpu <= 1'b0;
|
begin
|
|
opvalid <= 1'b0;
|
|
opvalid_alu <= 1'b0;
|
|
opvalid_mem <= 1'b0;
|
|
opvalid_div <= 1'b0;
|
|
opvalid_fpu <= 1'b0;
|
|
end
|
end
|
|
|
// Here's part of our debug interface. When we recognize a break
|
// Here's part of our debug interface. When we recognize a break
|
// instruction, we set the op_break flag. That'll prevent this
|
// instruction, we set the op_break flag. That'll prevent this
|
// instruction from entering the ALU, and cause an interrupt before
|
// instruction from entering the ALU, and cause an interrupt before
|
// this instruction. Thus, returning to this code will cause the
|
// this instruction. Thus, returning to this code will cause the
|
// break to repeat and continue upon return. To get out of this
|
// break to repeat and continue upon return. To get out of this
|
// condition, replace the break instruction with what it is supposed
|
// condition, replace the break instruction with what it is supposed
|
// to be, step through it, and then replace it back. In this fashion,
|
// to be, step through it, and then replace it back. In this fashion,
|
// a debugger can step through code.
|
// a debugger can step through code.
|
// assign w_op_break = (dcd_break)&&(r_dcdI[15:0] == 16'h0001);
|
// assign w_op_break = (dcd_break)&&(r_dcd_I[15:0] == 16'h0001);
|
initial op_break = 1'b0;
|
`ifdef OPT_PIPELINED
|
|
reg r_op_break;
|
|
|
|
initial r_op_break = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst) op_break <= 1'b0;
|
if ((i_rst)||(clear_pipeline)) r_op_break <= 1'b0;
|
else if (op_ce) op_break <= (dcd_break);
|
else if (op_ce)
|
else if ((clear_pipeline)||(~opvalid))
|
r_op_break <= (dcd_break);
|
op_break <= 1'b0;
|
else if (!op_valid)
|
|
r_op_break <= 1'b0;
|
|
assign op_break = r_op_break;
|
|
`else
|
|
assign op_break = dcd_break;
|
|
`endif
|
|
|
`ifdef OPT_PIPELINED
|
`ifdef OPT_PIPELINED
|
generate
|
generate
|
if (IMPLEMENT_LOCK != 0)
|
if (IMPLEMENT_LOCK != 0)
|
begin
|
begin
|
reg r_op_lock, r_op_lock_stall;
|
reg r_op_lock;
|
|
|
initial r_op_lock_stall = 1'b0;
|
|
always @(posedge i_clk)
|
|
if (i_rst)
|
|
r_op_lock_stall <= 1'b0;
|
|
else
|
|
r_op_lock_stall <= (~opvalid)||(~op_lock)
|
|
||(~dcdvalid)||(~pf_valid);
|
|
|
|
assign op_lock_stall = r_op_lock_stall;
|
|
|
|
initial r_op_lock = 1'b0;
|
initial r_op_lock = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (clear_pipeline)
|
r_op_lock <= 1'b0;
|
r_op_lock <= 1'b0;
|
else if (op_ce)
|
else if (op_ce)
|
r_op_lock <= (dcd_lock)&&(~clear_pipeline);
|
r_op_lock <= (dcd_valid)&&(dcd_lock)&&(~clear_pipeline);
|
assign op_lock = r_op_lock;
|
assign op_lock = r_op_lock;
|
|
|
end else begin
|
end else begin
|
assign op_lock_stall = 1'b0;
|
|
assign op_lock = 1'b0;
|
assign op_lock = 1'b0;
|
end endgenerate
|
end endgenerate
|
|
|
`else
|
`else
|
assign op_lock_stall = 1'b0;
|
|
assign op_lock = 1'b0;
|
assign op_lock = 1'b0;
|
`endif
|
`endif
|
|
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
initial op_illegal = 1'b0;
|
initial op_illegal = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((i_rst)||(clear_pipeline))
|
if (clear_pipeline)
|
op_illegal <= 1'b0;
|
op_illegal <= 1'b0;
|
else if(op_ce)
|
else if(op_ce)
|
`ifdef OPT_PIPELINED
|
`ifdef OPT_PIPELINED
|
op_illegal <=(dcd_illegal)||((dcd_lock)&&(IMPLEMENT_LOCK == 0));
|
op_illegal <= (dcd_valid)&&((dcd_illegal)||((dcd_lock)&&(IMPLEMENT_LOCK == 0)));
|
`else
|
`else
|
op_illegal <= (dcd_illegal)||(dcd_lock);
|
op_illegal <= (dcd_valid)&&((dcd_illegal)||(dcd_lock));
|
`endif
|
`endif
|
|
else if(alu_ce)
|
|
op_illegal <= 1'b0;
|
`endif
|
`endif
|
|
|
// No generate on EARLY_BRANCHING here, since if EARLY_BRANCHING is not
|
// No generate on EARLY_BRANCHING here, since if EARLY_BRANCHING is not
|
// set, dcd_early_branch will simply be a wire connected to zero and
|
// set, dcd_early_branch will simply be a wire connected to zero and
|
// this logic should just optimize.
|
// this logic should just optimize.
|
|
`ifdef OPT_PIPELINED
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (op_ce)
|
if (op_ce)
|
begin
|
begin
|
opF_wr <= (dcdF_wr)&&((~dcdR_cc)||(~dcdR_wr))
|
op_wF <= (dcd_wF)&&((~dcd_Rcc)||(~dcd_wR))
|
|
&&(~dcd_early_branch)&&(~dcd_illegal);
|
|
op_wR <= (dcd_wR)&&(~dcd_early_branch)&&(~dcd_illegal);
|
|
end
|
|
`else
|
|
always @(posedge i_clk)
|
|
begin
|
|
op_wF <= (dcd_wF)&&((~dcd_Rcc)||(~dcd_wR))
|
&&(~dcd_early_branch)&&(~dcd_illegal);
|
&&(~dcd_early_branch)&&(~dcd_illegal);
|
opR_wr <= (dcdR_wr)&&(~dcd_early_branch)&&(~dcd_illegal);
|
op_wR <= (dcd_wR)&&(~dcd_early_branch)&&(~dcd_illegal);
|
end
|
end
|
|
`endif
|
|
|
|
`ifdef VERILATOR
|
|
`ifdef OPT_PIPELINED
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (op_ce)
|
if (op_change_data_ce)
|
|
begin
|
|
op_sim <= dcd_sim;
|
|
op_sim_immv <= dcd_sim_immv;
|
|
end
|
|
`else
|
|
always @(*)
|
begin
|
begin
|
opn <= dcdOp; // Which ALU operation?
|
op_sim = dcd_sim;
|
// opM <= dcdM; // Is this a memory operation?
|
op_sim_immv = dcd_sim_immv;
|
|
end
|
|
`endif
|
|
`endif
|
|
|
|
`ifdef OPT_PIPELINED
|
|
reg [3:0] r_op_opn;
|
|
reg [4:0] r_op_R;
|
|
reg r_op_Rcc;
|
|
reg r_op_gie;
|
|
always @(posedge i_clk)
|
|
if (op_change_data_ce)
|
|
begin
|
|
// Which ALU operation? Early branches are
|
|
// unimplemented moves
|
|
r_op_opn <= (dcd_early_branch) ? 4'hf : dcd_opn;
|
|
// opM <= dcd_M; // Is this a memory operation?
|
// What register will these results be written into?
|
// What register will these results be written into?
|
opR <= dcdR;
|
r_op_R <= dcd_R;
|
opR_cc <= (dcdR_cc)&&(dcdR_wr)&&(dcdR[4]==dcd_gie);
|
r_op_Rcc <= (dcd_Rcc)&&(dcd_wR)&&(dcd_R[4]==dcd_gie);
|
// User level (1), vs supervisor (0)/interrupts disabled
|
// User level (1), vs supervisor (0)/interrupts disabled
|
op_gie <= dcd_gie;
|
r_op_gie <= dcd_gie;
|
|
|
|
|
//
|
//
|
op_pc <= (dcd_early_branch)?dcd_branch_pc:dcd_pc;
|
op_pc <= (dcd_early_branch)?dcd_branch_pc:dcd_pc[AW:1];
|
end
|
end
|
assign opFl = (op_gie)?(w_uflags):(w_iflags);
|
assign op_opn = r_op_opn;
|
|
assign op_R = r_op_R;
|
|
`ifdef OPT_NO_USERMODE
|
|
assign op_gie = 1'b0;
|
|
`else
|
|
assign op_gie = r_op_gie;
|
|
`endif
|
|
assign op_Rcc = r_op_Rcc;
|
|
`else
|
|
assign op_opn = dcd_opn;
|
|
assign op_R = dcd_R;
|
|
`ifdef OPT_NO_USERMODE
|
|
assign op_gie = 1'b0;
|
|
`else
|
|
assign op_gie = dcd_gie;
|
|
`endif
|
|
// With no pipelining, there is no early branching. We keep it
|
|
always @(posedge i_clk)
|
|
op_pc <= (dcd_early_branch)?dcd_branch_pc:dcd_pc[AW:1];
|
|
`endif
|
|
assign op_Fl = (op_gie)?(w_uflags):(w_iflags);
|
|
|
`ifdef OPT_VLIW
|
`ifdef OPT_CIS
|
reg r_op_phase;
|
reg r_op_phase;
|
initial r_op_phase = 1'b0;
|
initial r_op_phase = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((i_rst)||(clear_pipeline))
|
if (clear_pipeline)
|
r_op_phase <= 1'b0;
|
r_op_phase <= 1'b0;
|
else if (op_ce)
|
else if (op_change_data_ce)
|
r_op_phase <= dcd_phase;
|
r_op_phase <= (dcd_phase)&&((!dcd_wR)||(!dcd_Rpc));
|
assign op_phase = r_op_phase;
|
assign op_phase = r_op_phase;
|
`else
|
`else
|
assign op_phase = 1'b0;
|
assign op_phase = 1'b0;
|
`endif
|
`endif
|
|
|
| Line 954... |
Line 1022... |
// op_stall wire, which would stall any upstream stage.
|
// op_stall wire, which would stall any upstream stage.
|
// We'll create a flag here to start our coordination. Once we
|
// We'll create a flag here to start our coordination. Once we
|
// define this flag to something other than just plain zero, then
|
// define this flag to something other than just plain zero, then
|
// the stalls will already be in place.
|
// the stalls will already be in place.
|
`ifdef OPT_PIPELINED
|
`ifdef OPT_PIPELINED
|
assign opA = ((wr_reg_ce)&&(wr_reg_id == opA_id)) // &&(opA_rd))
|
assign op_Av = ((wr_reg_ce)&&(wr_reg_id == op_Aid)) // &&(op_rA))
|
? wr_reg_vl : r_opA;
|
? wr_gpreg_vl : r_op_Av;
|
`else
|
`else
|
assign opA = r_opA;
|
assign op_Av = r_op_Av;
|
`endif
|
`endif
|
|
|
`ifdef OPT_PIPELINED
|
`ifdef OPT_PIPELINED
|
// Stall if we have decoded an instruction that will read register A
|
// Stall if we have decoded an instruction that will read register A
|
// AND ... something that may write a register is running
|
// AND ... something that may write a register is running
|
// AND (series of conditions here ...)
|
// AND (series of conditions here ...)
|
// The operation might set flags, and we wish to read the
|
// The operation might set flags, and we wish to read the
|
// CC register
|
// CC register
|
// OR ... (No other conditions)
|
// OR ... (No other conditions)
|
assign dcdA_stall = (dcdA_rd) // &&(dcdvalid) is checked for elsewhere
|
assign dcd_A_stall = (dcd_rA) // &&(dcd_valid) is checked for elsewhere
|
&&((opvalid)||(mem_rdbusy)
|
&&((op_valid)||(mem_rdbusy)
|
||(div_busy)||(fpu_busy))
|
||(div_busy)||(fpu_busy))
|
&&((opF_wr)&&(dcdA_cc));
|
&&(((op_wF)||(cc_invalid_for_dcd))&&(dcd_Acc))
|
|
||((dcd_rA)&&(dcd_Acc)&&(cc_invalid_for_dcd));
|
`else
|
`else
|
// There are no pipeline hazards, if we aren't pipelined
|
// There are no pipeline hazards, if we aren't pipelined
|
assign dcdA_stall = 1'b0;
|
assign dcd_A_stall = 1'b0;
|
`endif
|
`endif
|
|
|
`ifdef OPT_PIPELINED
|
`ifdef OPT_PIPELINED
|
assign opB = ((wr_reg_ce)&&(wr_reg_id == opB_id)&&(opB_rd))
|
assign op_Bv = ((wr_reg_ce)&&(wr_reg_id == op_Bid)&&(op_rB))
|
? wr_reg_vl: r_opB;
|
? wr_gpreg_vl: r_op_Bv;
|
`else
|
`else
|
assign opB = r_opB;
|
assign op_Bv = r_op_Bv;
|
`endif
|
`endif
|
|
|
`ifdef OPT_PIPELINED
|
`ifdef OPT_PIPELINED
|
// Stall if we have decoded an instruction that will read register B
|
// Stall if we have decoded an instruction that will read register B
|
// AND ... something that may write a (unknown) register is running
|
// AND ... something that may write a (unknown) register is running
|
// AND (series of conditions here ...)
|
// AND (series of conditions here ...)
|
// The operation might set flags, and we wish to read the
|
// The operation might set flags, and we wish to read the
|
// CC register
|
// CC register
|
// OR the operation might set register B, and we still need
|
// OR the operation might set register B, and we still need
|
// a clock to add the offset to it
|
// a clock to add the offset to it
|
assign dcdB_stall = (dcdB_rd) // &&(dcdvalid) is checked for elsewhere
|
assign dcd_B_stall = (dcd_rB) // &&(dcd_valid) is checked for elsewhere
|
// If the op stage isn't valid, yet something
|
// If the op stage isn't valid, yet something
|
// is running, then it must have been valid.
|
// is running, then it must have been valid.
|
// We'll use the last values from that stage
|
// We'll use the last values from that stage
|
// (opR_wr, opF_wr, opR) in our logic below.
|
// (op_wR, op_wF, op_R) in our logic below.
|
&&((opvalid)||(mem_rdbusy)
|
&&((op_valid)||(mem_rdbusy)
|
||(div_busy)||(fpu_busy)||(alu_busy))
|
||(div_busy)||(fpu_busy)||(alu_busy))
|
&&(
|
&&(
|
// Okay, what happens if the result register
|
// Okay, what happens if the result register
|
// from instruction 1 becomes the input for
|
// from instruction 1 becomes the input for
|
// instruction two, *and* there's an immediate
|
// instruction two, *and* there's an immediate
|
| Line 1017... |
Line 1086... |
// If we were piping, the pipe logic in the
|
// If we were piping, the pipe logic in the
|
// decode circuit has told us that the hazard
|
// decode circuit has told us that the hazard
|
// is clear, so we're okay then.
|
// is clear, so we're okay then.
|
//
|
//
|
((~dcd_zI)&&(
|
((~dcd_zI)&&(
|
((opR == dcdB)&&(opR_wr))
|
((op_R == dcd_B)&&(op_wR))
|
||((mem_rdbusy)&&(~dcd_pipe))
|
||((mem_rdbusy)&&(~dcd_pipe))
|
))
|
))
|
// Stall following any instruction that will
|
// Stall following any instruction that will
|
// set the flags, if we're going to need the
|
// set the flags, if we're going to need the
|
// flags (CC) register for opB.
|
// flags (CC) register for op_B.
|
||((opF_wr)&&(dcdB_cc))
|
||(((op_wF)||(cc_invalid_for_dcd))&&(dcd_Bcc))
|
// Stall on any ongoing memory operation that
|
// Stall on any ongoing memory operation that
|
// will write to opB -- captured above
|
// will write to op_B -- captured above
|
// ||((mem_busy)&&(~mem_we)&&(mem_last_reg==dcdB)&&(~dcd_zI))
|
// ||((mem_busy)&&(~mem_we)&&(mem_last_reg==dcd_B)&&(~dcd_zI))
|
);
|
)
|
assign dcdF_stall = ((~dcdF[3])
|
||((dcd_rB)&&(dcd_Bcc)&&(cc_invalid_for_dcd));
|
||((dcdA_rd)&&(dcdA_cc))
|
assign dcd_F_stall = ((~dcd_F[3])
|
||((dcdB_rd)&&(dcdB_cc)))
|
||((dcd_rA)&&(dcd_Acc))
|
&&(opvalid)&&(opR_cc);
|
||((dcd_rB)&&(dcd_Bcc)))
|
// &&(dcdvalid) is checked for elsewhere
|
&&(op_valid)&&(op_Rcc);
|
|
// &&(dcd_valid) is checked for elsewhere
|
`else
|
`else
|
// No stalls without pipelining, 'cause how can you have a pipeline
|
// No stalls without pipelining, 'cause how can you have a pipeline
|
// hazard without the pipeline?
|
// hazard without the pipeline?
|
assign dcdB_stall = 1'b0;
|
assign dcd_B_stall = 1'b0;
|
assign dcdF_stall = 1'b0;
|
assign dcd_F_stall = 1'b0;
|
`endif
|
`endif
|
//
|
//
|
//
|
//
|
// PIPELINE STAGE #4 :: Apply Instruction
|
// PIPELINE STAGE #4 :: Apply Instruction
|
//
|
//
|
//
|
//
|
`ifdef OPT_NEW_INSTRUCTION_SET
|
cpuops #(IMPLEMENT_MPY) doalu(i_clk, (clear_pipeline),
|
cpuops #(IMPLEMENT_MPY) doalu(i_clk, i_rst, alu_ce,
|
alu_ce, op_opn, op_Av, op_Bv,
|
(opvalid_alu), opn, opA, opB,
|
alu_result, alu_flags, alu_valid, alu_busy);
|
alu_result, alu_flags, alu_valid, alu_illegal_op,
|
|
alu_busy);
|
|
`else
|
|
cpuops_deprecated #(IMPLEMENT_MPY) doalu(i_clk, i_rst, alu_ce,
|
|
(opvalid_alu), opn, opA, opB,
|
|
alu_result, alu_flags, alu_valid, alu_illegal_op);
|
|
assign alu_busy = 1'b0;
|
|
`endif
|
|
|
|
generate
|
generate
|
if (IMPLEMENT_DIVIDE != 0)
|
if (IMPLEMENT_DIVIDE != 0)
|
begin
|
begin
|
div thedivide(i_clk, (i_rst)||(clear_pipeline), div_ce, opn[0],
|
div thedivide(i_clk, (clear_pipeline), div_ce, op_opn[0],
|
opA, opB, div_busy, div_valid, div_error, div_result,
|
op_Av, op_Bv, div_busy, div_valid, div_error, div_result,
|
div_flags);
|
div_flags);
|
end else begin
|
end else begin
|
assign div_error = 1'b1;
|
assign div_error = 1'b0; // Can't be high unless div_valid
|
assign div_busy = 1'b0;
|
assign div_busy = 1'b0;
|
assign div_valid = 1'b0;
|
assign div_valid = 1'b0;
|
assign div_result= 32'h00;
|
assign div_result= 32'h00;
|
assign div_flags = 4'h0;
|
assign div_flags = 4'h0;
|
end endgenerate
|
end endgenerate
|
| Line 1075... |
Line 1137... |
generate
|
generate
|
if (IMPLEMENT_FPU != 0)
|
if (IMPLEMENT_FPU != 0)
|
begin
|
begin
|
//
|
//
|
// sfpu thefpu(i_clk, i_rst, fpu_ce,
|
// sfpu thefpu(i_clk, i_rst, fpu_ce,
|
// opA, opB, fpu_busy, fpu_valid, fpu_err, fpu_result,
|
// op_Av, op_Bv, fpu_busy, fpu_valid, fpu_err, fpu_result,
|
// fpu_flags);
|
// fpu_flags);
|
//
|
//
|
assign fpu_error = 1'b1;
|
assign fpu_error = 1'b0; // Must only be true if fpu_valid
|
assign fpu_busy = 1'b0;
|
assign fpu_busy = 1'b0;
|
assign fpu_valid = 1'b0;
|
assign fpu_valid = 1'b0;
|
assign fpu_result= 32'h00;
|
assign fpu_result= 32'h00;
|
assign fpu_flags = 4'h0;
|
assign fpu_flags = 4'h0;
|
end else begin
|
end else begin
|
assign fpu_error = 1'b1;
|
assign fpu_error = 1'b0;
|
assign fpu_busy = 1'b0;
|
assign fpu_busy = 1'b0;
|
assign fpu_valid = 1'b0;
|
assign fpu_valid = 1'b0;
|
assign fpu_result= 32'h00;
|
assign fpu_result= 32'h00;
|
assign fpu_flags = 4'h0;
|
assign fpu_flags = 4'h0;
|
end endgenerate
|
end endgenerate
|
|
|
|
|
assign set_cond = ((opF[7:4]&opFl[3:0])==opF[3:0]);
|
assign set_cond = ((op_F[7:4]&op_Fl[3:0])==op_F[3:0]);
|
initial alF_wr = 1'b0;
|
initial alu_wF = 1'b0;
|
initial alu_wr = 1'b0;
|
initial alu_wR = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
begin
|
begin
|
alu_wr <= 1'b0;
|
alu_wR <= 1'b0;
|
alF_wr <= 1'b0;
|
alu_wF <= 1'b0;
|
end else if (alu_ce)
|
end else if (alu_ce)
|
begin
|
begin
|
// alu_reg <= opR;
|
// alu_reg <= op_R;
|
alu_wr <= (opR_wr)&&(set_cond);
|
alu_wR <= (op_wR)&&(set_cond);
|
alF_wr <= (opF_wr)&&(set_cond);
|
alu_wF <= (op_wF)&&(set_cond);
|
end else if (~alu_busy) begin
|
end else if (~alu_busy) begin
|
// These are strobe signals, so clear them if not
|
// These are strobe signals, so clear them if not
|
// set for any particular clock
|
// set for any particular clock
|
alu_wr <= (i_halt)&&(i_dbg_we);
|
alu_wR <= (i_halt)&&(i_dbg_we);
|
alF_wr <= 1'b0;
|
alu_wF <= 1'b0;
|
end
|
end
|
|
|
`ifdef OPT_VLIW
|
`ifdef OPT_CIS
|
reg r_alu_phase;
|
reg r_alu_phase;
|
initial r_alu_phase = 1'b0;
|
initial r_alu_phase = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
r_alu_phase <= 1'b0;
|
r_alu_phase <= 1'b0;
|
else if ((alu_ce)||(mem_ce)||(div_ce)||(fpu_ce))
|
else if ((adf_ce_unconditional)||(mem_ce))
|
r_alu_phase <= op_phase;
|
r_alu_phase <= op_phase;
|
assign alu_phase = r_alu_phase;
|
assign alu_phase = r_alu_phase;
|
`else
|
`else
|
assign alu_phase = 1'b0;
|
assign alu_phase = 1'b0;
|
`endif
|
`endif
|
|
|
|
`ifdef OPT_PIPELINED
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((alu_ce)||(div_ce)||(fpu_ce))
|
if (adf_ce_unconditional)
|
alu_reg <= opR;
|
alu_reg <= op_R;
|
else if ((i_halt)&&(i_dbg_we))
|
else if ((i_halt)&&(i_dbg_we))
|
alu_reg <= i_dbg_reg;
|
alu_reg <= i_dbg_reg;
|
|
`else
|
|
always @(posedge i_clk)
|
|
if ((i_halt)&&(i_dbg_we))
|
|
alu_reg <= i_dbg_reg;
|
|
else
|
|
alu_reg <= op_R;
|
|
`endif
|
|
|
//
|
//
|
// DEBUG Register write access starts here
|
// DEBUG Register write access starts here
|
//
|
//
|
reg dbgv;
|
reg dbgv;
|
initial dbgv = 1'b0;
|
initial dbgv = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
dbgv <= (~i_rst)&&(~alu_ce)&&((i_halt)&&(i_dbg_we));
|
dbgv <= (~i_rst)&&(i_halt)&&(i_dbg_we)&&(r_halted);
|
reg [31:0] dbg_val;
|
reg [31:0] dbg_val;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
dbg_val <= i_dbg_data;
|
dbg_val <= i_dbg_data;
|
|
`ifdef OPT_NO_USERMODE
|
|
assign alu_gie = 1'b0;
|
|
`else
|
|
`ifdef OPT_PIPELINED
|
|
reg r_alu_gie;
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((alu_ce)||(mem_ce))
|
if ((adf_ce_unconditional)||(mem_ce))
|
alu_gie <= op_gie;
|
r_alu_gie <= op_gie;
|
|
assign alu_gie = r_alu_gie;
|
|
`else
|
|
assign alu_gie = op_gie;
|
|
`endif
|
|
`endif
|
|
|
|
`ifdef OPT_PIPELINED
|
|
reg [(AW-1):0] r_alu_pc;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((alu_ce)||((master_ce)&&(opvalid_mem)&&(~clear_pipeline)
|
if ((adf_ce_unconditional)
|
|
||((master_ce)&&(op_valid_mem)&&(~clear_pipeline)
|
&&(~mem_stalled)))
|
&&(~mem_stalled)))
|
alu_pc <= op_pc;
|
r_alu_pc <= op_pc;
|
|
assign alu_pc = r_alu_pc;
|
|
`else
|
|
assign alu_pc = op_pc;
|
|
`endif
|
|
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
|
reg r_alu_illegal;
|
reg r_alu_illegal;
|
initial r_alu_illegal = 0;
|
initial r_alu_illegal = 0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (clear_pipeline)
|
if (clear_pipeline)
|
r_alu_illegal <= 1'b0;
|
r_alu_illegal <= 1'b0;
|
else if ((alu_ce)||(mem_ce))
|
else if (alu_ce)
|
r_alu_illegal <= op_illegal;
|
r_alu_illegal <= op_illegal;
|
assign alu_illegal = (alu_illegal_op)||(r_alu_illegal);
|
else
|
`endif
|
r_alu_illegal <= 1'b0;
|
|
assign alu_illegal = (r_alu_illegal);
|
|
|
initial r_alu_pc_valid = 1'b0;
|
initial r_alu_pc_valid = 1'b0;
|
initial mem_pc_valid = 1'b0;
|
initial mem_pc_valid = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (clear_pipeline)
|
r_alu_pc_valid <= 1'b0;
|
r_alu_pc_valid <= 1'b0;
|
else if (alu_ce) // Includes && (~alu_clear_pipeline)
|
else if ((adf_ce_unconditional)&&(!op_phase)) //Includes&&(~alu_clear_pipeline)
|
r_alu_pc_valid <= 1'b1;
|
r_alu_pc_valid <= 1'b1;
|
else if ((~alu_busy)||(clear_pipeline))
|
else if (((~alu_busy)&&(~div_busy)&&(~fpu_busy))||(clear_pipeline))
|
r_alu_pc_valid <= 1'b0;
|
r_alu_pc_valid <= 1'b0;
|
assign alu_pc_valid = (r_alu_pc_valid)&&(~alu_busy);
|
assign alu_pc_valid = (r_alu_pc_valid)&&((~alu_busy)&&(~div_busy)&&(~fpu_busy));
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
mem_pc_valid <= 1'b0;
|
mem_pc_valid <= 1'b0;
|
else
|
else
|
mem_pc_valid <= (mem_ce);
|
mem_pc_valid <= (mem_ce);
|
| Line 1181... |
Line 1270... |
wire bus_lock;
|
wire bus_lock;
|
`ifdef OPT_PIPELINED
|
`ifdef OPT_PIPELINED
|
generate
|
generate
|
if (IMPLEMENT_LOCK != 0)
|
if (IMPLEMENT_LOCK != 0)
|
begin
|
begin
|
|
reg r_prelock_stall;
|
|
|
|
initial r_prelock_stall = 1'b0;
|
|
always @(posedge i_clk)
|
|
if (clear_pipeline)
|
|
r_prelock_stall <= 1'b0;
|
|
else if ((op_valid)&&(op_lock)&&(op_ce))
|
|
r_prelock_stall <= 1'b1;
|
|
else if ((op_valid)&&(dcd_valid)&&(pf_valid))
|
|
r_prelock_stall <= 1'b0;
|
|
|
|
assign prelock_stall = r_prelock_stall;
|
|
|
|
reg r_prelock_primed;
|
|
always @(posedge i_clk)
|
|
if (clear_pipeline)
|
|
r_prelock_primed <= 1'b0;
|
|
else if (r_prelock_stall)
|
|
r_prelock_primed <= 1'b1;
|
|
else if ((adf_ce_unconditional)||(mem_ce))
|
|
r_prelock_primed <= 1'b0;
|
|
|
reg [1:0] r_bus_lock;
|
reg [1:0] r_bus_lock;
|
initial r_bus_lock = 2'b00;
|
initial r_bus_lock = 2'b00;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (clear_pipeline)
|
r_bus_lock <= 2'b00;
|
r_bus_lock <= 2'b00;
|
else if ((op_ce)&&(op_lock))
|
else if ((op_valid)&&((adf_ce_unconditional)||(mem_ce)))
|
r_bus_lock <= 2'b11;
|
begin
|
else if ((|r_bus_lock)&&((~opvalid_mem)||(~op_ce)))
|
if (r_prelock_primed)
|
|
r_bus_lock <= 2'b10;
|
|
else if (r_bus_lock != 2'h0)
|
r_bus_lock <= r_bus_lock + 2'b11;
|
r_bus_lock <= r_bus_lock + 2'b11;
|
|
end
|
assign bus_lock = |r_bus_lock;
|
assign bus_lock = |r_bus_lock;
|
end else begin
|
end else begin
|
|
assign prelock_stall = 1'b0;
|
assign bus_lock = 1'b0;
|
assign bus_lock = 1'b0;
|
end endgenerate
|
end endgenerate
|
`else
|
`else
|
assign bus_lock = 1'b0;
|
assign bus_lock = 1'b0;
|
`endif
|
`endif
|
|
|
`ifdef OPT_PIPELINED_BUS_ACCESS
|
`ifdef OPT_PIPELINED_BUS_ACCESS
|
pipemem #(AW,IMPLEMENT_LOCK) domem(i_clk, i_rst,(mem_ce)&&(set_cond), bus_lock,
|
pipemem #(AW,IMPLEMENT_LOCK) domem(i_clk, i_rst,(mem_ce)&&(set_cond), bus_lock,
|
(opn[0]), opB, opA, opR,
|
(op_opn[2:0]), op_Bv, op_Av, op_R,
|
mem_busy, mem_pipe_stalled,
|
mem_busy, mem_pipe_stalled,
|
mem_valid, bus_err, mem_wreg, mem_result,
|
mem_valid, bus_err, mem_wreg, mem_result,
|
mem_cyc_gbl, mem_cyc_lcl,
|
mem_cyc_gbl, mem_cyc_lcl,
|
mem_stb_gbl, mem_stb_lcl,
|
mem_stb_gbl, mem_stb_lcl,
|
mem_we, mem_addr, mem_data,
|
mem_we, mem_addr, mem_data, mem_sel,
|
mem_ack, mem_stall, mem_err, i_wb_data);
|
mem_ack, mem_stall, mem_err, i_wb_data);
|
|
|
`else // PIPELINED_BUS_ACCESS
|
`else // PIPELINED_BUS_ACCESS
|
memops #(AW,IMPLEMENT_LOCK) domem(i_clk, i_rst,(mem_ce)&&(set_cond), bus_lock,
|
memops #(AW,IMPLEMENT_LOCK,WITH_LOCAL_BUS) domem(i_clk, i_rst,(mem_ce)&&(set_cond), bus_lock,
|
(opn[0]), opB, opA, opR,
|
(op_opn[2:0]), op_Bv, op_Av, op_R,
|
mem_busy,
|
mem_busy,
|
mem_valid, bus_err, mem_wreg, mem_result,
|
mem_valid, bus_err, mem_wreg, mem_result,
|
mem_cyc_gbl, mem_cyc_lcl,
|
mem_cyc_gbl, mem_cyc_lcl,
|
mem_stb_gbl, mem_stb_lcl,
|
mem_stb_gbl, mem_stb_lcl,
|
mem_we, mem_addr, mem_data,
|
mem_we, mem_addr, mem_data, mem_sel,
|
mem_ack, mem_stall, mem_err, i_wb_data);
|
mem_ack, mem_stall, mem_err, i_wb_data);
|
|
assign mem_pipe_stalled = 1'b0;
|
`endif // PIPELINED_BUS_ACCESS
|
`endif // PIPELINED_BUS_ACCESS
|
assign mem_rdbusy = ((mem_busy)&&(~mem_we));
|
assign mem_rdbusy = ((mem_busy)&&(~mem_we));
|
|
|
// Either the prefetch or the instruction gets the memory bus, but
|
// Either the prefetch or the instruction gets the memory bus, but
|
// never both.
|
// never both.
|
wbdblpriarb #(32,AW) pformem(i_clk, i_rst,
|
wbdblpriarb #(32,AW) pformem(i_clk, i_rst,
|
// Memory access to the arbiter, priority position
|
// Memory access to the arbiter, priority position
|
mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl,
|
mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl,
|
mem_we, mem_addr, mem_data, mem_ack, mem_stall, mem_err,
|
mem_we, mem_addr, mem_data, mem_sel,
|
|
mem_ack, mem_stall, mem_err,
|
// Prefetch access to the arbiter
|
// Prefetch access to the arbiter
|
pf_cyc, 1'b0, pf_stb, 1'b0, pf_we, pf_addr, pf_data,
|
//
|
|
// At a first glance, we might want something like:
|
|
//
|
|
// pf_cyc, 1'b0, pf_stb, 1'b0, pf_we, pf_addr, pf_data, 4'hf,
|
|
//
|
|
// However, we know that the prefetch will not generate any
|
|
// writes. Therefore, the write specific lines (mem_data and
|
|
// mem_sel) can be shared with the memory in order to ease
|
|
// timing and LUT usage.
|
|
pf_cyc,1'b0,pf_stb, 1'b0, pf_we, pf_addr, mem_data, mem_sel,
|
pf_ack, pf_stall, pf_err,
|
pf_ack, pf_stall, pf_err,
|
// Common wires, in and out, of the arbiter
|
// Common wires, in and out, of the arbiter
|
o_wb_gbl_cyc, o_wb_lcl_cyc, o_wb_gbl_stb, o_wb_lcl_stb,
|
o_wb_gbl_cyc, o_wb_lcl_cyc, o_wb_gbl_stb, o_wb_lcl_stb,
|
o_wb_we, o_wb_addr, o_wb_data,
|
o_wb_we, o_wb_addr, o_wb_data, o_wb_sel,
|
i_wb_ack, i_wb_stall, i_wb_err);
|
i_wb_ack, i_wb_stall, i_wb_err);
|
|
|
|
|
|
|
//
|
//
|
| Line 1258... |
Line 1384... |
//
|
//
|
// Write back to our generic register set ...
|
// Write back to our generic register set ...
|
// When shall we write back? On one of two conditions
|
// When shall we write back? On one of two conditions
|
// Note that the flags needed to be checked before issuing the
|
// Note that the flags needed to be checked before issuing the
|
// bus instruction, so they don't need to be checked here.
|
// bus instruction, so they don't need to be checked here.
|
// Further, alu_wr includes (set_cond), so we don't need to
|
// Further, alu_wR includes (set_cond), so we don't need to
|
// check for that here either.
|
// check for that here either.
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
assign wr_reg_ce = (dbgv)||(mem_valid)
|
assign wr_reg_ce = (dbgv)||(~alu_illegal)&&
|
||((~clear_pipeline)&&(~alu_illegal)
|
(((alu_wr)&&(~clear_pipeline)
|
&&(((alu_wR)&&(alu_valid))
|
&&((alu_valid)||(div_valid)||(fpu_valid)))
|
||(div_valid)||(fpu_valid)));
|
||(mem_valid));
|
|
`else
|
|
assign wr_reg_ce = (dbgv)||((alu_wr)&&(~clear_pipeline))||(mem_valid)||(div_valid)||(fpu_valid);
|
|
`endif
|
|
// Which register shall be written?
|
// Which register shall be written?
|
// COULD SIMPLIFY THIS: by adding three bits to these registers,
|
// COULD SIMPLIFY THIS: by adding three bits to these registers,
|
// One or PC, one for CC, and one for GIE match
|
// One or PC, one for CC, and one for GIE match
|
// Note that the alu_reg is the register to write on a divide or
|
// Note that the alu_reg is the register to write on a divide or
|
// FPU operation.
|
// FPU operation.
|
assign wr_reg_id = (alu_wr)?alu_reg:mem_wreg;
|
`ifdef OPT_NO_USERMODE
|
|
assign wr_reg_id[3:0] = (alu_wR|div_valid|fpu_valid)
|
|
? alu_reg[3:0]:mem_wreg[3:0];
|
|
assign wr_reg_id[4] = 1'b0;
|
|
`else
|
|
assign wr_reg_id = (alu_wR|div_valid|fpu_valid)?alu_reg:mem_wreg;
|
|
`endif
|
|
|
// Are we writing to the CC register?
|
// Are we writing to the CC register?
|
assign wr_write_cc = (wr_reg_id[3:0] == `CPU_CC_REG);
|
assign wr_write_cc = (wr_reg_id[3:0] == `CPU_CC_REG);
|
|
assign wr_write_scc = (wr_reg_id[4:0] == {1'b0, `CPU_CC_REG});
|
|
assign wr_write_ucc = (wr_reg_id[4:0] == {1'b1, `CPU_CC_REG});
|
// Are we writing to the PC?
|
// Are we writing to the PC?
|
assign wr_write_pc = (wr_reg_id[3:0] == `CPU_PC_REG);
|
assign wr_write_pc = (wr_reg_id[3:0] == `CPU_PC_REG);
|
|
|
// What value to write?
|
// What value to write?
|
assign wr_reg_vl = ((mem_valid) ? mem_result
|
assign wr_gpreg_vl = ((mem_valid) ? mem_result
|
:((div_valid|fpu_valid))
|
:((div_valid|fpu_valid))
|
? ((div_valid) ? div_result:fpu_result)
|
? ((div_valid) ? div_result:fpu_result)
|
:((dbgv) ? dbg_val : alu_result));
|
:((dbgv) ? dbg_val : alu_result));
|
|
assign wr_spreg_vl = ((mem_valid) ? mem_result
|
|
:((dbgv) ? dbg_val : alu_result));
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (wr_reg_ce)
|
if (wr_reg_ce)
|
regset[wr_reg_id] <= wr_reg_vl;
|
`ifdef OPT_NO_USERMODE
|
|
regset[wr_reg_id[3:0]] <= wr_gpreg_vl;
|
|
`else
|
|
regset[wr_reg_id] <= wr_gpreg_vl;
|
|
`endif
|
|
|
//
|
//
|
// Write back to the condition codes/flags register ...
|
// Write back to the condition codes/flags register ...
|
// When shall we write to our flags register? alF_wr already
|
// When shall we write to our flags register? alu_wF already
|
// includes the set condition ...
|
// includes the set condition ...
|
assign wr_flags_ce = ((alF_wr)||(div_valid)||(fpu_valid))&&(~clear_pipeline)&&(~alu_illegal);
|
assign wr_flags_ce = ((alu_wF)||(div_valid)||(fpu_valid))&&(~clear_pipeline)&&(~alu_illegal);
|
assign w_uflags = { uhalt_phase, ufpu_err_flag,
|
assign w_uflags = { 1'b0, uhalt_phase, ufpu_err_flag,
|
udiv_err_flag, ubus_err_flag, trap, ill_err_u,
|
udiv_err_flag, ubus_err_flag, trap, ill_err_u,
|
1'b0, step, 1'b1, sleep,
|
ubreak, step, 1'b1, sleep,
|
((wr_flags_ce)&&(alu_gie))?alu_flags:flags };
|
((wr_flags_ce)&&(alu_gie))?alu_flags:flags };
|
assign w_iflags = { ihalt_phase, ifpu_err_flag,
|
assign w_iflags = { 1'b0, ihalt_phase, ifpu_err_flag,
|
idiv_err_flag, ibus_err_flag, trap, ill_err_i,
|
idiv_err_flag, ibus_err_flag, trap, ill_err_i,
|
break_en, 1'b0, 1'b0, sleep,
|
break_en, 1'b0, 1'b0, sleep,
|
((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags };
|
((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags };
|
|
|
|
|
// What value to write?
|
// What value to write?
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
// If explicitly writing the register itself
|
// If explicitly writing the register itself
|
if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_cc))
|
if ((wr_reg_ce)&&(wr_write_ucc))
|
flags <= wr_reg_vl[3:0];
|
flags <= wr_gpreg_vl[3:0];
|
// Otherwise if we're setting the flags from an ALU operation
|
// Otherwise if we're setting the flags from an ALU operation
|
else if ((wr_flags_ce)&&(alu_gie))
|
else if ((wr_flags_ce)&&(alu_gie))
|
flags <= (div_valid)?div_flags:((fpu_valid)?fpu_flags
|
flags <= (div_valid)?div_flags:((fpu_valid)?fpu_flags
|
: alu_flags);
|
: alu_flags);
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
|
if ((wr_reg_ce)&&(wr_write_scc))
|
iflags <= wr_reg_vl[3:0];
|
iflags <= wr_gpreg_vl[3:0];
|
else if ((wr_flags_ce)&&(~alu_gie))
|
else if ((wr_flags_ce)&&(~alu_gie))
|
iflags <= (div_valid)?div_flags:((fpu_valid)?fpu_flags
|
iflags <= (div_valid)?div_flags:((fpu_valid)?fpu_flags
|
: alu_flags);
|
: alu_flags);
|
|
|
// The 'break' enable bit. This bit can only be set from supervisor
|
// The 'break' enable bit. This bit can only be set from supervisor
|
| Line 1329... |
Line 1467... |
// not execute the break instruction, choosing instead to enter into
|
// not execute the break instruction, choosing instead to enter into
|
// either interrupt mode or halt first.
|
// either interrupt mode or halt first.
|
// if ((break_en) AND (break_instruction)) // user mode or not
|
// if ((break_en) AND (break_instruction)) // user mode or not
|
// HALT CPU
|
// HALT CPU
|
// else if (break_instruction) // only in user mode
|
// else if (break_instruction) // only in user mode
|
// set an interrupt flag, go to supervisor mode
|
// set an interrupt flag, set the user break bit,
|
// allow supervisor to step the CPU.
|
// go to supervisor mode, allow supervisor to step the CPU.
|
// Upon a CPU halt, any break condition will be reset. The
|
// Upon a CPU halt, any break condition will be reset. The
|
// external debugger will then need to deal with whatever
|
// external debugger will then need to deal with whatever
|
// condition has taken place.
|
// condition has taken place.
|
initial break_en = 1'b0;
|
initial break_en = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((i_rst)||(i_halt))
|
if ((i_rst)||(i_halt))
|
break_en <= 1'b0;
|
break_en <= 1'b0;
|
else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
|
else if ((wr_reg_ce)&&(wr_write_scc))
|
break_en <= wr_reg_vl[`CPU_BREAK_BIT];
|
break_en <= wr_spreg_vl[`CPU_BREAK_BIT];
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
|
assign o_break = ((break_en)||(~op_gie))&&(op_break)
|
`ifdef OPT_PIPELINED
|
&&(~alu_valid)&&(~mem_valid)&&(~mem_busy)
|
reg r_break_pending;
|
&&(~div_busy)&&(~fpu_busy)
|
|
&&(~clear_pipeline)
|
initial r_break_pending = 1'b0;
|
||((~alu_gie)&&(bus_err))
|
always @(posedge i_clk)
|
||((~alu_gie)&&(div_valid)&&(div_error))
|
if ((clear_pipeline)||(~op_valid))
|
||((~alu_gie)&&(fpu_valid)&&(fpu_error))
|
r_break_pending <= 1'b0;
|
||((~alu_gie)&&(alu_pc_valid)&&(alu_illegal));
|
else if (op_break)
|
`else
|
r_break_pending <= (~alu_busy)&&(~div_busy)&&(~fpu_busy)&&(~mem_busy)&&(!wr_reg_ce);
|
assign o_break = (((break_en)||(~op_gie))&&(op_break)
|
else
|
&&(~alu_valid)&&(~mem_valid)&&(~mem_busy)
|
r_break_pending <= 1'b0;
|
&&(~clear_pipeline))
|
assign break_pending = r_break_pending;
|
||((~alu_gie)&&(bus_err))
|
`else
|
||((~alu_gie)&&(div_valid)&&(div_error))
|
assign break_pending = op_break;
|
||((~alu_gie)&&(fpu_valid)&&(fpu_error));
|
|
`endif
|
`endif
|
|
|
|
|
|
assign o_break = ((break_en)||(~op_gie))&&(break_pending)
|
|
&&(~clear_pipeline)
|
|
||((~alu_gie)&&(bus_err))
|
|
||((~alu_gie)&&(div_error))
|
|
||((~alu_gie)&&(fpu_error))
|
|
||((~alu_gie)&&(alu_illegal)&&(!clear_pipeline));
|
|
|
// The sleep register. Setting the sleep register causes the CPU to
|
// The sleep register. Setting the sleep register causes the CPU to
|
// sleep until the next interrupt. Setting the sleep register within
|
// sleep until the next interrupt. Setting the sleep register within
|
// interrupt mode causes the processor to halt until a reset. This is
|
// interrupt mode causes the processor to halt until a reset. This is
|
// a panic/fault halt. The trick is that you cannot be allowed to
|
// a panic/fault halt. The trick is that you cannot be allowed to
|
// set the sleep bit and switch to supervisor mode in the same
|
// set the sleep bit and switch to supervisor mode in the same
|
// instruction: users are not allowed to halt the CPU.
|
// instruction: users are not allowed to halt the CPU.
|
|
initial sleep = 1'b0;
|
|
`ifdef OPT_NO_USERMODE
|
|
reg r_sleep_is_halt;
|
|
initial r_sleep_is_halt = 1'b0;
|
|
always @(posedge i_clk)
|
|
if (i_rst)
|
|
r_sleep_is_halt <= 1'b0;
|
|
else if ((wr_reg_ce)&&(wr_write_cc)
|
|
&&(wr_spreg_vl[`CPU_SLEEP_BIT])
|
|
&&(~wr_spreg_vl[`CPU_GIE_BIT]))
|
|
r_sleep_is_halt <= 1'b1;
|
|
|
|
// Trying to switch to user mode, either via a WAIT or an RTU
|
|
// instruction will cause the CPU to sleep until an interrupt, in
|
|
// the NO-USERMODE build.
|
|
always @(posedge i_clk)
|
|
if ((i_rst)||((i_interrupt)&&(!r_sleep_is_halt)))
|
|
sleep <= 1'b0;
|
|
else if ((wr_reg_ce)&&(wr_write_cc)
|
|
&&(wr_spreg_vl[`CPU_GIE_BIT]))
|
|
sleep <= 1'b1;
|
|
`else
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((i_rst)||(w_switch_to_interrupt))
|
if ((i_rst)||(w_switch_to_interrupt))
|
sleep <= 1'b0;
|
sleep <= 1'b0;
|
else if ((wr_reg_ce)&&(wr_write_cc)&&(~alu_gie))
|
else if ((wr_reg_ce)&&(wr_write_cc)&&(~alu_gie))
|
// In supervisor mode, we have no protections. The
|
// In supervisor mode, we have no protections. The
|
// supervisor can set the sleep bit however he wants.
|
// supervisor can set the sleep bit however he wants.
|
// Well ... not quite. Switching to user mode and
|
// Well ... not quite. Switching to user mode and
|
// sleep mode shouold only be possible if the interrupt
|
// sleep mode shouold only be possible if the interrupt
|
// flag isn't set.
|
// flag isn't set.
|
// Thus: if (i_interrupt)&&(wr_reg_vl[GIE])
|
// Thus: if (i_interrupt)&&(wr_spreg_vl[GIE])
|
// don't set the sleep bit
|
// don't set the sleep bit
|
// otherwise however it would o.w. be set
|
// otherwise however it would o.w. be set
|
sleep <= (wr_reg_vl[`CPU_SLEEP_BIT])
|
sleep <= (wr_spreg_vl[`CPU_SLEEP_BIT])
|
&&((~i_interrupt)||(~wr_reg_vl[`CPU_GIE_BIT]));
|
&&((~i_interrupt)||(~wr_spreg_vl[`CPU_GIE_BIT]));
|
else if ((wr_reg_ce)&&(wr_write_cc)&&(wr_reg_vl[`CPU_GIE_BIT]))
|
else if ((wr_reg_ce)&&(wr_write_cc)&&(wr_spreg_vl[`CPU_GIE_BIT]))
|
// In user mode, however, you can only set the sleep
|
// In user mode, however, you can only set the sleep
|
// mode while remaining in user mode. You can't switch
|
// mode while remaining in user mode. You can't switch
|
// to sleep mode *and* supervisor mode at the same
|
// to sleep mode *and* supervisor mode at the same
|
// time, lest you halt the CPU.
|
// time, lest you halt the CPU.
|
sleep <= wr_reg_vl[`CPU_SLEEP_BIT];
|
sleep <= wr_spreg_vl[`CPU_SLEEP_BIT];
|
|
`endif
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((i_rst)||(w_switch_to_interrupt))
|
if (i_rst)
|
step <= 1'b0;
|
|
else if ((wr_reg_ce)&&(~alu_gie)&&(wr_reg_id[4])&&(wr_write_cc))
|
|
step <= wr_reg_vl[`CPU_STEP_BIT];
|
|
else if (((alu_pc_valid)||(mem_pc_valid))&&(step)&&(gie))
|
|
step <= 1'b0;
|
step <= 1'b0;
|
|
else if ((wr_reg_ce)&&(~alu_gie)&&(wr_write_ucc))
|
|
step <= wr_spreg_vl[`CPU_STEP_BIT];
|
|
|
// The GIE register. Only interrupts can disable the interrupt register
|
// The GIE register. Only interrupts can disable the interrupt register
|
|
`ifdef OPT_NO_USERMODE
|
|
assign w_switch_to_interrupt = 1'b0;
|
|
assign w_release_from_interrupt = 1'b0;
|
|
`else
|
assign w_switch_to_interrupt = (gie)&&(
|
assign w_switch_to_interrupt = (gie)&&(
|
// On interrupt (obviously)
|
// On interrupt (obviously)
|
((i_interrupt)&&(~alu_phase)&&(~bus_lock))
|
((i_interrupt)&&(~alu_phase)&&(~bus_lock))
|
// If we are stepping the CPU
|
// If we are stepping the CPU
|
||(((alu_pc_valid)||(mem_pc_valid))&&(step)&&(~alu_phase)&&(~bus_lock))
|
||(((alu_pc_valid)||(mem_pc_valid))&&(step)&&(~alu_phase)&&(~bus_lock))
|
// If we encounter a break instruction, if the break
|
// If we encounter a break instruction, if the break
|
// enable isn't set.
|
// enable isn't set.
|
||((master_ce)&&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy)
|
||((master_ce)&&(break_pending)&&(~break_en))
|
&&(op_break)&&(~break_en))
|
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
|
// On an illegal instruction
|
// On an illegal instruction
|
||((alu_pc_valid)&&(alu_illegal))
|
||((alu_illegal)&&(!clear_pipeline))
|
`endif
|
|
// On division by zero. If the divide isn't
|
// On division by zero. If the divide isn't
|
// implemented, div_valid and div_error will be short
|
// implemented, div_valid and div_error will be short
|
// circuited and that logic will be bypassed
|
// circuited and that logic will be bypassed
|
||((div_valid)&&(div_error))
|
||(div_error)
|
// Same thing on a floating point error.
|
// Same thing on a floating point error. Note that
|
||((fpu_valid)&&(fpu_error))
|
// fpu_error must *never* be set unless fpu_valid is
|
|
// also set as well, else this will fail.
|
|
||(fpu_error)
|
//
|
//
|
||(bus_err)
|
||(bus_err)
|
// If we write to the CC register
|
// If we write to the CC register
|
||((wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT])
|
||((wr_reg_ce)&&(~wr_spreg_vl[`CPU_GIE_BIT])
|
&&(wr_reg_id[4])&&(wr_write_cc))
|
&&(wr_reg_id[4])&&(wr_write_cc))
|
);
|
);
|
assign w_release_from_interrupt = (~gie)&&(~i_interrupt)
|
assign w_release_from_interrupt = (~gie)&&(~i_interrupt)
|
// Then if we write the CC register
|
// Then if we write the sCC register
|
&&(((wr_reg_ce)&&(wr_reg_vl[`CPU_GIE_BIT])
|
&&(((wr_reg_ce)&&(wr_spreg_vl[`CPU_GIE_BIT])
|
&&(~wr_reg_id[4])&&(wr_write_cc))
|
&&(wr_write_scc))
|
);
|
);
|
|
`endif
|
|
|
|
`ifdef OPT_NO_USERMODE
|
|
assign gie = 1'b0;
|
|
`else
|
|
reg r_gie;
|
|
|
|
initial r_gie = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
gie <= 1'b0;
|
r_gie <= 1'b0;
|
else if (w_switch_to_interrupt)
|
else if (w_switch_to_interrupt)
|
gie <= 1'b0;
|
r_gie <= 1'b0;
|
else if (w_release_from_interrupt)
|
else if (w_release_from_interrupt)
|
gie <= 1'b1;
|
r_gie <= 1'b1;
|
|
assign gie = r_gie;
|
|
`endif
|
|
|
initial trap = 1'b0;
|
`ifdef OPT_NO_USERMODE
|
|
assign trap = 1'b0;
|
|
assign ubreak = 1'b0;
|
|
`else
|
|
reg r_trap;
|
|
|
|
initial r_trap = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if ((i_rst)||(w_release_from_interrupt))
|
trap <= 1'b0;
|
r_trap <= 1'b0;
|
else if (w_release_from_interrupt)
|
else if ((alu_gie)&&(wr_reg_ce)&&(~wr_spreg_vl[`CPU_GIE_BIT])
|
trap <= 1'b0;
|
&&(wr_write_ucc)) // &&(wr_reg_id[4]) implied
|
else if ((alu_gie)&&(wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT])
|
r_trap <= 1'b1;
|
&&(wr_write_cc)) // &&(wr_reg_id[4]) implied
|
else if ((wr_reg_ce)&&(wr_write_ucc)&&(~alu_gie))
|
trap <= 1'b1;
|
r_trap <= (r_trap)&&(wr_spreg_vl[`CPU_TRAP_BIT]);
|
else if ((wr_reg_ce)&&(wr_write_cc)&&(wr_reg_id[4]))
|
|
trap <= wr_reg_vl[`CPU_TRAP_BIT];
|
reg r_ubreak;
|
|
|
|
initial r_ubreak = 1'b0;
|
|
always @(posedge i_clk)
|
|
if ((i_rst)||(w_release_from_interrupt))
|
|
r_ubreak <= 1'b0;
|
|
else if ((op_gie)&&(break_pending)&&(w_switch_to_interrupt))
|
|
r_ubreak <= 1'b1;
|
|
else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)&&(wr_write_ucc))
|
|
r_ubreak <= (ubreak)&&(wr_spreg_vl[`CPU_BREAK_BIT]);
|
|
|
|
assign trap = r_trap;
|
|
assign ubreak = r_ubreak;
|
|
`endif
|
|
|
|
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
initial ill_err_i = 1'b0;
|
initial ill_err_i = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
ill_err_i <= 1'b0;
|
ill_err_i <= 1'b0;
|
// Only the debug interface can clear this bit
|
// Only the debug interface can clear this bit
|
else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
|
else if ((dbgv)&&(wr_write_scc))
|
&&(~wr_reg_vl[`CPU_ILL_BIT]))
|
ill_err_i <= (ill_err_i)&&(wr_spreg_vl[`CPU_ILL_BIT]);
|
ill_err_i <= 1'b0;
|
else if ((alu_illegal)&&(~alu_gie)&&(!clear_pipeline))
|
else if ((alu_pc_valid)&&(alu_illegal)&&(~alu_gie))
|
|
ill_err_i <= 1'b1;
|
ill_err_i <= 1'b1;
|
initial ill_err_u = 1'b0;
|
|
|
`ifdef OPT_NO_USERMODE
|
|
assign ill_err_u = 1'b0;
|
|
`else
|
|
reg r_ill_err_u;
|
|
|
|
initial r_ill_err_u = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
|
ill_err_u <= 1'b0;
|
|
// The bit is automatically cleared on release from interrupt
|
// The bit is automatically cleared on release from interrupt
|
else if (w_release_from_interrupt)
|
// or reset
|
ill_err_u <= 1'b0;
|
if ((i_rst)||(w_release_from_interrupt))
|
// If the supervisor writes to this register, clearing the
|
r_ill_err_u <= 1'b0;
|
// bit, then clear it
|
// If the supervisor (or debugger) writes to this register,
|
else if (((~alu_gie)||(dbgv))
|
// clearing the bit, then clear it
|
&&(wr_reg_ce)&&(~wr_reg_vl[`CPU_ILL_BIT])
|
else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)&&(wr_write_ucc))
|
&&(wr_reg_id[4])&&(wr_write_cc))
|
r_ill_err_u <=((ill_err_u)&&(wr_spreg_vl[`CPU_ILL_BIT]));
|
ill_err_u <= 1'b0;
|
else if ((alu_illegal)&&(alu_gie)&&(!clear_pipeline))
|
else if ((alu_pc_valid)&&(alu_illegal)&&(alu_gie))
|
r_ill_err_u <= 1'b1;
|
ill_err_u <= 1'b1;
|
|
|
assign ill_err_u = r_ill_err_u;
|
|
`endif
|
`else
|
`else
|
assign ill_err_u = 1'b0;
|
assign ill_err_u = 1'b0;
|
assign ill_err_i = 1'b0;
|
assign ill_err_i = 1'b0;
|
`endif
|
`endif
|
// Supervisor/interrupt bus error flag -- this will crash the CPU if
|
// Supervisor/interrupt bus error flag -- this will crash the CPU if
|
// ever set.
|
// ever set.
|
initial ibus_err_flag = 1'b0;
|
initial ibus_err_flag = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
ibus_err_flag <= 1'b0;
|
ibus_err_flag <= 1'b0;
|
else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
|
else if ((dbgv)&&(wr_write_scc))
|
&&(~wr_reg_vl[`CPU_BUSERR_BIT]))
|
ibus_err_flag <= (ibus_err_flag)&&(wr_spreg_vl[`CPU_BUSERR_BIT]);
|
ibus_err_flag <= 1'b0;
|
|
else if ((bus_err)&&(~alu_gie))
|
else if ((bus_err)&&(~alu_gie))
|
ibus_err_flag <= 1'b1;
|
ibus_err_flag <= 1'b1;
|
// User bus error flag -- if ever set, it will cause an interrupt to
|
// User bus error flag -- if ever set, it will cause an interrupt to
|
// supervisor mode.
|
// supervisor mode.
|
initial ubus_err_flag = 1'b0;
|
`ifdef OPT_NO_USERMODE
|
|
assign ubus_err_flag = 1'b0;
|
|
`else
|
|
reg r_ubus_err_flag;
|
|
|
|
initial r_ubus_err_flag = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if ((i_rst)||(w_release_from_interrupt))
|
ubus_err_flag <= 1'b0;
|
r_ubus_err_flag <= 1'b0;
|
else if (w_release_from_interrupt)
|
else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)&&(wr_write_ucc))
|
ubus_err_flag <= 1'b0;
|
r_ubus_err_flag <= (ubus_err_flag)&&(wr_spreg_vl[`CPU_BUSERR_BIT]);
|
else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)
|
|
&&(~wr_reg_vl[`CPU_BUSERR_BIT])
|
|
&&(wr_reg_id[4])&&(wr_write_cc))
|
|
ubus_err_flag <= 1'b0;
|
|
else if ((bus_err)&&(alu_gie))
|
else if ((bus_err)&&(alu_gie))
|
ubus_err_flag <= 1'b1;
|
r_ubus_err_flag <= 1'b1;
|
|
|
|
assign ubus_err_flag = r_ubus_err_flag;
|
|
`endif
|
|
|
generate
|
generate
|
if (IMPLEMENT_DIVIDE != 0)
|
if (IMPLEMENT_DIVIDE != 0)
|
begin
|
begin
|
reg r_idiv_err_flag, r_udiv_err_flag;
|
reg r_idiv_err_flag, r_udiv_err_flag;
|
| Line 1513... |
Line 1719... |
// to be able to tell if/why the CPU crashed.
|
// to be able to tell if/why the CPU crashed.
|
initial r_idiv_err_flag = 1'b0;
|
initial r_idiv_err_flag = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
r_idiv_err_flag <= 1'b0;
|
r_idiv_err_flag <= 1'b0;
|
else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
|
else if ((dbgv)&&(wr_write_scc))
|
&&(~wr_reg_vl[`CPU_DIVERR_BIT]))
|
r_idiv_err_flag <= (r_idiv_err_flag)&&(wr_spreg_vl[`CPU_DIVERR_BIT]);
|
r_idiv_err_flag <= 1'b0;
|
else if ((div_error)&&(~alu_gie))
|
else if ((div_error)&&(div_valid)&&(~alu_gie))
|
|
r_idiv_err_flag <= 1'b1;
|
r_idiv_err_flag <= 1'b1;
|
|
|
|
assign idiv_err_flag = r_idiv_err_flag;
|
|
`ifdef OPT_NO_USERMODE
|
|
assign udiv_err_flag = 1'b0;
|
|
`else
|
// User divide (by zero) error flag -- if ever set, it will
|
// User divide (by zero) error flag -- if ever set, it will
|
// cause a sudden switch interrupt to supervisor mode.
|
// cause a sudden switch interrupt to supervisor mode.
|
initial r_udiv_err_flag = 1'b0;
|
initial r_udiv_err_flag = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if ((i_rst)||(w_release_from_interrupt))
|
r_udiv_err_flag <= 1'b0;
|
|
else if (w_release_from_interrupt)
|
|
r_udiv_err_flag <= 1'b0;
|
r_udiv_err_flag <= 1'b0;
|
else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)
|
else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)
|
&&(~wr_reg_vl[`CPU_DIVERR_BIT])
|
&&(wr_write_ucc))
|
&&(wr_reg_id[4])&&(wr_write_cc))
|
r_udiv_err_flag <= (r_udiv_err_flag)&&(wr_spreg_vl[`CPU_DIVERR_BIT]);
|
r_udiv_err_flag <= 1'b0;
|
else if ((div_error)&&(alu_gie))
|
else if ((div_error)&&(alu_gie)&&(div_valid))
|
|
r_udiv_err_flag <= 1'b1;
|
r_udiv_err_flag <= 1'b1;
|
|
|
assign idiv_err_flag = r_idiv_err_flag;
|
|
assign udiv_err_flag = r_udiv_err_flag;
|
assign udiv_err_flag = r_udiv_err_flag;
|
|
`endif
|
end else begin
|
end else begin
|
assign idiv_err_flag = 1'b0;
|
assign idiv_err_flag = 1'b0;
|
assign udiv_err_flag = 1'b0;
|
assign udiv_err_flag = 1'b0;
|
end endgenerate
|
end endgenerate
|
|
|
| Line 1550... |
Line 1757... |
reg r_ifpu_err_flag, r_ufpu_err_flag;
|
reg r_ifpu_err_flag, r_ufpu_err_flag;
|
initial r_ifpu_err_flag = 1'b0;
|
initial r_ifpu_err_flag = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
r_ifpu_err_flag <= 1'b0;
|
r_ifpu_err_flag <= 1'b0;
|
else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
|
else if ((dbgv)&&(wr_write_scc))
|
&&(~wr_reg_vl[`CPU_FPUERR_BIT]))
|
r_ifpu_err_flag <= (r_ifpu_err_flag)&&(wr_spreg_vl[`CPU_FPUERR_BIT]);
|
r_ifpu_err_flag <= 1'b0;
|
|
else if ((fpu_error)&&(fpu_valid)&&(~alu_gie))
|
else if ((fpu_error)&&(fpu_valid)&&(~alu_gie))
|
r_ifpu_err_flag <= 1'b1;
|
r_ifpu_err_flag <= 1'b1;
|
// User floating point error flag -- if ever set, it will cause
|
// User floating point error flag -- if ever set, it will cause
|
// a sudden switch interrupt to supervisor mode.
|
// a sudden switch interrupt to supervisor mode.
|
initial r_ufpu_err_flag = 1'b0;
|
initial r_ufpu_err_flag = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if ((i_rst)&&(w_release_from_interrupt))
|
r_ufpu_err_flag <= 1'b0;
|
|
else if (w_release_from_interrupt)
|
|
r_ufpu_err_flag <= 1'b0;
|
r_ufpu_err_flag <= 1'b0;
|
else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)
|
else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)
|
&&(~wr_reg_vl[`CPU_FPUERR_BIT])
|
&&(wr_write_ucc))
|
&&(wr_reg_id[4])&&(wr_write_cc))
|
r_ufpu_err_flag <= (r_ufpu_err_flag)&&(wr_spreg_vl[`CPU_FPUERR_BIT]);
|
r_ufpu_err_flag <= 1'b0;
|
|
else if ((fpu_error)&&(alu_gie)&&(fpu_valid))
|
else if ((fpu_error)&&(alu_gie)&&(fpu_valid))
|
r_ufpu_err_flag <= 1'b1;
|
r_ufpu_err_flag <= 1'b1;
|
|
|
assign ifpu_err_flag = r_ifpu_err_flag;
|
assign ifpu_err_flag = r_ifpu_err_flag;
|
assign ufpu_err_flag = r_ufpu_err_flag;
|
assign ufpu_err_flag = r_ufpu_err_flag;
|
end else begin
|
end else begin
|
assign ifpu_err_flag = 1'b0;
|
assign ifpu_err_flag = 1'b0;
|
assign ufpu_err_flag = 1'b0;
|
assign ufpu_err_flag = 1'b0;
|
end endgenerate
|
end endgenerate
|
|
|
`ifdef OPT_VLIW
|
`ifdef OPT_CIS
|
reg r_ihalt_phase, r_uhalt_phase;
|
reg r_ihalt_phase;
|
|
|
initial r_ihalt_phase = 0;
|
initial r_ihalt_phase = 0;
|
initial r_uhalt_phase = 0;
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (~alu_gie)
|
if (i_rst)
|
|
r_ihalt_phase <= 1'b0;
|
|
else if ((~alu_gie)&&(alu_pc_valid)&&(~clear_pipeline))
|
r_ihalt_phase <= alu_phase;
|
r_ihalt_phase <= alu_phase;
|
|
|
|
assign ihalt_phase = r_ihalt_phase;
|
|
|
|
`ifdef OPT_NO_USERMODE
|
|
assign uhalt_phase = 1'b0;
|
|
`else
|
|
reg r_uhalt_phase;
|
|
|
|
initial r_uhalt_phase = 0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (alu_gie)
|
if ((i_rst)||(w_release_from_interrupt))
|
r_uhalt_phase <= alu_phase;
|
|
else if (w_release_from_interrupt)
|
|
r_uhalt_phase <= 1'b0;
|
r_uhalt_phase <= 1'b0;
|
|
else if ((alu_gie)&&(alu_pc_valid))
|
|
r_uhalt_phase <= alu_phase;
|
|
else if ((~alu_gie)&&(wr_reg_ce)&&(wr_write_ucc))
|
|
r_uhalt_phase <= wr_spreg_vl[`CPU_PHASE_BIT];
|
|
|
assign ihalt_phase = r_ihalt_phase;
|
|
assign uhalt_phase = r_uhalt_phase;
|
assign uhalt_phase = r_uhalt_phase;
|
|
`endif
|
`else
|
`else
|
assign ihalt_phase = 1'b0;
|
assign ihalt_phase = 1'b0;
|
assign uhalt_phase = 1'b0;
|
assign uhalt_phase = 1'b0;
|
`endif
|
`endif
|
|
|
| Line 1608... |
Line 1823... |
//
|
//
|
// Do we need to all our partial results from the pipeline?
|
// Do we need to all our partial results from the pipeline?
|
// What happens when the pipeline has gie and ~gie instructions within
|
// What happens when the pipeline has gie and ~gie instructions within
|
// it? Do we clear both? What if a gie instruction tries to clear
|
// it? Do we clear both? What if a gie instruction tries to clear
|
// a non-gie instruction?
|
// a non-gie instruction?
|
|
`ifdef OPT_NO_USERMODE
|
|
assign upc = {(AW+2){1'b0}};
|
|
`else
|
|
reg [(AW+1):0] r_upc;
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_pc))
|
if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_pc))
|
upc <= wr_reg_vl[(AW-1):0];
|
r_upc <= { wr_spreg_vl[(AW+1):2], 2'b00 };
|
else if ((alu_gie)&&
|
else if ((alu_gie)&&
|
(((alu_pc_valid)&&(~clear_pipeline))
|
(((alu_pc_valid)&&(~clear_pipeline)&&(!alu_illegal))
|
||(mem_pc_valid)))
|
||(mem_pc_valid)))
|
upc <= alu_pc;
|
r_upc <= { alu_pc, 2'b00 };
|
|
assign upc = r_upc;
|
|
`endif
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
ipc <= RESET_ADDRESS;
|
ipc <= { RESET_BUS_ADDRESS, 2'b00 };
|
else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_pc))
|
else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_pc))
|
ipc <= wr_reg_vl[(AW-1):0];
|
ipc <= { wr_spreg_vl[(AW+1):2], 2'b00 };
|
else if ((~alu_gie)&&
|
else if ((!alu_gie)&&(!alu_phase)&&
|
(((alu_pc_valid)&&(~clear_pipeline))
|
(((alu_pc_valid)&&(~clear_pipeline)&&(!alu_illegal))
|
||(mem_pc_valid)))
|
||(mem_pc_valid)))
|
ipc <= alu_pc;
|
ipc <= { alu_pc, 2'b00 };
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
pf_pc <= RESET_ADDRESS;
|
pf_pc <= { RESET_BUS_ADDRESS, 2'b00 };
|
else if (w_switch_to_interrupt)
|
else if ((w_switch_to_interrupt)||((~gie)&&(w_clear_icache)))
|
pf_pc <= ipc;
|
pf_pc <= { ipc[(AW+1):2], 2'b00 };
|
else if (w_release_from_interrupt)
|
else if ((w_release_from_interrupt)||((gie)&&(w_clear_icache)))
|
pf_pc <= upc;
|
pf_pc <= { upc[(AW+1):2], 2'b00 };
|
else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
|
else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
|
pf_pc <= wr_reg_vl[(AW-1):0];
|
pf_pc <= { wr_spreg_vl[(AW+1):2], 2'b00 };
|
`ifdef OPT_PIPELINED
|
`ifdef OPT_PIPELINED
|
else if ((dcd_early_branch)&&(~clear_pipeline))
|
else if ((dcd_early_branch)&&(~clear_pipeline))
|
pf_pc <= dcd_branch_pc + 1;
|
pf_pc <= { dcd_branch_pc + 1'b1, 2'b00 };
|
else if ((new_pc)||((~dcd_stalled)&&(pf_valid)))
|
else if ((new_pc)||((!pf_stalled)&&(pf_valid)))
|
pf_pc <= pf_pc + {{(AW-1){1'b0}},1'b1};
|
pf_pc <= { pf_pc[(AW+1):2] + {{(AW-1){1'b0}},1'b1}, 2'b00 };
|
`else
|
`else
|
else if ((alu_gie==gie)&&(
|
else if ((alu_gie==gie)&&(
|
((alu_pc_valid)&&(~clear_pipeline))
|
((alu_pc_valid)&&(~clear_pipeline))
|
||(mem_pc_valid)))
|
||(mem_pc_valid)))
|
pf_pc <= alu_pc;
|
pf_pc <= { alu_pc[(AW-1):0], 2'b00 };
|
`endif
|
`endif
|
|
|
initial new_pc = 1'b1;
|
`ifdef OPT_PIPELINED
|
|
reg r_clear_icache;
|
|
initial r_clear_icache = 1'b1;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((i_rst)||(i_clear_pf_cache))
|
if ((i_rst)||(i_clear_pf_cache))
|
|
r_clear_icache <= 1'b1;
|
|
else if ((wr_reg_ce)&&(wr_write_scc))
|
|
r_clear_icache <= wr_spreg_vl[`CPU_CLRCACHE_BIT];
|
|
else
|
|
r_clear_icache <= 1'b0;
|
|
assign w_clear_icache = r_clear_icache;
|
|
`else
|
|
assign w_clear_icache = i_clear_pf_cache;
|
|
`endif
|
|
|
|
initial new_pc = 1'b1;
|
|
always @(posedge i_clk)
|
|
if ((i_rst)||(w_clear_icache))
|
new_pc <= 1'b1;
|
new_pc <= 1'b1;
|
else if (w_switch_to_interrupt)
|
else if (w_switch_to_interrupt)
|
new_pc <= 1'b1;
|
new_pc <= 1'b1;
|
else if (w_release_from_interrupt)
|
else if (w_release_from_interrupt)
|
new_pc <= 1'b1;
|
new_pc <= 1'b1;
|
| Line 1662... |
Line 1899... |
else
|
else
|
new_pc <= 1'b0;
|
new_pc <= 1'b0;
|
|
|
//
|
//
|
// The debug interface
|
// The debug interface
|
|
wire [31:0] w_debug_pc;
|
|
`ifdef OPT_NO_USERMODE
|
|
assign w_debug_pc[(AW+1):0] = { ipc, 2'b00 };
|
|
`else
|
|
assign w_debug_pc[(AW+1):0] = { (i_dbg_reg[4])
|
|
? { upc[(AW+1):2], uhalt_phase, 1'b0 }
|
|
: { ipc[(AW+1):2], ihalt_phase, 1'b0 } };
|
|
`endif
|
generate
|
generate
|
if (AW<32)
|
if (AW<30)
|
begin
|
assign w_debug_pc[31:(AW+2)] = 0;
|
|
endgenerate
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
begin
|
begin
|
o_dbg_reg <= regset[i_dbg_reg];
|
`ifdef OPT_NO_USERMODE
|
|
o_dbg_reg <= regset[i_dbg_reg[3:0]];
|
if (i_dbg_reg[3:0] == `CPU_PC_REG)
|
if (i_dbg_reg[3:0] == `CPU_PC_REG)
|
o_dbg_reg <= {{(32-AW){1'b0}},(i_dbg_reg[4])?upc:ipc};
|
o_dbg_reg <= w_debug_pc;
|
else if (i_dbg_reg[3:0] == `CPU_CC_REG)
|
else if (i_dbg_reg[3:0] == `CPU_CC_REG)
|
begin
|
begin
|
o_dbg_reg[13:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
|
o_dbg_reg[14:0] <= w_iflags;
|
|
o_dbg_reg[15] <= 1'b0;
|
|
o_dbg_reg[31:23] <= w_cpu_info;
|
o_dbg_reg[`CPU_GIE_BIT] <= gie;
|
o_dbg_reg[`CPU_GIE_BIT] <= gie;
|
end
|
end
|
end
|
`else
|
end else begin
|
|
always @(posedge i_clk)
|
|
begin
|
|
o_dbg_reg <= regset[i_dbg_reg];
|
o_dbg_reg <= regset[i_dbg_reg];
|
if (i_dbg_reg[3:0] == `CPU_PC_REG)
|
if (i_dbg_reg[3:0] == `CPU_PC_REG)
|
o_dbg_reg <= (i_dbg_reg[4])?upc:ipc;
|
o_dbg_reg <= w_debug_pc;
|
else if (i_dbg_reg[3:0] == `CPU_CC_REG)
|
else if (i_dbg_reg[3:0] == `CPU_CC_REG)
|
begin
|
begin
|
o_dbg_reg[13:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
|
o_dbg_reg[14:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
|
|
o_dbg_reg[15] <= 1'b0;
|
|
o_dbg_reg[31:23] <= w_cpu_info;
|
o_dbg_reg[`CPU_GIE_BIT] <= gie;
|
o_dbg_reg[`CPU_GIE_BIT] <= gie;
|
end
|
end
|
|
`endif
|
end
|
end
|
end endgenerate
|
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
o_dbg_cc <= { o_break, bus_err, gie, sleep };
|
o_dbg_cc <= { o_break, bus_err, gie, sleep };
|
|
|
|
`ifdef OPT_PIPELINED
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
o_dbg_stall <= (i_halt)&&(
|
r_halted <= (i_halt)&&(
|
(pf_cyc)||(mem_cyc_gbl)||(mem_cyc_lcl)||(mem_busy)
|
// To be halted, any long lasting instruction must
|
||((~opvalid)&&(~i_rst)&&(~dcd_illegal))
|
// be completed.
|
||((~dcdvalid)&&(~i_rst)&&(~pf_illegal)));
|
(~pf_cyc)&&(~mem_busy)&&(~alu_busy)
|
|
&&(~div_busy)&&(~fpu_busy)
|
|
// Operations must either be valid, or illegal
|
|
&&((op_valid)||(i_rst)||(dcd_illegal))
|
|
// Decode stage must be either valid, in reset, or ill
|
|
&&((dcd_valid)||(i_rst)||(pf_illegal)));
|
|
`else
|
|
always @(posedge i_clk)
|
|
r_halted <= (i_halt)&&((op_valid)||(i_rst));
|
|
`endif
|
|
assign o_dbg_stall = ~r_halted;
|
|
|
//
|
//
|
//
|
//
|
// Produce accounting outputs: Account for any CPU stalls, so we can
|
// Produce accounting outputs: Account for any CPU stalls, so we can
|
// later evaluate how well we are doing.
|
// later evaluate how well we are doing.
|
| Line 1714... |
Line 1974... |
`ifdef DEBUG_SCOPE
|
`ifdef DEBUG_SCOPE
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
o_debug <= {
|
o_debug <= {
|
/*
|
/*
|
o_break, i_wb_err, pf_pc[1:0],
|
o_break, i_wb_err, pf_pc[1:0],
|
//
|
|
flags,
|
flags,
|
//
|
pf_valid, dcd_valid, op_valid, alu_valid, mem_valid,
|
pf_valid, dcdvalid, opvalid, alu_valid,
|
|
//
|
|
mem_valid,
|
|
op_ce, alu_ce, mem_ce,
|
op_ce, alu_ce, mem_ce,
|
//
|
//
|
master_ce,
|
master_ce, op_valid_alu, op_valid_mem,
|
opvalid_alu, opvalid_mem, alu_stall,
|
|
//
|
//
|
mem_busy, op_pipe,
|
alu_stall, mem_busy, op_pipe, mem_pipe_stalled,
|
`ifdef OPT_PIPELINED_BUS_ACCESS
|
|
mem_pipe_stalled,
|
|
`else
|
|
1'b0,
|
|
`endif
|
|
mem_we,
|
mem_we,
|
//
|
// ((op_valid_alu)&&(alu_stall))
|
// ((opvalid_alu)&&(alu_stall))
|
// ||((op_valid_mem)&&(~op_pipe)&&(mem_busy))
|
// ||((opvalid_mem)&&(~op_pipe)&&(mem_busy))
|
// ||((op_valid_mem)&&( op_pipe)&&(mem_pipe_stalled)));
|
// ||((opvalid_mem)&&( op_pipe)&&(mem_pipe_stalled)));
|
// op_Av[23:20], op_Av[3:0],
|
// opA[23:20], opA[3:0],
|
gie, sleep, wr_reg_ce, wr_gpreg_vl[4:0]
|
gie, sleep, wr_reg_ce, wr_reg_vl[4:0]
|
|
*/
|
*/
|
|
|
o_break, i_wb_err, o_wb_gbl_cyc, o_wb_gbl_stb,
|
|
pf_valid, dcdvalid, opvalid, alu_valid,
|
|
mem_valid, dcd_ce, op_ce, alu_ce,
|
|
mem_ce,
|
|
pf_ce, gie, sleep,
|
|
{ ((o_wb_gbl_cyc)&&(o_wb_gbl_stb)&&(o_wb_we))
|
|
? o_wb_data[15:0]
|
|
: ((o_wb_gbl_cyc)&&(~o_wb_we)&&(i_wb_ack))
|
|
? i_wb_data[15:0]
|
|
: o_wb_addr[15:0]
|
|
}
|
|
/*
|
/*
|
i_rst, master_ce, (new_pc),
|
i_rst, master_ce, (new_pc),
|
((dcd_early_branch)&&(dcdvalid)),
|
((dcd_early_branch)&&(dcd_valid)),
|
pf_valid, pf_illegal,
|
pf_valid, pf_illegal,
|
op_ce, dcd_ce, dcdvalid, dcd_stalled,
|
op_ce, dcd_ce, dcd_valid, dcd_stalled,
|
pf_cyc, pf_stb, pf_we, pf_ack, pf_stall, pf_err,
|
pf_cyc, pf_stb, pf_we, pf_ack, pf_stall, pf_err,
|
pf_pc[7:0], pf_addr[7:0]
|
pf_pc[7:0], pf_addr[7:0]
|
*/
|
*/
|
/*
|
|
i_wb_err, gie, alu_illegal,
|
i_wb_err, gie, alu_illegal,
|
(new_pc)||((dcd_early_branch)&&(~clear_pipeline)),
|
(new_pc)||((dcd_early_branch)&&(~clear_pipeline)),
|
mem_busy,
|
mem_busy,
|
(mem_busy)?{ (o_wb_gbl_stb|o_wb_lcl_stb), o_wb_we,
|
(mem_busy)?{ (o_wb_gbl_stb|o_wb_lcl_stb), o_wb_we,
|
o_wb_addr[8:0] }
|
o_wb_addr[8:0] }
|
: { instruction[31:21] },
|
: { pf_instruction[31:21] },
|
pf_valid, (pf_valid) ? alu_pc[14:0]
|
pf_valid, (pf_valid) ? alu_pc[14:0]
|
:{ pf_cyc, pf_stb, pf_pc[12:0] }
|
:{ pf_cyc, pf_stb, pf_pc[14:2] }
|
*/
|
|
/*
|
/*
|
i_wb_err, gie, new_pc, dcd_early_branch, // 4
|
i_wb_err, gie, new_pc, dcd_early_branch, // 4
|
pf_valid, pf_cyc, pf_stb, instruction_pc[0], // 4
|
pf_valid, pf_cyc, pf_stb, pf_instruction_pc[0], // 4
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instruction[30:27], // 4
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pf_instruction[30:27], // 4
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dcd_gie, mem_busy, o_wb_gbl_cyc, o_wb_gbl_stb, // 4
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dcd_gie, mem_busy, o_wb_gbl_cyc, o_wb_gbl_stb, // 4
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dcdvalid,
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dcd_valid,
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((dcd_early_branch)&&(~clear_pipeline)) // 15
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((dcd_early_branch)&&(~clear_pipeline)) // 15
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? dcd_branch_pc[14:0]:pf_pc[14:0]
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? dcd_branch_pc[14:0]:pf_pc[14:0]
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*/
|
*/
|
};
|
};
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`endif
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`endif
|
