| Line 65... |
Line 65... |
//
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//
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module ziptimer(i_clk, i_rst, i_ce,
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module ziptimer(i_clk, i_rst, i_ce,
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_data,
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_int);
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o_int);
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parameter BW = 32, VW = (BW-1);
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parameter BW = 32, VW = (BW-1), RELOADABLE=1;
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input i_clk, i_rst, i_ce;
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input i_clk, i_rst, i_ce;
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// Wishbone inputs
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// Wishbone inputs
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input [(BW-1):0] i_wb_data;
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input [(BW-1):0] i_wb_data;
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// Wishbone outputs
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// Wishbone outputs
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Line 77... |
output wire o_wb_stall;
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output wire o_wb_stall;
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output wire [(BW-1):0] o_wb_data;
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output wire [(BW-1):0] o_wb_data;
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// Interrupt line
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// Interrupt line
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output reg o_int;
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output reg o_int;
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reg r_auto_reload, r_running;
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reg r_running;
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reg [(VW-1):0] r_reload_value;
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wire wb_write;
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wire wb_write;
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assign wb_write = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we));
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assign wb_write = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we));
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wire auto_reload;
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wire [(VW-1):0] reload_value;
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initial r_running = 1'b0;
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initial r_running = 1'b0;
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initial r_auto_reload = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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r_running <= 1'b0;
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r_running <= 1'b0;
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else if (wb_write)
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else if (wb_write)
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r_running <= (|i_wb_data[(VW-1):0]);
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r_running <= (|i_wb_data[(VW-1):0]);
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else if ((o_int)&&(~r_auto_reload))
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else if ((o_int)&&(~auto_reload))
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r_running <= 1'b0;
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r_running <= 1'b0;
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generate
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if (RELOADABLE != 0)
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begin
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reg r_auto_reload;
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reg [(VW-1):0] r_reload_value;
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initial r_auto_reload = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (wb_write)
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if (wb_write)
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r_auto_reload <= (i_wb_data[(BW-1)]);
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r_auto_reload <= (i_wb_data[(BW-1)]);
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assign auto_reload = r_auto_reload;
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// If setting auto-reload mode, and the value to other
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// If setting auto-reload mode, and the value to other
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// than zero, set the auto-reload value
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// than zero, set the auto-reload value
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((wb_write)&&(i_wb_data[(BW-1)])&&(|i_wb_data[(VW-1):0]))
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if ((wb_write)&&(i_wb_data[(BW-1)])&&(|i_wb_data[(VW-1):0]))
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r_reload_value <= i_wb_data[(VW-1):0];
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r_reload_value <= i_wb_data[(VW-1):0];
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assign reload_value = r_reload_value;
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end else begin
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assign auto_reload = 1'b0;
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assign reload_value = 0;
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end endgenerate
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reg [(VW-1):0] r_value;
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reg [(VW-1):0] r_value;
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initial r_value = 0;
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initial r_value = 0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (wb_write)
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if (wb_write)
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r_value <= i_wb_data[(VW-1):0];
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r_value <= i_wb_data[(VW-1):0];
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else if ((r_running)&&(i_ce)&&(~o_int))
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else if ((r_running)&&(i_ce)&&(~o_int))
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r_value <= r_value + {(VW){1'b1}}; // r_value - 1;
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r_value <= r_value + {(VW){1'b1}}; // r_value - 1;
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else if ((r_running)&&(r_auto_reload)&&(o_int))
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else if ((r_running)&&(auto_reload)&&(o_int))
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r_value <= r_reload_value;
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r_value <= reload_value;
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// Set the interrupt on our last tick.
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// Set the interrupt on our last tick, as we transition from one to
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// zero.
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initial o_int = 1'b0;
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initial o_int = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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o_int <= 1'b0;
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o_int <= 1'b0;
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else if (i_ce)
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else if (i_ce)
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Line 148... |
o_wb_ack <= (i_wb_cyc)&&(i_wb_stb);
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o_wb_ack <= (i_wb_cyc)&&(i_wb_stb);
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assign o_wb_stall = 1'b0;
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assign o_wb_stall = 1'b0;
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generate
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generate
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if (VW < BW-1)
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if (VW < BW-1)
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assign o_wb_data = { r_auto_reload, {(BW-1-VW){1'b0}}, r_value };
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assign o_wb_data = { auto_reload, {(BW-1-VW){1'b0}}, r_value };
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else
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else
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assign o_wb_data = { r_auto_reload, r_value };
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assign o_wb_data = { auto_reload, r_value };
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endgenerate
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endgenerate
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endmodule
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endmodule
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