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///////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: ziptimer.v
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// Filename: ziptimer.v
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//
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//
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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//
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//
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//
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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///////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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// Copyright (C) 2015,2017, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory. Run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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///////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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module ziptimer(i_clk, i_rst, i_ce,
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module ziptimer(i_clk, i_rst, i_ce,
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_data,
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_int);
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o_int);
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reg r_running;
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reg r_running;
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wire wb_write;
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wire wb_write;
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assign wb_write = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we));
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assign wb_write = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we));
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wire auto_reload, need_reload;
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wire auto_reload;
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wire [(VW-1):0] reload_value;
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wire [(VW-1):0] reload_value;
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initial r_running = 1'b0;
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initial r_running = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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r_running <= 1'b0;
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r_running <= 1'b0;
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generate
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generate
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if (RELOADABLE != 0)
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if (RELOADABLE != 0)
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begin
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begin
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reg r_auto_reload, r_need_reload;
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reg r_auto_reload;
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reg [(VW-1):0] r_reload_value;
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reg [(VW-1):0] r_reload_value;
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initial r_auto_reload = 1'b0;
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initial r_auto_reload = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (wb_write)
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if (wb_write)
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r_auto_reload <= (i_wb_data[(BW-1)]);
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r_auto_reload <= (i_wb_data[(BW-1)]);
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assign auto_reload = r_auto_reload;
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assign auto_reload = r_auto_reload;
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// than zero, set the auto-reload value
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// than zero, set the auto-reload value
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((wb_write)&&(i_wb_data[(BW-1)])&&(|i_wb_data[(VW-1):0]))
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if ((wb_write)&&(i_wb_data[(BW-1)])&&(|i_wb_data[(VW-1):0]))
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r_reload_value <= i_wb_data[(VW-1):0];
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r_reload_value <= i_wb_data[(VW-1):0];
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assign reload_value = r_reload_value;
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assign reload_value = r_reload_value;
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initial r_need_reload = 1'b0;
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always @(posedge i_clk)
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if (i_rst)
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r_need_reload <= 1'b0;
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else if ((i_ce)&&(auto_reload))
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r_need_reload <= (i_ce)
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&&(r_value == { {(VW-1){1'b0}}, 1'b1 });
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assign need_reload = r_need_reload;
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end else begin
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end else begin
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assign auto_reload = 1'b0;
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assign auto_reload = 1'b0;
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assign reload_value = 0;
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assign reload_value = 0;
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assign need_reload = 1'b0;
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end endgenerate
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end endgenerate
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reg [(VW-1):0] r_value;
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reg [(VW-1):0] r_value;
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initial r_value = 0;
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initial r_value = 0;
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