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[/] [s6soc/] [trunk/] [rtl/] [cpu/] [ziptimer.v] - Diff between revs 42 and 46

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///////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
//
// Filename:    ziptimer.v
// Filename:    ziptimer.v
//
//
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
//
//
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//
//
//
//
// Creator:     Dan Gisselquist, Ph.D.
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Technology, LLC
//              Gisselquist Technology, LLC
//
//
///////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
//
// Copyright (C) 2015, Gisselquist Technology, LLC
// Copyright (C) 2015,2017, Gisselquist Technology, LLC
//
//
// This program is free software (firmware): you can redistribute it and/or
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
// your option) any later version.
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// This program is distributed in the hope that it will be useful, but WITHOUT
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
// for more details.
//
//
 
// You should have received a copy of the GNU General Public License along
 
// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
 
// target there if the PDF file isn't present.)  If not, see
 
// <http://www.gnu.org/licenses/> for a copy.
 
//
// License:     GPL, v3, as defined and found on www.gnu.org,
// License:     GPL, v3, as defined and found on www.gnu.org,
//              http://www.gnu.org/licenses/gpl.html
//              http://www.gnu.org/licenses/gpl.html
//
//
//
//
///////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
 
//
//
//
module  ziptimer(i_clk, i_rst, i_ce,
module  ziptimer(i_clk, i_rst, i_ce,
                i_wb_cyc, i_wb_stb, i_wb_we, i_wb_data,
                i_wb_cyc, i_wb_stb, i_wb_we, i_wb_data,
                        o_wb_ack, o_wb_stall, o_wb_data,
                        o_wb_ack, o_wb_stall, o_wb_data,
                o_int);
                o_int);
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        reg                     r_running;
        reg                     r_running;
 
 
        wire    wb_write;
        wire    wb_write;
        assign  wb_write = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we));
        assign  wb_write = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we));
 
 
        wire                    auto_reload, need_reload;
        wire    auto_reload;
        wire    [(VW-1):0]       reload_value;
        wire    [(VW-1):0]       reload_value;
 
 
        initial r_running = 1'b0;
        initial r_running = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
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                        r_running <= 1'b0;
                        r_running <= 1'b0;
 
 
        generate
        generate
        if (RELOADABLE != 0)
        if (RELOADABLE != 0)
        begin
        begin
                reg                     r_auto_reload, r_need_reload;
                reg     r_auto_reload;
                reg     [(VW-1):0]       r_reload_value;
                reg     [(VW-1):0]       r_reload_value;
 
 
                initial r_auto_reload = 1'b0;
                initial r_auto_reload = 1'b0;
 
 
                always @(posedge i_clk)
                always @(posedge i_clk)
                        if (wb_write)
                        if (wb_write)
                                r_auto_reload <= (i_wb_data[(BW-1)]);
                                r_auto_reload <= (i_wb_data[(BW-1)]);
 
 
                assign  auto_reload = r_auto_reload;
                assign  auto_reload = r_auto_reload;
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                // than zero, set the auto-reload value
                // than zero, set the auto-reload value
                always @(posedge i_clk)
                always @(posedge i_clk)
                        if ((wb_write)&&(i_wb_data[(BW-1)])&&(|i_wb_data[(VW-1):0]))
                        if ((wb_write)&&(i_wb_data[(BW-1)])&&(|i_wb_data[(VW-1):0]))
                                r_reload_value <= i_wb_data[(VW-1):0];
                                r_reload_value <= i_wb_data[(VW-1):0];
                assign  reload_value = r_reload_value;
                assign  reload_value = r_reload_value;
 
 
                initial r_need_reload = 1'b0;
 
                always @(posedge i_clk)
 
                        if (i_rst)
 
                                r_need_reload <= 1'b0;
 
                        else if ((i_ce)&&(auto_reload))
 
                                r_need_reload <= (i_ce)
 
                                        &&(r_value == { {(VW-1){1'b0}}, 1'b1 });
 
 
 
                assign need_reload = r_need_reload;
 
        end else begin
        end else begin
                assign  auto_reload = 1'b0;
                assign  auto_reload = 1'b0;
                assign  reload_value = 0;
                assign  reload_value = 0;
                assign  need_reload = 1'b0;
 
        end endgenerate
        end endgenerate
 
 
 
 
        reg     [(VW-1):0]       r_value;
        reg     [(VW-1):0]       r_value;
        initial r_value = 0;
        initial r_value = 0;

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