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[/] [s6soc/] [trunk/] [rtl/] [txuart.v] - Diff between revs 4 and 13

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Rev 4 Rev 13
Line 102... Line 102...
// `define      TXU_START       4'hd    // An unused state
// `define      TXU_START       4'hd    // An unused state
`define TXU_BREAK       4'he
`define TXU_BREAK       4'he
`define TXU_IDLE        4'hf
`define TXU_IDLE        4'hf
//
//
//
//
module txuart(i_clk, i_reset, i_setup, i_break, i_wr, i_data, o_uart, i_cts, o_busy);
module txuart(i_clk, i_reset, i_setup, i_break, i_wr, i_data, o_uart, o_busy);
        input                   i_clk, i_reset;
        input                   i_clk, i_reset;
        input           [29:0]   i_setup;
        input           [29:0]   i_setup;
        input                   i_break;
        input                   i_break;
        input                   i_wr;
        input                   i_wr;
        input           [7:0]    i_data;
        input           [7:0]    i_data;
        output  reg             o_uart;
        output  reg             o_uart;
        input                   i_cts;
 
        output  wire            o_busy;
        output  wire            o_busy;
 
 
        wire    [27:0]   clocks_per_baud, break_condition;
        wire    [27:0]   clocks_per_baud, break_condition;
        wire    [1:0]    data_bits;
        wire    [1:0]    data_bits;
        wire            use_parity, parity_even, dblstop, fixd_parity;
        wire            use_parity, parity_even, dblstop, fixd_parity;
Line 225... Line 224...
                                // out this last bit.
                                // out this last bit.
                        end
                        end
                end
                end
        end
        end
 
 
        // assign       o_busy = (r_busy)||(~i_cts);
 
        assign  o_busy = (r_busy);
        assign  o_busy = (r_busy);
endmodule
endmodule
 
 
 
 
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