| Line 1... |
Line 1... |
/////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
//
|
|
//
|
//
|
// Filename: txuart.v
|
// Filename: txuart.v
|
//
|
//
|
// Project: FPGA library development (Spartan 3E development board)
|
// Project: CMod S6 System on a Chip, ZipCPU demonstration project
|
//
|
//
|
// Purpose: Transmit outputs over a single UART line.
|
// Purpose: Transmit outputs over a single UART line.
|
//
|
//
|
// To interface with this module, connect it to your system clock,
|
// To interface with this module, connect it to your system clock,
|
// pass it the 32 bit setup register (defined below) and the byte
|
// pass it the 32 bit setup register (defined below) and the byte
|
| Line 58... |
Line 57... |
// 32'h005161 // For 9600 baud, 8 bit, no parity
|
// 32'h005161 // For 9600 baud, 8 bit, no parity
|
//
|
//
|
// Creator: Dan Gisselquist
|
// Creator: Dan Gisselquist
|
// Gisselquist Technology, LLC
|
// Gisselquist Technology, LLC
|
//
|
//
|
// Copyright: 2015
|
////////////////////////////////////////////////////////////////////////////////
|
|
//
|
|
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
|
|
//
|
|
// This program is free software (firmware): you can redistribute it and/or
|
|
// modify it under the terms of the GNU General Public License as published
|
|
// by the Free Software Foundation, either version 3 of the License, or (at
|
|
// your option) any later version.
|
|
//
|
|
// This program is distributed in the hope that it will be useful, but WITHOUT
|
|
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
|
|
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
|
// for more details.
|
|
//
|
|
// You should have received a copy of the GNU General Public License along
|
|
// with this program. (It's in the $(ROOT)/doc directory, run make with no
|
|
// target there if the PDF file isn't present.) If not, see
|
|
// <http://www.gnu.org/licenses/> for a copy.
|
|
//
|
|
// License: GPL, v3, as defined and found on www.gnu.org,
|
|
// http://www.gnu.org/licenses/gpl.html
|
//
|
//
|
//
|
//
|
/////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
//
|
//
|
// This software is the ownership of Gisselquist Technology, LLC, and as
|
|
// such it is proprietary. It is provided without any warrantees, either
|
|
// express or implied, so that it may be tested. Upon completion, I ask
|
|
// that working code be returned and not further distributed beyond those
|
|
// that it is originally offered to.
|
|
//
|
//
|
// Thank you.
|
|
//
|
//
|
`define TXU_BIT_ZERO 4'h0
|
`define TXU_BIT_ZERO 4'h0
|
`define TXU_BIT_ONE 4'h1
|
`define TXU_BIT_ONE 4'h1
|
`define TXU_BIT_TWO 4'h2
|
`define TXU_BIT_TWO 4'h2
|
`define TXU_BIT_THREE 4'h3
|
`define TXU_BIT_THREE 4'h3
|
| Line 87... |
Line 100... |
// 4'hb // Unused
|
// 4'hb // Unused
|
// 4'hc // Unused
|
// 4'hc // Unused
|
// `define TXU_START 4'hd // An unused state
|
// `define TXU_START 4'hd // An unused state
|
`define TXU_BREAK 4'he
|
`define TXU_BREAK 4'he
|
`define TXU_IDLE 4'hf
|
`define TXU_IDLE 4'hf
|
|
//
|
module txuart(i_clk, i_reset, i_setup, i_break, i_wr, i_data, o_uart, o_busy);
|
//
|
|
module txuart(i_clk, i_reset, i_setup, i_break, i_wr, i_data, o_uart, i_cts, o_busy);
|
input i_clk, i_reset;
|
input i_clk, i_reset;
|
input [29:0] i_setup;
|
input [29:0] i_setup;
|
input i_break;
|
input i_break;
|
input i_wr;
|
input i_wr;
|
input [7:0] i_data;
|
input [7:0] i_data;
|
output reg o_uart, o_busy;
|
output reg o_uart;
|
|
input i_cts;
|
|
output wire o_busy;
|
|
|
wire [27:0] clocks_per_baud, break_condition;
|
wire [27:0] clocks_per_baud, break_condition;
|
wire [1:0] data_bits;
|
wire [1:0] data_bits;
|
wire use_parity, parity_even, dblstop, fixd_parity;
|
wire use_parity, parity_even, dblstop, fixd_parity;
|
reg [29:0] r_setup;
|
reg [29:0] r_setup;
|
| Line 112... |
Line 128... |
|
|
reg [27:0] baud_counter;
|
reg [27:0] baud_counter;
|
reg [3:0] state;
|
reg [3:0] state;
|
reg [7:0] lcl_data;
|
reg [7:0] lcl_data;
|
reg calc_parity;
|
reg calc_parity;
|
|
reg r_busy;
|
|
|
initial o_uart = 1'b1;
|
initial o_uart = 1'b1;
|
initial o_busy = 1'b1;
|
initial r_busy = 1'b1;
|
initial state = `TXU_IDLE;
|
initial state = `TXU_IDLE;
|
// initial baud_counter = clocks_per_baud;
|
// initial baud_counter = clocks_per_baud;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
begin
|
begin
|
if (i_reset)
|
if (i_reset)
|
begin
|
begin
|
baud_counter <= clocks_per_baud;
|
baud_counter <= clocks_per_baud;
|
o_uart <= 1'b1;
|
o_uart <= 1'b1;
|
o_busy <= 1'b1;
|
r_busy <= 1'b1;
|
state <= `TXU_IDLE;
|
state <= `TXU_IDLE;
|
lcl_data <= 8'h0;
|
lcl_data <= 8'h0;
|
calc_parity <= 1'b0;
|
calc_parity <= 1'b0;
|
end else if (i_break)
|
end else if (i_break)
|
begin
|
begin
|
baud_counter <= break_condition;
|
baud_counter <= break_condition;
|
o_uart <= 1'b0;
|
o_uart <= 1'b0;
|
state <= `TXU_BREAK;
|
state <= `TXU_BREAK;
|
calc_parity <= 1'b0;
|
calc_parity <= 1'b0;
|
o_busy <= 1'b1;
|
r_busy <= 1'b1;
|
end else if (baud_counter != 0)
|
end else if (baud_counter != 0)
|
begin // o_busy needs to be set coming into here
|
begin // r_busy needs to be set coming into here
|
baud_counter <= baud_counter - 28'h01;
|
baud_counter <= baud_counter - 28'h01;
|
o_busy <= 1'b1;
|
r_busy <= 1'b1;
|
end else if (state == `TXU_BREAK)
|
end else if (state == `TXU_BREAK)
|
begin
|
begin
|
state <= `TXU_IDLE;
|
state <= `TXU_IDLE;
|
o_busy <= 1'b1;
|
r_busy <= 1'b1;
|
o_uart <= 1'b1;
|
o_uart <= 1'b1;
|
calc_parity <= 1'b0;
|
calc_parity <= 1'b0;
|
// Give us two stop bits before becoming available
|
// Give us two stop bits before becoming available
|
baud_counter <= clocks_per_baud<<2;
|
baud_counter <= clocks_per_baud<<2;
|
end else if (state == `TXU_IDLE) // STATE_IDLE
|
end else if (state == `TXU_IDLE) // STATE_IDLE
|
begin
|
begin
|
// baud_counter <= 0;
|
// baud_counter <= 0;
|
r_setup <= i_setup;
|
r_setup <= i_setup;
|
calc_parity <= 1'b0;
|
calc_parity <= 1'b0;
|
if ((i_wr)&&(~o_busy))
|
if ((i_wr)&&(~r_busy))
|
begin // Immediately start us off with a start bit
|
begin // Immediately start us off with a start bit
|
o_uart <= 1'b0;
|
o_uart <= 1'b0;
|
o_busy <= 1'b1;
|
r_busy <= 1'b1;
|
case(data_bits)
|
case(data_bits)
|
2'b00: state <= `TXU_BIT_ZERO;
|
2'b00: state <= `TXU_BIT_ZERO;
|
2'b01: state <= `TXU_BIT_ONE;
|
2'b01: state <= `TXU_BIT_ONE;
|
2'b10: state <= `TXU_BIT_TWO;
|
2'b10: state <= `TXU_BIT_TWO;
|
2'b11: state <= `TXU_BIT_THREE;
|
2'b11: state <= `TXU_BIT_THREE;
|
endcase
|
endcase
|
lcl_data <= i_data;
|
lcl_data <= i_data;
|
baud_counter <= clocks_per_baud-28'h01;
|
baud_counter <= clocks_per_baud-28'h01;
|
end else begin // Stay in idle
|
end else begin // Stay in idle
|
o_uart <= 1'b1;
|
o_uart <= 1'b1;
|
o_busy <= 0;
|
r_busy <= 0;
|
// lcl_data is irrelevant
|
// lcl_data is irrelevant
|
// state <= state;
|
// state <= state;
|
end
|
end
|
end else begin
|
end else begin
|
// One clock tick in each of these states ...
|
// One clock tick in each of these states ...
|
baud_counter <= clocks_per_baud - 28'h01;
|
baud_counter <= clocks_per_baud - 28'h01;
|
o_busy <= 1'b1;
|
r_busy <= 1'b1;
|
if (state[3] == 0) // First 8 bits
|
if (state[3] == 0) // First 8 bits
|
begin
|
begin
|
o_uart <= lcl_data[0];
|
o_uart <= lcl_data[0];
|
calc_parity <= calc_parity ^ lcl_data[0];
|
calc_parity <= calc_parity ^ lcl_data[0];
|
if (state == `TXU_BIT_SEVEN)
|
if (state == `TXU_BIT_SEVEN)
|
| Line 201... |
Line 218... |
calc_parity <= 1'b0;
|
calc_parity <= 1'b0;
|
end else // `TXU_SECOND_STOP and default:
|
end else // `TXU_SECOND_STOP and default:
|
begin
|
begin
|
state <= `TXU_IDLE; // Go back to idle
|
state <= `TXU_IDLE; // Go back to idle
|
o_uart <= 1'b1;
|
o_uart <= 1'b1;
|
// Still o_busy, since we need to wait
|
// Still r_busy, since we need to wait
|
// for the baud clock to finish counting
|
// for the baud clock to finish counting
|
// out this last bit.
|
// out this last bit.
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
|
// assign o_busy = (r_busy)||(~i_cts);
|
|
assign o_busy = (r_busy);
|
endmodule
|
endmodule
|
|
|
|
|
|
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
