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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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// Copyright (C) 2015-2017, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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| Line 24... |
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// You should have received a copy of the GNU General Public License along
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// with this program. (It's in the $(ROOT)/doc directory. Run make with no
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// target there if the PDF file isn't present.) If not, see
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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// <http://www.gnu.org/licenses/> for a copy.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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module wbubus(i_clk,i_rx_stb,i_rx_data,o_wb_cyc,o_wb_stb,o_wb_we,o_wb_addr,
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module wbubus(i_clk,i_rx_stb,i_rx_data,o_wb_cyc,o_wb_stb,o_wb_we,o_wb_addr,
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o_wb_data,i_wb_ack,i_wb_stall,i_wb_err,i_wb_data,i_interrupt,o_tx_stb,o_tx_data
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o_wb_data,i_wb_ack,i_wb_stall,i_wb_err,i_wb_data,i_interrupt,o_tx_stb,o_tx_data
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,i_tx_busy);parameter LGWATCHDOG=19;input i_clk;input i_rx_stb;input[7:0]
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,i_tx_busy,o_dbg);parameter LGWATCHDOG=12;input i_clk;input i_rx_stb;input[7:0
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i_rx_data;output wire o_wb_cyc,o_wb_stb,o_wb_we;output wire[31:0]o_wb_addr,
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]i_rx_data;output wire o_wb_cyc,o_wb_stb,o_wb_we;output wire[31:0]o_wb_addr,
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o_wb_data;input i_wb_ack,i_wb_stall,i_wb_err;input[31:0]i_wb_data;input
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o_wb_data;input i_wb_ack,i_wb_stall,i_wb_err;input[31:0]i_wb_data;input
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i_interrupt;output wire o_tx_stb;output wire[7:0]o_tx_data;input i_tx_busy;reg
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i_interrupt;output wire o_tx_stb;output wire[7:0]o_tx_data;input i_tx_busy;
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PhcDs;wire QhcDs;wire[35:0]RhcDs;ShcDs ThcDs(i_clk,i_rx_stb,i_rx_data,QhcDs,
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output wire o_dbg;reg geVMD2;wire heVMD2;wire[35:0]ieVMD2;jeVMD2 keVMD2(i_clk,
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RhcDs);wire UhcDs,VhcDs,WhcDs,XhcDs;wire[35:0]YhcDs,ZhcDs;
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i_rx_stb,i_rx_data,heVMD2,ieVMD2);wire leVMD2,meVMD2,neVMD2,oeVMD2;wire[35:0]
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`ifdef aicDs
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peVMD2,qeVMD2;wire reVMD2,seVMD2;assign meVMD2=(~leVMD2)&&(reVMD2);assign
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assign VhcDs=QhcDs;assign YhcDs=RhcDs;assign XhcDs=1'd0;
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oeVMD2=geVMD2;teVMD2#(36,6)ueVMD2(i_clk,oeVMD2,heVMD2,ieVMD2,meVMD2,peVMD2,
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`else
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reVMD2,seVMD2);veVMD2 weVMD2(i_clk,geVMD2,meVMD2,peVMD2,leVMD2,o_wb_cyc,
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wire bicDs,cicDs;assign VhcDs=(~UhcDs)&&(bicDs);assign XhcDs=PhcDs;dicDs#(36,6
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o_wb_stb,o_wb_we,o_wb_addr,o_wb_data,i_wb_ack,i_wb_stall,i_wb_err,i_wb_data,
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)eicDs(i_clk,XhcDs,QhcDs,RhcDs,VhcDs,YhcDs,bicDs,cicDs);
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neVMD2,qeVMD2);wire xeVMD2;yeVMD2 zeVMD2(i_clk,oeVMD2,neVMD2,qeVMD2,o_wb_cyc,
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`endif
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i_interrupt,neVMD2,o_tx_stb,o_tx_data,i_tx_busy,xeVMD2);reg[(LGWATCHDOG-1):0]
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ficDs gicDs(i_clk,PhcDs,VhcDs,YhcDs,UhcDs,o_wb_cyc,o_wb_stb,o_wb_we,o_wb_addr
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AeVMD2;initial geVMD2=1'd0;initial AeVMD2=0;always@(posedge i_clk)if((~o_wb_cyc
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,o_wb_data,i_wb_ack,i_wb_stall,i_wb_err,i_wb_data,WhcDs,ZhcDs);wire hicDs;iicDs
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)||(i_wb_ack))begin AeVMD2<=0;geVMD2<=1'd0;end else if(&AeVMD2)begin geVMD2<=
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jicDs(i_clk,XhcDs,WhcDs,ZhcDs,o_wb_cyc,i_interrupt,WhcDs,o_tx_stb,o_tx_data,
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1'd1;AeVMD2<=0;end else begin AeVMD2<=AeVMD2+{{(LGWATCHDOG-1){1'd0}},1'd1};
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i_tx_busy,hicDs);reg[(LGWATCHDOG-1):0]kicDs;initial PhcDs=1'd0;initial kicDs=0
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geVMD2<=1'd0;end assign o_dbg=oeVMD2;endmodule module BeVMD2(i_clk,CeVMD2,
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;always@(posedge i_clk)if((~o_wb_cyc)||(i_wb_ack))begin kicDs<=0;PhcDs<=1'd0;
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DeVMD2,EeVMD2,FeVMD2);input i_clk,CeVMD2;input[35:0]DeVMD2;output reg EeVMD2;
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end else if(&kicDs)begin PhcDs<=1'd1;kicDs<=0;end else begin kicDs<=kicDs+{{(
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output reg[35:0]FeVMD2;wire GeVMD2=(DeVMD2[35:33]==3'd3);reg[7:0]HeVMD2;initial
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LGWATCHDOG-1){1'd0}},1'd1};PhcDs<=1'd0;end endmodule
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HeVMD2=8'd0;always@(posedge i_clk)if((CeVMD2)&&(GeVMD2))HeVMD2<=HeVMD2+8'd1;reg
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[31:0]IeVMD2[0:255];always@(posedge i_clk)if(CeVMD2)IeVMD2[HeVMD2]<={DeVMD2[32
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module licDs(i_clk,micDs,nicDs,oicDs,picDs,qicDs,i_tx_busy,ricDs);input i_clk,
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:31],DeVMD2[29:0]};reg[35:0]JeVMD2;always@(posedge i_clk)if(CeVMD2)JeVMD2<=
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micDs;input[6:0]nicDs;output reg oicDs;output reg[6:0]picDs;input qicDs;input
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DeVMD2;reg[7:0]KeVMD2;always@(posedge i_clk)KeVMD2=HeVMD2-{JeVMD2[32:31],JeVMD2
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i_tx_busy;output wire ricDs;reg sicDs,ticDs;initial sicDs=1'd1;initial ticDs=
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[29:24]};reg[24:0]LeVMD2;always@(posedge i_clk)case(JeVMD2[32:30])3'd0:LeVMD2
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1'd1;always@(posedge i_clk)if((~i_tx_busy)&&(oicDs))sicDs<=(picDs[6]);always@(
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<={19'd0,JeVMD2[29:24]};3'd2:LeVMD2<={13'd0,JeVMD2[29:18]};3'd4:LeVMD2<={7'd0,
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posedge i_clk)if((micDs)&&(~ricDs))ticDs<=(nicDs[6]);reg[6:0]uicDs;initial
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JeVMD2[29:12]};3'd6:LeVMD2<={1'd0,JeVMD2[29:6]};3'd1:LeVMD2<={{(19){JeVMD2[29]
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uicDs=7'd0;always@(posedge i_clk)if((~i_tx_busy)&&(oicDs))begin if(picDs[6])
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}},JeVMD2[29:24]};3'd3:LeVMD2<={{(13){JeVMD2[29]}},JeVMD2[29:18]};3'd5:LeVMD2
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uicDs<=0;else uicDs<=uicDs+7'd1;end reg vicDs;initial vicDs=1'd0;always@(
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<={{(7){JeVMD2[29]}},JeVMD2[29:12]};3'd7:LeVMD2<={{(1){JeVMD2[29]}},JeVMD2[29:6
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posedge i_clk)vicDs<=(uicDs>7'd72);initial oicDs=1'd0;always@(posedge i_clk)if
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]};endcase wire[31:0]MeVMD2;assign MeVMD2={{(7){LeVMD2[24]}},LeVMD2};reg[9:0]
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((micDs)&&(~ricDs))begin oicDs<=(vicDs)||(~nicDs[6]);picDs<=nicDs;end else if(
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NeVMD2;always@(posedge i_clk)if(~JeVMD2[34])NeVMD2<=10'd1+{6'd0,JeVMD2[33:31]}
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~ricDs)begin oicDs<=(~i_tx_busy)&&(~qicDs)&&(~sicDs)&&(ticDs);picDs<=7'd64;end
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;else NeVMD2<=10'd9+{1'd0,JeVMD2[33:31],JeVMD2[29:24]};reg[31:0]OeVMD2;always@
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else if(~i_tx_busy)oicDs<=1'd0;reg wicDs;initial wicDs=1'd0;always@(posedge
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(posedge i_clk)OeVMD2<=IeVMD2[KeVMD2];reg[2:0]PeVMD2;initial PeVMD2=0;always@(
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i_clk)wicDs<=(oicDs);assign ricDs=(wicDs)||(oicDs);endmodule
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posedge i_clk)PeVMD2<={PeVMD2[1:0],CeVMD2};always@(posedge i_clk)EeVMD2<=PeVMD2
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[2];always@(posedge i_clk)if(JeVMD2[35:30]==6'd46)FeVMD2<=JeVMD2;else casez(
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module xicDs(i_clk,micDs,yicDs,oicDs,zicDs,AicDs);parameter BicDs=32,CicDs=36,
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JeVMD2[35:30])6'b001??0:FeVMD2<={4'd0,MeVMD2[31:0]};6'b001??1:FeVMD2<={3'd1,
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DicDs=10;input i_clk,micDs;input[(CicDs-1):0]yicDs;output wire oicDs;output
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MeVMD2[31:30],1'd1,MeVMD2[29:0]};6'b010???:FeVMD2<={3'd3,OeVMD2[31:30],JeVMD2[
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wire[(CicDs-1):0]zicDs;input AicDs;reg EicDs;reg[35:0]FicDs;wire[31:0]GicDs;
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30],OeVMD2[29:0]};6'b10????:FeVMD2<={5'd24,JeVMD2[30],20'd0,NeVMD2};6'b11????:
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assign GicDs=yicDs[31:0];always@(posedge i_clk)if((micDs)&&(~EicDs))begin if(
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FeVMD2<={5'd24,JeVMD2[30],20'd0,NeVMD2};default:FeVMD2<=JeVMD2;endcase
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yicDs[35:32]!=4'd2)begin FicDs<=yicDs;end else if(GicDs[31:6]==26'd0)FicDs<={
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endmodule module teVMD2(i_clk,QeVMD2,ReVMD2,SeVMD2,TeVMD2,UeVMD2,VeVMD2,WeVMD2
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6'd12,GicDs[5:0],24'd0};else if(GicDs[31:12]==20'd0)FicDs<={6'd13,GicDs[11:0],
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);parameter BW=66,LGFLEN=10;input i_clk,QeVMD2;input ReVMD2;input[(BW-1):0]
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18'd0};else if(GicDs[31:18]==14'd0)FicDs<={6'd14,GicDs[17:0],12'd0};else if(
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SeVMD2;input TeVMD2;output reg[(BW-1):0]UeVMD2;output reg VeVMD2;output wire
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GicDs[31:24]==8'd0)FicDs<={6'd15,GicDs[23:0],6'd0};else begin FicDs<=yicDs;end
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WeVMD2;localparam XeVMD2=(1<<LGFLEN);reg[(BW-1):0]YeVMD2[0:(XeVMD2-1)];reg[(
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end initial EicDs=1'd0;always@(posedge i_clk)if((micDs)&&(~EicDs))EicDs<=micDs
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LGFLEN-1):0]ZeVMD2,afVMD2;reg bfVMD2;initial bfVMD2=1'd0;always@(posedge i_clk
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;else if(~AicDs)EicDs<=1'd0;wire HicDs;assign HicDs=(EicDs)&&(~AicDs);reg IicDs
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)if(QeVMD2)bfVMD2<=1'd0;else if(TeVMD2)bfVMD2<=(bfVMD2)&&(ReVMD2);else if(
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;always@(posedge i_clk)IicDs<=EicDs;wire[35:0]JicDs;assign JicDs=FicDs;reg[(
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ReVMD2)bfVMD2<=(ZeVMD2+2==afVMD2);else if(ZeVMD2+1==afVMD2)bfVMD2<=1'd1;initial
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DicDs-1):0]KicDs;reg LicDs,MicDs;always@(posedge i_clk)if(HicDs)begin if(zicDs
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ZeVMD2=0;always@(posedge i_clk)if(QeVMD2)ZeVMD2<={(LGFLEN){1'd0}};else if(
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[35:33]==3'd1)KicDs<=0;else if(zicDs[35:33]==3'd7)KicDs<=KicDs+{{(DicDs-1){1'd0
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ReVMD2)begin if((TeVMD2)||(~bfVMD2))ZeVMD2<=ZeVMD2+{{(LGFLEN-1){1'd0}},1'd1};
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}},1'd1};end always@(posedge i_clk)if((HicDs)&&(zicDs[35:33]==3'd1))MicDs<=1'd0
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end always@(posedge i_clk)if(ReVMD2)YeVMD2[ZeVMD2]<=SeVMD2;reg cfVMD2;initial
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;else if(KicDs==10'd1023)MicDs<=1'd1;reg[31:0]NicDs[0:((1<<DicDs)-1)];always@(
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cfVMD2=1'd0;always@(posedge i_clk)if(QeVMD2)cfVMD2<=1'd0;else if(ReVMD2)cfVMD2
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posedge i_clk)NicDs[KicDs]<={JicDs[32:31],JicDs[29:0]};reg[(DicDs-1):0]OicDs;
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<=(cfVMD2)&&(TeVMD2);else if(TeVMD2)cfVMD2<=(afVMD2+1==ZeVMD2);else cfVMD2<=(
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wire[(DicDs-1):0]PicDs;assign PicDs=OicDs-{{(DicDs-1){1'd0}},1'd1};initial
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afVMD2==ZeVMD2);initial afVMD2=0;always@(posedge i_clk)if(QeVMD2)afVMD2<={(
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OicDs=0;always@(posedge i_clk)if((HicDs)||(~EicDs))OicDs<=KicDs+{(DicDs){1'd1}
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LGFLEN){1'd0}};else if(TeVMD2)begin if((ReVMD2)||(~cfVMD2))afVMD2<=afVMD2+{{(
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};else if((PicDs!=KicDs)&&(~QicDs)&&((~PicDs[DicDs-1])||(MicDs)))OicDs<=PicDs;
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LGFLEN-1){1'd0}},1'd1};end always@(posedge i_clk)UeVMD2<=YeVMD2[(TeVMD2)?(
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reg[(BicDs-1):0]RicDs;reg[(DicDs-1):0]SicDs;always@(posedge i_clk)begin RicDs
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afVMD2+{{(LGFLEN-1){1'd0}},1'd1}):(afVMD2)];wire[(LGFLEN-1):0]dfVMD2;assign
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<=NicDs[OicDs];SicDs<=OicDs;end reg QicDs;reg[9:0]TicDs;always@(posedge i_clk)
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dfVMD2=ZeVMD2+{{(LGFLEN-1){1'd0}},1'd1};assign WeVMD2=((ReVMD2)&&(bfVMD2)&&(~
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if((HicDs)||(~EicDs)||(~IicDs))QicDs<=1'd0;else if(~QicDs)begin QicDs<=(({1'd0
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TeVMD2))||((TeVMD2)&&(cfVMD2)&&(~ReVMD2));wire[(LGFLEN-1):0]efVMD2;assign
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,SicDs}<{MicDs,KicDs}))&&(JicDs[35:33]==3'd7)&&(RicDs=={JicDs[32:31],JicDs[29:0
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efVMD2=afVMD2+{{(LGFLEN-1){1'd0}},1'd1};always@(posedge i_clk)if(QeVMD2)VeVMD2
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]});TicDs<=KicDs-SicDs;end wire[(DicDs-1):0]UicDs;wire[9:0]VicDs;wire[2:0]WicDs
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<=1'd0;else VeVMD2<=(~TeVMD2)&&(ZeVMD2!=afVMD2)||(TeVMD2)&&(ZeVMD2!=efVMD2);
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;assign UicDs=TicDs;assign WicDs=TicDs[2:0]-3'd2;assign VicDs=TicDs-10'd10;
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endmodule module yeVMD2(i_clk,QeVMD2,CeVMD2,ffVMD2,gfVMD2,hfVMD2,ifVMD2,EeVMD2
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initial LicDs=1'd0;reg[(CicDs-1):0]XicDs;always@(posedge i_clk)begin if((~EicDs
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,jfVMD2,i_tx_busy,kfVMD2);input i_clk,QeVMD2;input CeVMD2;input[35:0]ffVMD2;
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)||(~IicDs)||(HicDs))LicDs<=1'd0;else if(LicDs);else if((QicDs)&&(TicDs<10'd521
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input gfVMD2,hfVMD2,ifVMD2;output wire EeVMD2;output wire[7:0]jfVMD2;input
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))begin if(TicDs==10'd1)XicDs[35:30]<={5'd3,JicDs[30]};else if(UicDs<10'd10)
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i_tx_busy;output wire kfVMD2;wire lfVMD2,mfVMD2,nfVMD2,ofVMD2;wire[35:0]pfVMD2
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XicDs[35:30]<={2'd2,WicDs,JicDs[30]};else XicDs[35:24]<={2'd1,VicDs[8:6],JicDs
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;wire qfVMD2,rfVMD2,sfVMD2,tfVMD2,ufVMD2,vfVMD2,wfVMD2,xfVMD2;wire[35:0]yfVMD2
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[30],VicDs[5:0]};LicDs<=1'd1;end else XicDs<=JicDs;end assign oicDs=EicDs;
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,zfVMD2;wire[6:0]AfVMD2,BfVMD2;assign lfVMD2=(nfVMD2)&&(~rfVMD2);teVMD2#(36,10
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assign zicDs=(LicDs)?(XicDs):(FicDs);endmodule
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)CfVMD2(i_clk,QeVMD2,CeVMD2,ffVMD2,lfVMD2,pfVMD2,nfVMD2,ofVMD2);assign kfVMD2=
|
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ofVMD2;DfVMD2 EfVMD2(i_clk,lfVMD2,pfVMD2,gfVMD2,ifVMD2,hfVMD2,qfVMD2,yfVMD2,
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module YicDs(i_clk,micDs,ZicDs,oicDs,ajcDs);input i_clk,micDs;input[35:0]ZicDs
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rfVMD2,wfVMD2);assign wfVMD2=sfVMD2;FfVMD2 GfVMD2(i_clk,qfVMD2,yfVMD2,sfVMD2,
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;output reg oicDs;output reg[35:0]ajcDs;wire bjcDs=(ZicDs[35:33]==3'd3);reg[7:0
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zfVMD2,mfVMD2);HfVMD2 IfVMD2(i_clk,sfVMD2,zfVMD2,vfVMD2,tfVMD2,AfVMD2,mfVMD2);
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]cjcDs;initial cjcDs=8'd0;always@(posedge i_clk)if((micDs)&&(bjcDs))cjcDs<=
|
JfVMD2 KfVMD2(i_clk,tfVMD2,AfVMD2,ufVMD2,BfVMD2,(gfVMD2||ifVMD2||nfVMD2||rfVMD2
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cjcDs+8'd1;reg[31:0]NicDs[0:255];always@(posedge i_clk)if(micDs)NicDs[cjcDs]<=
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),xfVMD2,vfVMD2);LfVMD2 MfVMD2(i_clk,ufVMD2,BfVMD2,EeVMD2,jfVMD2,xfVMD2,
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{ZicDs[32:31],ZicDs[29:0]};reg[35:0]JicDs;always@(posedge i_clk)if(micDs)JicDs
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i_tx_busy);endmodule module NfVMD2(i_clk,CeVMD2,OfVMD2,EeVMD2,PfVMD2,QfVMD2);
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<=ZicDs;reg[7:0]djcDs;always@(posedge i_clk)djcDs=cjcDs-{JicDs[32:31],JicDs[29
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input i_clk,CeVMD2;input[7:0]OfVMD2;output reg EeVMD2,PfVMD2;output reg[5:0]
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:24]};reg[24:0]ejcDs;always@(posedge i_clk)case(JicDs[32:30])3'd0:ejcDs<={19'd0
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QfVMD2;always@(posedge i_clk)EeVMD2<=CeVMD2;always@(posedge i_clk)begin PfVMD2
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,JicDs[29:24]};3'd2:ejcDs<={13'd0,JicDs[29:18]};3'd4:ejcDs<={7'd0,JicDs[29:12]
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<=1'd1;QfVMD2<=6'd0;if((OfVMD2>=8'd48)&&(OfVMD2<=8'd57))QfVMD2<={2'd0,OfVMD2[3
|
};3'd6:ejcDs<={1'd0,JicDs[29:6]};3'd1:ejcDs<={{(19){JicDs[29]}},JicDs[29:24]};
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:0]};else if((OfVMD2>=8'd65)&&(OfVMD2<=8'd90))QfVMD2<=(OfVMD2[5:0]-6'd1+6'd10)
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3'd3:ejcDs<={{(13){JicDs[29]}},JicDs[29:18]};3'd5:ejcDs<={{(7){JicDs[29]}},
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;else if((OfVMD2>=8'd97)&&(OfVMD2<=8'd122))QfVMD2<=(OfVMD2[5:0]+6'd3);else if(
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JicDs[29:12]};3'd7:ejcDs<={{(1){JicDs[29]}},JicDs[29:6]};endcase wire[31:0]
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OfVMD2==8'd64)QfVMD2<=6'd62;else if(OfVMD2==8'd37)QfVMD2<=6'd63;else PfVMD2<=
|
GicDs;assign GicDs={{(7){ejcDs[24]}},ejcDs};reg[9:0]fjcDs;always@(posedge i_clk
|
1'd0;end endmodule module JfVMD2(i_clk,CeVMD2,RfVMD2,EeVMD2,SfVMD2,ifVMD2,
|
)if(~JicDs[34])fjcDs<=10'd1+{6'd0,JicDs[33:31]};else fjcDs<=10'd8+{1'd0,JicDs[
|
i_tx_busy,TfVMD2);input i_clk,CeVMD2;input[6:0]RfVMD2;output reg EeVMD2;output
|
33:31],JicDs[29:24]};reg[31:0]RicDs;always@(posedge i_clk)RicDs<=NicDs[djcDs];
|
reg[6:0]SfVMD2;input ifVMD2;input i_tx_busy;output wire TfVMD2;reg UfVMD2,
|
reg[2:0]IicDs;initial IicDs=0;always@(posedge i_clk)IicDs<={IicDs[1:0],micDs};
|
VfVMD2;initial UfVMD2=1'd1;initial VfVMD2=1'd1;always@(posedge i_clk)if((~
|
always@(posedge i_clk)oicDs<=IicDs[2];always@(posedge i_clk)if(JicDs[35:30]==
|
i_tx_busy)&&(EeVMD2))UfVMD2<=(SfVMD2[6]);always@(posedge i_clk)if((CeVMD2)&&(~
|
6'd46)ajcDs<=JicDs;else casez(JicDs[35:30])6'b001??0:ajcDs<={4'd0,GicDs[31:0]}
|
TfVMD2))VfVMD2<=(RfVMD2[6]);reg[6:0]WfVMD2;initial WfVMD2=7'd0;always@(posedge
|
;6'b001??1:ajcDs<={3'd1,GicDs[31:30],1'd1,GicDs[29:0]};6'b010???:ajcDs<={3'd3,
|
i_clk)if((~i_tx_busy)&&(EeVMD2))begin if(SfVMD2[6])WfVMD2<=0;else WfVMD2<=
|
RicDs[31:30],JicDs[30],RicDs[29:0]};6'b10????:ajcDs<={5'd24,JicDs[30],20'd0,
|
WfVMD2+7'd1;end reg XfVMD2;initial XfVMD2=1'd0;always@(posedge i_clk)XfVMD2<=(
|
fjcDs};6'b11????:ajcDs<={5'd24,JicDs[30],20'd0,fjcDs};default:ajcDs<=JicDs;
|
WfVMD2>7'd72);initial EeVMD2=1'd0;always@(posedge i_clk)if((CeVMD2)&&(~TfVMD2)
|
endcase endmodule
|
)begin EeVMD2<=(XfVMD2)||(~RfVMD2[6]);SfVMD2<=RfVMD2;end else if(~TfVMD2)begin
|
|
EeVMD2<=(~i_tx_busy)&&(~ifVMD2)&&(~UfVMD2)&&(VfVMD2);SfVMD2<=7'd64;end else if
|
module gjcDs(i_clk,micDs,ZicDs,i_tx_busy,oicDs,picDs,ricDs);input i_clk,micDs;
|
(~i_tx_busy)EeVMD2<=1'd0;reg YfVMD2;initial YfVMD2=1'd0;always@(posedge i_clk)
|
input[35:0]ZicDs;input i_tx_busy;output reg oicDs;output reg[6:0]picDs;output
|
YfVMD2<=(EeVMD2);assign TfVMD2=(YfVMD2)||(EeVMD2);endmodule module HfVMD2(i_clk
|
reg ricDs;wire[2:0]hjcDs;assign hjcDs=(ZicDs[35:33]==3'd0)?3'd1:(ZicDs[35:32]
|
,CeVMD2,DeVMD2,i_tx_busy,EeVMD2,SfVMD2,TfVMD2);input i_clk,CeVMD2;input[35:0]
|
==4'd2)?3'd6:(ZicDs[35:32]==4'd3)?(3'd2+{1'd0,ZicDs[31:30]}):(ZicDs[35:34]==
|
DeVMD2;input i_tx_busy;output reg EeVMD2;output reg[6:0]SfVMD2;output reg
|
2'd1)?3'd2:(ZicDs[35:34]==2'd2)?3'd1:3'd6;reg ijcDs;reg[2:0]jjcDs;reg[29:0]
|
TfVMD2;wire[2:0]ZfVMD2;assign ZfVMD2=(DeVMD2[35:33]==3'd0)?3'd1:(DeVMD2[35:32]
|
JicDs;initial oicDs=1'd0;initial ricDs=1'd0;initial ijcDs=1'd0;always@(posedge
|
==4'd2)?3'd6:(DeVMD2[35:32]==4'd3)?(3'd2+{1'd0,DeVMD2[31:30]}):(DeVMD2[35:34]
|
i_clk)if((micDs)&&(~ricDs))begin jjcDs<=hjcDs-3'd1;JicDs<=ZicDs[29:0];oicDs<=
|
==2'd1)?3'd2:(DeVMD2[35:34]==2'd2)?3'd1:3'd6;reg agVMD2;reg[2:0]bgVMD2;reg[29:0
|
1'd1;picDs<={1'd0,ZicDs[35:30]};ricDs<=1'd1;ijcDs<=1'd1;end else if((oicDs)&&(
|
]JeVMD2;initial EeVMD2=1'd0;initial TfVMD2=1'd0;initial agVMD2=1'd0;always@(
|
i_tx_busy))begin ricDs<=1'd1;ijcDs<=1'd1;end else if(oicDs)oicDs<=1'd0;else if
|
posedge i_clk)if((CeVMD2)&&(~TfVMD2))begin bgVMD2<=ZfVMD2-3'd1;JeVMD2<=DeVMD2[
|
(jjcDs>0)begin oicDs<=1'd1;picDs<={1'd0,JicDs[29:24]};JicDs[29:6]<=JicDs[23:0]
|
29:0];EeVMD2<=1'd1;SfVMD2<={1'd0,DeVMD2[35:30]};TfVMD2<=1'd1;agVMD2<=1'd1;end
|
;jjcDs<=jjcDs-3'd1;ricDs<=1'd1;ijcDs<=1'd1;end else if(~picDs[6])begin oicDs<=
|
else if((EeVMD2)&&(i_tx_busy))begin TfVMD2<=1'd1;agVMD2<=1'd1;end else if(
|
1'd1;picDs<=7'd64;ricDs<=1'd1;ijcDs<=1'd1;end else begin ijcDs<=1'd0;ricDs<=(
|
EeVMD2)EeVMD2<=1'd0;else if(bgVMD2>0)begin EeVMD2<=1'd1;SfVMD2<={1'd0,JeVMD2[29
|
ijcDs);end endmodule
|
:24]};JeVMD2[29:6]<=JeVMD2[23:0];bgVMD2<=bgVMD2-3'd1;TfVMD2<=1'd1;agVMD2<=1'd1
|
|
;end else if(~SfVMD2[6])begin EeVMD2<=1'd1;SfVMD2<=7'd64;TfVMD2<=1'd1;agVMD2<=
|
module ficDs(i_clk,kjcDs,micDs,yicDs,ricDs,o_wb_cyc,o_wb_stb,o_wb_we,o_wb_addr
|
1'd1;end else begin agVMD2<=1'd0;TfVMD2<=(agVMD2);end endmodule module DfVMD2(
|
,o_wb_data,i_wb_ack,i_wb_stall,i_wb_err,i_wb_data,oicDs,ljcDs);input i_clk,
|
i_clk,CeVMD2,ffVMD2,cgVMD2,dgVMD2,hfVMD2,EeVMD2,egVMD2,TfVMD2,i_tx_busy);input
|
kjcDs;input micDs;input[35:0]yicDs;output reg ricDs;output reg o_wb_cyc,
|
i_clk;input CeVMD2;input[35:0]ffVMD2;input cgVMD2,dgVMD2,hfVMD2;output reg
|
o_wb_stb,o_wb_we;output reg[31:0]o_wb_addr,o_wb_data;input i_wb_ack,i_wb_stall
|
EeVMD2;output reg[35:0]egVMD2;output reg TfVMD2;input i_tx_busy;reg fgVMD2,
|
,i_wb_err;input[31:0]i_wb_data;output reg oicDs;output reg[35:0]ljcDs;wire
|
ggVMD2;initial fgVMD2=1'd0;always@(posedge i_clk)if((EeVMD2)&&(~i_tx_busy)&&(
|
mjcDs,njcDs,ojcDs,pjcDs;assign mjcDs=(micDs)&&(~ricDs);assign ojcDs=(mjcDs)&&(
|
egVMD2[35:30]==6'd4))fgVMD2<=hfVMD2;else fgVMD2<=(fgVMD2)||(hfVMD2);wire hgVMD2
|
yicDs[35:34]==2'd1);assign njcDs=(mjcDs)&&(yicDs[35:30]==6'd46);wire[31:0]qjcDs
|
;reg igVMD2;reg[35:0]jgVMD2;initial jgVMD2=36'd0;always@(posedge i_clk)if((
|
;assign qjcDs={yicDs[32:31],yicDs[29:0]};assign pjcDs=((mjcDs)&&((yicDs[35:33]
|
CeVMD2)||(EeVMD2))jgVMD2<=36'd0;else if(~jgVMD2[35])jgVMD2<=jgVMD2+36'd43;
|
!=3'd3)||(~o_wb_we))&&(yicDs[35:30]!=6'd46));reg[9:0]rjcDs,jjcDs;reg sjcDs,
|
initial igVMD2=1'd0;always@(posedge i_clk)if((EeVMD2)&&(~i_tx_busy)&&(egVMD2[35
|
tjcDs,ujcDs,vjcDs;initial tjcDs=1'd0;initial ujcDs=1'd1;always@(posedge i_clk)
|
:31]==5'd0))igVMD2<=1'd1;else if(~jgVMD2[35])igVMD2<=1'd0;assign hgVMD2=(~
|
if(kjcDs)begin oicDs<=1'd1;ljcDs<={6'd3,30'd0};tjcDs<=1'd0;o_wb_cyc<=1'd0;end
|
igVMD2)&&(jgVMD2[35]);initial EeVMD2=1'd0;initial TfVMD2=1'd0;always@(posedge
|
else if(o_wb_cyc)begin oicDs<=1'd0;if(tjcDs)begin if(njcDs)o_wb_cyc<=1'd0;
|
i_clk)if((EeVMD2)&&(i_tx_busy))begin TfVMD2<=1'd1;end else if(EeVMD2)begin
|
o_wb_stb<=1'd0;end else if((i_wb_err)||(pjcDs))begin o_wb_cyc<=(~ricDs);
|
EeVMD2<=1'd0;TfVMD2<=1'd1;end else if(TfVMD2)TfVMD2<=1'd0;else if(CeVMD2)begin
|
o_wb_stb<=1'd0;tjcDs<=1'd1;oicDs<=1'd1;ljcDs<={6'd5,30'd0};end else if((
|
egVMD2<=ffVMD2;EeVMD2<=1'd1;TfVMD2<=1'd1;end else if((fgVMD2)&&(~ggVMD2))begin
|
o_wb_stb)&&(~i_wb_stall))begin if(jjcDs!=0)jjcDs<=jjcDs-10'd1;else o_wb_stb<=
|
EeVMD2<=1'd1;egVMD2<={6'd4,30'd0};TfVMD2<=1'd1;end else if(hgVMD2)begin EeVMD2
|
1'd0;if(o_wb_we)begin oicDs<=1'd1;ljcDs<={6'd2,30'd0};end if(sjcDs)o_wb_addr<=
|
<=1'd1;TfVMD2<=1'd1;if(cgVMD2)egVMD2<={6'd1,30'd0};else egVMD2<={6'd0,30'd0};
|
o_wb_addr+32'd1;end else if(ojcDs)begin sjcDs<=yicDs[30];o_wb_data<=qjcDs;
|
end initial ggVMD2=1'd0;always@(posedge i_clk)if((fgVMD2)&&((~EeVMD2)&&(~TfVMD2
|
o_wb_stb<=1'd1;end if(njcDs)vjcDs<=1'd1;if((tjcDs)||(i_wb_err)||(pjcDs))ricDs
|
)&&(~CeVMD2)))ggVMD2<=1'd1;else if(~hfVMD2)ggVMD2<=1'd0;endmodule module kgVMD2
|
<=1'd0;else if((njcDs)||(ojcDs)||(vjcDs))ricDs<=1'd1;else if((o_wb_we)&&(
|
(i_clk,CeVMD2,lgVMD2,mgVMD2,EeVMD2,egVMD2);input i_clk,CeVMD2,lgVMD2;input[5:0
|
o_wb_stb)&&(~i_wb_stall)&&(jjcDs==0))ricDs<=1'd0;else if((o_wb_we)&&(~o_wb_stb
|
]mgVMD2;output reg EeVMD2;output reg[35:0]egVMD2;reg[2:0]bgVMD2,ngVMD2;reg[1:0
|
))ricDs<=1'd0;if((tjcDs)||(i_wb_err))begin end else if(rjcDs!=10'd0)begin if((
|
]ogVMD2;wire pgVMD2;assign pgVMD2=((bgVMD2==ngVMD2)&&(ngVMD2!=0))||((CeVMD2)&&
|
i_wb_ack)&&(~o_wb_we))begin oicDs<=1'd1;ljcDs<={3'd7,i_wb_data[31:30],sjcDs,
|
(~lgVMD2)&&(ogVMD2==2'd1));initial bgVMD2=3'd0;always@(posedge i_clk)if((CeVMD2
|
i_wb_data[29:0]};end if((i_wb_ack)&&(~ojcDs))rjcDs<=rjcDs-10'd1;else if((~
|
)&&(~lgVMD2))bgVMD2<=0;else if(pgVMD2)bgVMD2<=(CeVMD2)?3'd1:3'd0;else if(CeVMD2
|
i_wb_ack)&&(ojcDs))rjcDs<=rjcDs+10'd1;end else if(rjcDs==10'd0)begin if((~
|
)bgVMD2<=bgVMD2+3'd1;reg[35:0]qgVMD2;always@(posedge i_clk)if(pgVMD2)qgVMD2[35
|
o_wb_we)||(vjcDs)||(njcDs))o_wb_cyc<=1'd0;else if(ojcDs)begin rjcDs<=rjcDs+
|
:30]<=mgVMD2;else if(CeVMD2)case(bgVMD2)3'd0:qgVMD2[35:30]<=mgVMD2;3'd1:qgVMD2
|
10'd1;o_wb_data<=qjcDs;end end end else if(micDs)begin oicDs<=1'd0;sjcDs<=yicDs
|
[29:24]<=mgVMD2;3'd2:qgVMD2[23:18]<=mgVMD2;3'd3:qgVMD2[17:12]<=mgVMD2;3'd4:
|
[30];o_wb_we<=(~yicDs[35]);tjcDs<=1'd0;ricDs<=1'd0;vjcDs<=1'd0;if(yicDs[35:32]
|
qgVMD2[11:6]<=mgVMD2;3'd5:qgVMD2[5:0]<=mgVMD2;default:begin end endcase always
|
==4'd0)begin ujcDs<=1'd1;o_wb_addr<=yicDs[31:0];end else if(yicDs[35:33]==3'd1
|
@(posedge i_clk)if(EeVMD2)ogVMD2<=egVMD2[35:34];always@(posedge i_clk)if((
|
)begin o_wb_addr<=o_wb_addr+{yicDs[32:31],yicDs[29:0]};ujcDs<=1'd1;end else if
|
CeVMD2)&&(~lgVMD2)&&(ogVMD2==2'd1))egVMD2[35:30]<=6'd46;else egVMD2<=qgVMD2;
|
(yicDs[35:34]==2'd3)begin jjcDs<=yicDs[9:0]-10'd1;o_wb_cyc<=1'd1;o_wb_stb<=1'd1
|
initial ngVMD2=3'd0;always@(posedge i_clk)if((CeVMD2)&&(~lgVMD2))ngVMD2<=0;else
|
;rjcDs<=yicDs[9:0];ricDs<=1'd1;if(ujcDs)begin oicDs<=1'd1;ljcDs<={4'd2,
|
if((CeVMD2)&&((ngVMD2==0)||(pgVMD2)))begin if(mgVMD2[5:4]==2'd3)ngVMD2<=3'd2;
|
o_wb_addr};ujcDs<=1'd0;end end else if(~yicDs[35])begin o_wb_cyc<=1'd1;o_wb_stb
|
else if(mgVMD2[5:4]==2'd2)ngVMD2<=3'd1;else if(mgVMD2[5:3]==3'd2)ngVMD2<=3'd2;
|
<=1'd1;o_wb_data<=qjcDs;ricDs<=1'd1;jjcDs<=10'd0;ujcDs<=1'd1;rjcDs<=10'd1;end
|
else if(mgVMD2[5:3]==3'd1)ngVMD2<=3'd2+{1'd0,mgVMD2[2:1]};else ngVMD2<=3'd6;end
|
end else begin tjcDs<=1'd0;ricDs<=1'd0;oicDs<=1'd0;end endmodule
|
else if(pgVMD2)ngVMD2<=0;always@(posedge i_clk)EeVMD2<=pgVMD2;endmodule module
|
|
FfVMD2(i_clk,CeVMD2,ffVMD2,EeVMD2,rgVMD2,dgVMD2);parameter DW=32,CW=36,TBITS=10
|
module dicDs(i_clk,kjcDs,wjcDs,xjcDs,yjcDs,zjcDs,AjcDs,BjcDs);parameter CjcDs=
|
;input i_clk,CeVMD2;input[(CW-1):0]ffVMD2;output wire EeVMD2;output wire[(CW-1
|
66,DjcDs=10,EjcDs=(1<<DjcDs);input i_clk,kjcDs;input wjcDs;input[(CjcDs-1):0]
|
):0]rgVMD2;input dgVMD2;reg sgVMD2;reg[35:0]tgVMD2;wire[31:0]MeVMD2;assign
|
xjcDs;input yjcDs;output reg[(CjcDs-1):0]zjcDs;output reg AjcDs;output wire
|
MeVMD2=ffVMD2[31:0];always@(posedge i_clk)if((CeVMD2)&&(~sgVMD2))begin if(
|
BjcDs;reg[(CjcDs-1):0]FjcDs[0:(EjcDs-1)];reg[(DjcDs-1):0]GjcDs,HjcDs;initial
|
ffVMD2[35:32]!=4'd2)begin tgVMD2<=ffVMD2;end else if(MeVMD2[31:6]==26'd0)tgVMD2
|
GjcDs=0;always@(posedge i_clk)if(kjcDs)GjcDs<={(DjcDs){1'd0}};else if(wjcDs)
|
<={6'd12,MeVMD2[5:0],24'd0};else if(MeVMD2[31:12]==20'd0)tgVMD2<={6'd13,MeVMD2
|
begin if(GjcDs+1!=HjcDs)GjcDs<=GjcDs+{{(DjcDs-1){1'd0}},1'd1};end always@(
|
[11:0],18'd0};else if(MeVMD2[31:18]==14'd0)tgVMD2<={6'd14,MeVMD2[17:0],12'd0};
|
posedge i_clk)if(wjcDs)FjcDs[GjcDs]<=xjcDs;initial HjcDs=0;always@(posedge
|
else if(MeVMD2[31:24]==8'd0)tgVMD2<={6'd15,MeVMD2[23:0],6'd0};else begin tgVMD2
|
i_clk)if(kjcDs)HjcDs<={(DjcDs){1'd0}};else if(yjcDs)begin if(GjcDs!=HjcDs)HjcDs
|
<=ffVMD2;end end initial sgVMD2=1'd0;always@(posedge i_clk)if((CeVMD2)&&(~
|
<=HjcDs+{{(DjcDs-1){1'd0}},1'd1};end always@(posedge i_clk)zjcDs<=FjcDs[(yjcDs
|
sgVMD2))sgVMD2<=CeVMD2;else if(~dgVMD2)sgVMD2<=1'd0;wire ugVMD2;assign ugVMD2=
|
)?(HjcDs+{{(DjcDs-1){1'd0}},1'd1}):(HjcDs)];wire[(DjcDs-1):0]IjcDs;assign IjcDs
|
(sgVMD2)&&(~dgVMD2);reg PeVMD2;always@(posedge i_clk)PeVMD2<=sgVMD2;wire[35:0]
|
=GjcDs+{{(DjcDs-1){1'd0}},1'd1};assign BjcDs=((wjcDs)&&(IjcDs==HjcDs))||((yjcDs
|
JeVMD2;assign JeVMD2=tgVMD2;reg[(TBITS-1):0]vgVMD2;reg wgVMD2;always@(posedge
|
)&&(GjcDs==HjcDs));wire[(DjcDs-1):0]JjcDs;assign JjcDs=HjcDs+{{(DjcDs-1){1'd0}
|
i_clk)if(ugVMD2)begin if(rgVMD2[35:33]==3'd1)vgVMD2<=0;else if(rgVMD2[35:33]==
|
},1'd1};always@(posedge i_clk)if(kjcDs)AjcDs<=1'd0;else AjcDs<=(~yjcDs)&&(GjcDs
|
3'd7)vgVMD2<=vgVMD2+{{(TBITS-1){1'd0}},1'd1};end always@(posedge i_clk)if((
|
!=HjcDs)||(yjcDs)&&(GjcDs!=JjcDs);endmodule
|
ugVMD2)&&(rgVMD2[35:33]==3'd1))wgVMD2<=1'd0;else if(vgVMD2==10'd1023)wgVMD2<=
|
|
1'd1;reg[31:0]IeVMD2[0:((1<<TBITS)-1)];always@(posedge i_clk)IeVMD2[vgVMD2]<={
|
module KjcDs(i_clk,micDs,yicDs,LjcDs,AicDs,MjcDs,oicDs,ljcDs,ricDs,i_tx_busy);
|
JeVMD2[32:31],JeVMD2[29:0]};reg xgVMD2,ygVMD2;reg[(TBITS-1):0]zgVMD2;reg[(TBITS
|
input i_clk;input micDs;input[35:0]yicDs;input LjcDs,AicDs,MjcDs;output reg
|
-1):0]AgVMD2;initial zgVMD2=0;initial xgVMD2=0;always@(posedge i_clk)begin
|
oicDs;output reg[35:0]ljcDs;output reg ricDs;input i_tx_busy;reg NjcDs,OjcDs;
|
ygVMD2<=((AgVMD2-vgVMD2)=={{(TBITS-1){1'd0}},1'd1});if((ugVMD2)||(~sgVMD2))
|
initial NjcDs=1'd0;always@(posedge i_clk)if((oicDs)&&(~i_tx_busy)&&(ljcDs[35:30
|
begin zgVMD2<=vgVMD2+{(TBITS){1'd1}};AgVMD2=vgVMD2+{{(TBITS-1){1'd1}},1'd0};
|
]==6'd4))NjcDs<=MjcDs;else NjcDs<=(NjcDs)||(MjcDs);wire PjcDs;reg QjcDs;reg[35
|
xgVMD2<=1'd0;end else if((~xgVMD2)&&(~BgVMD2)&&((~AgVMD2[TBITS-1])||(wgVMD2)))
|
:0]RjcDs;initial RjcDs=36'd0;always@(posedge i_clk)if((micDs)||(oicDs))RjcDs<=
|
begin zgVMD2<=AgVMD2;AgVMD2=AgVMD2-{{(TBITS-1){1'd0}},1'd1};xgVMD2<=ygVMD2;end
|
36'd0;else if(~RjcDs[35])RjcDs<=RjcDs+36'd43;initial QjcDs=1'd0;always@(posedge
|
end reg[1:0]CgVMD2;reg DgVMD2,EgVMD2;reg[(DW-1):0]OeVMD2;reg[(TBITS-1):0]FgVMD2
|
i_clk)if((oicDs)&&(~i_tx_busy)&&(ljcDs[35:31]==5'd0))QjcDs<=1'd1;else if(~RjcDs
|
,GgVMD2,HgVMD2;always@(posedge i_clk)begin OeVMD2<=IeVMD2[zgVMD2];FgVMD2<=
|
[35])QjcDs<=1'd0;assign PjcDs=(~QjcDs)&&(RjcDs[35]);initial oicDs=1'd0;initial
|
zgVMD2;DgVMD2<=(OeVMD2=={JeVMD2[32:31],JeVMD2[29:0]});GgVMD2<=FgVMD2;HgVMD2<=
|
ricDs=1'd0;always@(posedge i_clk)if((oicDs)&&(i_tx_busy))begin ricDs<=1'd1;end
|
vgVMD2-FgVMD2;EgVMD2<=({1'd0,FgVMD2}<{wgVMD2,vgVMD2})&&(FgVMD2!=vgVMD2);end
|
else if(oicDs)begin oicDs<=1'd0;ricDs<=1'd1;end else if(ricDs)ricDs<=1'd0;else
|
always@(posedge i_clk)if((ugVMD2)||(~sgVMD2))CgVMD2<=0;else CgVMD2<={CgVMD2[0]
|
if(micDs)begin ljcDs<=yicDs;oicDs<=1'd1;ricDs<=1'd1;end else if((NjcDs)&&(~
|
,1'd1};reg BgVMD2;reg[(TBITS-1):0]IgVMD2;always@(posedge i_clk)if((ugVMD2)||(~
|
OjcDs))begin oicDs<=1'd1;ljcDs<={6'd4,30'd0};ricDs<=1'd1;end else if(PjcDs)
|
sgVMD2)||(~PeVMD2))BgVMD2<=1'd0;else if(~BgVMD2)begin BgVMD2<=(EgVMD2)&&(DgVMD2
|
begin oicDs<=1'd1;ricDs<=1'd1;if(LjcDs)ljcDs<={6'd1,30'd0};else ljcDs<={6'd0,
|
)&&(JeVMD2[35:33]==3'd7)&&(CgVMD2==2'd3);end reg JgVMD2,KgVMD2,LgVMD2;always@(
|
30'd0};end initial OjcDs=1'd0;always@(posedge i_clk)if((NjcDs)&&((~oicDs)&&(~
|
posedge i_clk)if(~BgVMD2)begin IgVMD2<=HgVMD2;LgVMD2<=(HgVMD2<10'd1313);JgVMD2
|
ricDs)&&(~micDs)))OjcDs<=1'd1;else if(~MjcDs)OjcDs<=1'd0;endmodule
|
<=(HgVMD2==10'd1);KgVMD2<=(HgVMD2<10'd10);end wire[(TBITS-1):0]MgVMD2;wire[9:0
|
|
]NgVMD2;wire[2:0]OgVMD2;assign MgVMD2=IgVMD2;assign OgVMD2=IgVMD2[2:0]-3'd2;
|
module ShcDs(i_clk,micDs,SjcDs,oicDs,ljcDs);input i_clk,micDs;input[7:0]SjcDs;
|
assign NgVMD2=IgVMD2-10'd10;reg[(CW-1):0]PgVMD2;always@(posedge i_clk)begin if
|
output wire oicDs;output wire[35:0]ljcDs;wire TjcDs,UjcDs;wire[5:0]VjcDs;WjcDs
|
((~sgVMD2)||(~PeVMD2)||(ugVMD2))begin PgVMD2<=JeVMD2;end else if((BgVMD2)&&(
|
XjcDs(i_clk,micDs,SjcDs,TjcDs,UjcDs,VjcDs);wire YjcDs;wire[35:0]ZjcDs;akcDs
|
LgVMD2))begin PgVMD2<=JeVMD2;if(JgVMD2)PgVMD2[35:30]<={5'd3,JeVMD2[30]};else if
|
bkcDs(i_clk,TjcDs,UjcDs,VjcDs,YjcDs,ZjcDs);
|
(KgVMD2)PgVMD2[35:30]<={2'd2,OgVMD2,JeVMD2[30]};else PgVMD2[35:24]<={2'd1,
|
`ifdef ckcDs
|
NgVMD2[8:6],JeVMD2[30],NgVMD2[5:0]};end else PgVMD2<=JeVMD2;end assign EeVMD2=
|
assign oicDs=YjcDs;assign ljcDs=ZjcDs;
|
sgVMD2;assign rgVMD2=(PeVMD2)?(PgVMD2):(tgVMD2);endmodule module veVMD2(i_clk,
|
`else
|
QeVMD2,CeVMD2,ffVMD2,TfVMD2,o_wb_cyc,o_wb_stb,o_wb_we,o_wb_addr,o_wb_data,
|
YicDs dkcDs(i_clk,YjcDs,ZjcDs,oicDs,ljcDs);
|
i_wb_ack,i_wb_stall,i_wb_err,i_wb_data,EeVMD2,egVMD2);input i_clk,QeVMD2;input
|
`endif
|
CeVMD2;input[35:0]ffVMD2;output wire TfVMD2;output reg o_wb_cyc;output reg
|
endmodule
|
o_wb_stb;output reg o_wb_we;output reg[31:0]o_wb_addr,o_wb_data;input i_wb_ack
|
|
,i_wb_stall,i_wb_err;input[31:0]i_wb_data;output reg EeVMD2;output reg[35:0]
|
module iicDs(i_clk,kjcDs,micDs,yicDs,ekcDs,MjcDs,qicDs,oicDs,fkcDs,i_tx_busy,
|
egVMD2;wire QgVMD2,RgVMD2,SgVMD2,TgVMD2;assign QgVMD2=(CeVMD2)&&(~TfVMD2);
|
gkcDs);input i_clk,kjcDs;input micDs;input[35:0]yicDs;input ekcDs,MjcDs,qicDs;
|
assign SgVMD2=(QgVMD2)&&(ffVMD2[35:34]==2'd1);assign RgVMD2=(QgVMD2)&&(ffVMD2[
|
output wire oicDs;output wire[7:0]fkcDs;input i_tx_busy;output wire gkcDs;wire
|
35:30]==6'd46);wire[31:0]UgVMD2;assign UgVMD2={ffVMD2[32:31],ffVMD2[29:0]};
|
hkcDs,ikcDs,jkcDs,kkcDs;wire[35:0]lkcDs;wire YjcDs,mkcDs,nkcDs,okcDs,pkcDs,
|
assign TgVMD2=((QgVMD2)&&(ffVMD2[35:33]!=3'd3)&&(ffVMD2[35:30]!=6'd46));reg[2:0
|
qkcDs,rkcDs,skcDs;wire[35:0]tkcDs,ukcDs;wire[6:0]vkcDs,wkcDs;
|
]VgVMD2;reg[9:0]WgVMD2,bgVMD2;reg XgVMD2,YgVMD2,ZgVMD2,ahVMD2,bhVMD2;reg chVMD2
|
`ifdef xkcDs
|
;initial YgVMD2=1'd1;initial VgVMD2=3'd0;initial EeVMD2=1'd0;always@(posedge
|
assign hkcDs=micDs;assign lkcDs=yicDs;assign kkcDs=1'd0;
|
i_clk)if(QeVMD2)begin VgVMD2<=3'd0;EeVMD2<=1'd1;egVMD2<={6'd3,i_wb_data[29:0]}
|
`else
|
;o_wb_cyc<=1'd0;o_wb_stb<=1'd0;end else case(VgVMD2)3'd0:begin o_wb_cyc<=1'd0;
|
assign hkcDs=(jkcDs)&&(~mkcDs);dicDs#(36,10)ykcDs(i_clk,kjcDs,micDs,yicDs,
|
o_wb_stb<=1'd0;EeVMD2<=1'd0;XgVMD2<=ffVMD2[30];o_wb_we<=(~ffVMD2[35]);egVMD2<=
|
hkcDs,lkcDs,jkcDs,kkcDs);
|
{4'd2,o_wb_addr};o_wb_we<=(ffVMD2[35:34]!=2'd3);o_wb_data<=UgVMD2;if(CeVMD2)
|
`endif
|
begin casez(ffVMD2[35:32])4'd0:begin o_wb_addr<=ffVMD2[31:0];end 4'b001?:begin
|
assign gkcDs=kkcDs;KjcDs zkcDs(i_clk,hkcDs,lkcDs,ekcDs,qicDs,MjcDs,YjcDs,tkcDs
|
o_wb_addr<=o_wb_addr+{ffVMD2[32:31],ffVMD2[29:0]};end 4'b01??:begin VgVMD2<=
|
,mkcDs,rkcDs);
|
3'd2;o_wb_cyc<=1'd1;o_wb_stb<=1'd1;end 4'b11??:begin if(YgVMD2)EeVMD2<=1'd1;
|
`ifdef AkcDs
|
VgVMD2<=3'd1;o_wb_cyc<=1'd1;o_wb_stb<=1'd1;end default:;endcase end end 3'd1:
|
assign nkcDs=YjcDs;assign ukcDs=tkcDs;assign rkcDs=ikcDs;
|
begin o_wb_cyc<=1'd1;o_wb_stb<=1'd1;if(i_wb_err)VgVMD2<=3'd0;EeVMD2<=(i_wb_err
|
`else
|
)||(i_wb_ack);if(i_wb_err)egVMD2<={6'd5,i_wb_data[29:0]};else egVMD2<={3'd7,
|
assign rkcDs=nkcDs;xicDs BkcDs(i_clk,YjcDs,tkcDs,nkcDs,ukcDs,ikcDs);
|
i_wb_data[31:30],XgVMD2,i_wb_data[29:0]};if((XgVMD2)&&(~i_wb_stall))o_wb_addr
|
`endif
|
<=o_wb_addr+32'd1;if(~i_wb_stall)begin if((chVMD2)||(ZgVMD2))begin VgVMD2<=3'd3
|
gjcDs CkcDs(i_clk,nkcDs,ukcDs,qkcDs,okcDs,vkcDs,ikcDs);licDs DkcDs(i_clk,okcDs
|
;o_wb_stb<=1'd0;end end end 3'd2:begin o_wb_cyc<=1'd1;o_wb_stb<=1'd1;if(
|
,vkcDs,pkcDs,wkcDs,(ekcDs||qicDs||jkcDs||mkcDs),skcDs,qkcDs);EkcDs FkcDs(i_clk
|
i_wb_err)egVMD2<={6'd5,i_wb_data[29:0]};else egVMD2<={6'd2,i_wb_data[29:0]};if
|
,pkcDs,wkcDs,oicDs,fkcDs,skcDs,i_tx_busy);endmodule
|
((XgVMD2)&&(~i_wb_stall))o_wb_addr<=o_wb_addr+32'd1;EeVMD2<=(i_wb_err)||(~
|
|
i_wb_stall);if(i_wb_err)begin VgVMD2<=3'd5;o_wb_cyc<=1'd0;o_wb_stb<=1'd0;end
|
module akcDs(i_clk,micDs,GkcDs,HkcDs,oicDs,ljcDs);input i_clk,micDs,GkcDs;input
|
else if(~i_wb_stall)begin VgVMD2<=3'd4;o_wb_stb<=1'd0;end end 3'd3:begin
|
[5:0]HkcDs;output reg oicDs;output reg[35:0]ljcDs;reg[2:0]jjcDs,IkcDs;wire
|
o_wb_cyc<=1'd1;o_wb_stb<=1'd0;if(i_wb_err)egVMD2<={6'd5,i_wb_data[29:0]};else
|
JkcDs;assign JkcDs=((jjcDs==IkcDs)&&(IkcDs!=0))||((micDs)&&(~GkcDs)&&(KkcDs==
|
egVMD2<={3'd7,i_wb_data[31:30],XgVMD2,i_wb_data[29:0]};EeVMD2<=(((i_wb_ack)&&(
|
2'd1));initial jjcDs=3'd0;always@(posedge i_clk)if((micDs)&&(~GkcDs))jjcDs<=0;
|
~o_wb_we))||(i_wb_err));if(((ahVMD2)&&(i_wb_ack))||(bhVMD2)||(i_wb_err))begin
|
else if(JkcDs)jjcDs<=(micDs)?3'd1:3'd0;else if(micDs)jjcDs<=jjcDs+3'd1;reg[35:0
|
o_wb_cyc<=1'd0;VgVMD2<=3'd0;end end 3'd4:begin egVMD2<={6'd5,i_wb_data[29:0]};
|
]LkcDs;always@(posedge i_clk)if(JkcDs)LkcDs[35:30]<=HkcDs;else if(micDs)case(
|
EeVMD2<=(i_wb_err)||(TgVMD2);o_wb_data<=UgVMD2;o_wb_cyc<=1'd1;o_wb_stb<=1'd0;if
|
jjcDs)3'd0:LkcDs[35:30]<=HkcDs;3'd1:LkcDs[29:24]<=HkcDs;3'd2:LkcDs[23:18]<=
|
(TgVMD2)begin o_wb_cyc<=1'd0;VgVMD2<=3'd0;end else if(i_wb_err)begin o_wb_cyc
|
HkcDs;3'd3:LkcDs[17:12]<=HkcDs;3'd4:LkcDs[11:6]<=HkcDs;3'd5:LkcDs[5:0]<=HkcDs;
|
<=1'd0;VgVMD2<=3'd5;end else if(SgVMD2)begin VgVMD2<=3'd2;o_wb_stb<=1'd1;end
|
default:begin end endcase reg[1:0]KkcDs;always@(posedge i_clk)if(oicDs)KkcDs<=
|
else if(RgVMD2)VgVMD2<=3'd3;end 3'd5:begin o_wb_cyc<=1'd0;o_wb_stb<=1'd0;egVMD2
|
ljcDs[35:34];always@(posedge i_clk)if((micDs)&&(~GkcDs)&&(KkcDs==2'd1))ljcDs[35
|
<={6'd5,i_wb_data[29:0]};EeVMD2<=(TgVMD2);if((RgVMD2)||(TgVMD2))VgVMD2<=3'd0;
|
:30]<=6'd46;else ljcDs<=LkcDs;initial IkcDs=3'd0;always@(posedge i_clk)if((
|
end default:begin EeVMD2<=1'd1;egVMD2<={6'd3,i_wb_data[29:0]};VgVMD2<=3'd0;
|
micDs)&&(~GkcDs))IkcDs<=0;else if((micDs)&&((IkcDs==0)||(JkcDs)))begin if(HkcDs
|
o_wb_cyc<=1'd0;o_wb_stb<=1'd0;end endcase assign TfVMD2=(VgVMD2!=3'd0)&&(VgVMD2
|
[5:4]==2'd3)IkcDs<=3'd2;else if(HkcDs[5:4]==2'd2)IkcDs<=3'd1;else if(HkcDs[5:3
|
!=3'd4)&&(VgVMD2!=3'd5);always@(posedge i_clk)if(QeVMD2)YgVMD2<=1'd1;else if((
|
]==3'd2)IkcDs<=3'd2;else if(HkcDs[5:3]==3'd1)IkcDs<=3'd2+{1'd0,HkcDs[2:1]};else
|
~o_wb_cyc)&&(CeVMD2)&&(~ffVMD2[35]))YgVMD2<=1'd1;else if(o_wb_cyc)YgVMD2<=1'd0
|
IkcDs<=3'd6;end else if(JkcDs)IkcDs<=0;always@(posedge i_clk)oicDs<=JkcDs;
|
;always@(posedge i_clk)if(~o_wb_cyc)WgVMD2<=10'd0;else if((o_wb_stb)&&(~
|
endmodule
|
i_wb_stall)&&(~i_wb_ack))WgVMD2<=WgVMD2+10'd1;else if(((~o_wb_stb)||(i_wb_stall
|
|
))&&(i_wb_ack))WgVMD2<=WgVMD2-10'd1;always@(posedge i_clk)ahVMD2<=(~o_wb_stb)
|
module EkcDs(i_clk,micDs,MkcDs,oicDs,fkcDs,ricDs,AicDs);input i_clk;input micDs
|
&&(WgVMD2==10'd1)||(o_wb_stb)&&(WgVMD2==10'd0);always@(posedge i_clk)bhVMD2<=(
|
;input[6:0]MkcDs;output reg oicDs;output reg[7:0]fkcDs;output wire ricDs;input
|
~o_wb_stb)&&(WgVMD2==10'd0);always@(posedge i_clk)if(~o_wb_stb)bgVMD2<=ffVMD2[9
|
AicDs;initial fkcDs=8'd0;always@(posedge i_clk)if((micDs)&&(~ricDs))begin if(
|
:0];else if((o_wb_stb)&&(~i_wb_stall)&&(|bgVMD2))bgVMD2<=bgVMD2-10'd1;always@(
|
MkcDs[6])fkcDs<=8'd10;else if(MkcDs[5:0]<=6'd9)fkcDs<=8'd48+{4'd0,MkcDs[3:0]};
|
posedge i_clk)begin chVMD2<=(~o_wb_cyc)&&(ffVMD2[9:0]==10'd1);ZgVMD2<=(o_wb_stb
|
else if(MkcDs[5:0]<=6'd35)fkcDs<=8'd65+{2'd0,MkcDs[5:0]}-8'd10;else if(MkcDs[5
|
)&&(bgVMD2[9:2]==8'd0)&&((~bgVMD2[1])||((~bgVMD2[0])&&(~i_wb_stall)));end
|
:0]<=6'd61)fkcDs<=8'd97+{2'd0,MkcDs[5:0]}-8'd36;else if(MkcDs[5:0]==6'd62)fkcDs
|
endmodule module jeVMD2(i_clk,CeVMD2,OfVMD2,EeVMD2,egVMD2);input i_clk,CeVMD2;
|
<=8'd64;else fkcDs<=8'd37;end always@(posedge i_clk)if((oicDs)&&(~AicDs))oicDs
|
input[7:0]OfVMD2;output wire EeVMD2;output wire[35:0]egVMD2;wire dhVMD2,ehVMD2
|
<=1'd0;else if((micDs)&&(~oicDs))oicDs<=1'd1;assign ricDs=oicDs;endmodule
|
;wire[5:0]fhVMD2;NfVMD2 ghVMD2(i_clk,CeVMD2,OfVMD2,dhVMD2,ehVMD2,fhVMD2);wire
|
|
qfVMD2;wire[35:0]hhVMD2;kgVMD2 ihVMD2(i_clk,dhVMD2,ehVMD2,fhVMD2,qfVMD2,hhVMD2
|
module WjcDs(i_clk,micDs,SjcDs,oicDs,NkcDs,OkcDs);input i_clk,micDs;input[7:0]
|
);BeVMD2 jhVMD2(i_clk,qfVMD2,hhVMD2,EeVMD2,egVMD2);endmodule module LfVMD2(
|
SjcDs;output reg oicDs,NkcDs;output reg[5:0]OkcDs;always@(posedge i_clk)oicDs
|
i_clk,CeVMD2,khVMD2,EeVMD2,jfVMD2,TfVMD2,dgVMD2);input i_clk;input CeVMD2;input
|
<=micDs;always@(posedge i_clk)begin NkcDs<=1'd1;OkcDs<=6'd0;if((SjcDs>=8'd48)
|
[6:0]khVMD2;output reg EeVMD2;output reg[7:0]jfVMD2;output wire TfVMD2;input
|
&&(SjcDs<=8'd57))OkcDs<={2'd0,SjcDs[3:0]};else if((SjcDs>=8'd65)&&(SjcDs<=8'd90
|
dgVMD2;initial jfVMD2=8'd0;always@(posedge i_clk)if((CeVMD2)&&(~TfVMD2))begin
|
))OkcDs<=(SjcDs[5:0]-6'd1+6'd10);else if((SjcDs>=8'd97)&&(SjcDs<=8'd122))OkcDs
|
if(khVMD2[6])jfVMD2<=8'd10;else if(khVMD2[5:0]<=6'd9)jfVMD2<=8'd48+{4'd0,khVMD2
|
<=(SjcDs[5:0]+6'd3);else if(SjcDs==8'd64)OkcDs<=6'd62;else if(SjcDs==8'd37)
|
[3:0]};else if(khVMD2[5:0]<=6'd35)jfVMD2<=8'd65+{2'd0,khVMD2[5:0]}-8'd10;else
|
OkcDs<=6'd63;else NkcDs<=1'd0;end endmodule
|
if(khVMD2[5:0]<=6'd61)jfVMD2<=8'd97+{2'd0,khVMD2[5:0]}-8'd36;else if(khVMD2[5:0
|
|
]==6'd62)jfVMD2<=8'd64;else jfVMD2<=8'd37;end always@(posedge i_clk)if((EeVMD2
|
|
)&&(~dgVMD2))EeVMD2<=1'd0;else if((CeVMD2)&&(~EeVMD2))EeVMD2<=1'd1;assign
|
|
TfVMD2=EeVMD2;endmodule
|
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