| Line 76... |
Line 76... |
{ R_QSPI_SREG, "QSPISTAT" },
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{ R_QSPI_SREG, "QSPISTAT" },
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{ R_QSPI_SREG, "QSPIS" },
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{ R_QSPI_SREG, "QSPIS" },
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{ R_QSPI_IDREG, "QSPIID" },
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{ R_QSPI_IDREG, "QSPIID" },
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{ R_QSPI_IDREG, "QSPII" },
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{ R_QSPI_IDREG, "QSPII" },
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//
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//
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{ R_CLOCK, "CLOCK" },
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// The real-time-clock registers have been removed
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{ R_CLOCK, "TIME" },
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// (they never fit in the core)
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{ R_TIMER, "TIMER" },
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//
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{ R_STOPWATCH, "STOPWACH" },
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// The real-time-date register has been removed
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{ R_STOPWATCH, "STOPWATCH" },
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// (it never fit either)
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{ R_CKALARM, "CKALARM" },
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//
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{ R_CKALARM, "ALARM" },
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// The wishbone scope
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// { R_DATE, "DATE" },
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//
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// Scopes are defined and come and go. Be aware, therefore, not all
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// of these scopes may be defined at the same time.
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{ R_SCOPE, "SCOPE" },
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{ R_SCOPE, "SCOPE" },
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{ R_SCOPE, "SCOP" },
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{ R_SCOPE, "SCOP" },
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{ R_SCOPED, "SCOPDATA" },
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{ R_SCOPED, "SCOPDATA" },
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{ R_SCOPED, "SCDATA" },
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{ R_SCOPED, "SCDATA" },
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{ R_SCOPED, "SCOPED" },
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{ R_SCOPED, "SCOPED" },
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{ R_SCOPED, "SCOPD" },
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{ R_SCOPED, "SCOPD" },
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//
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//
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// For working with the ICAPE interface ... if I can ever get a
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// The ICAPE interface registers have been removed.
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// testing environment suitable to prove that it works.
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//
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{ R_CFG_CRC, "FPGACRC" },
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{ R_CFG_FAR_MAJ, "FPGAFARH" },
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{ R_CFG_FAR_MIN, "FPGAFARL" },
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{ R_CFG_FDRI, "FPGAFDRI" },
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{ R_CFG_FDRO, "FPGAFDRO" },
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{ R_CFG_CMD, "FPGACMD" },
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{ R_CFG_CTL, "FPGACTL" },
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{ R_CFG_MASK, "FPGAMASK" },
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{ R_CFG_STAT, "FPGASTAT" },
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{ R_CFG_LOUT, "FPGALOUT" },
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{ R_CFG_COR1, "FPGACOR1" },
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{ R_CFG_COR2, "FPGACOR2" },
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{ R_CFG_PWRDN, "FPGAPWRDN" },
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{ R_CFG_FLR, "FPGAFLR" },
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{ R_CFG_IDCODE, "FPGAIDCODE" },
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{ R_CFG_CWDT, "FPGACWDT" },
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{ R_CFG_HCOPT, "FPGAHCOPT" },
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{ R_CFG_CSBO, "FPGACSBO" },
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{ R_CFG_GEN1, "FPGAGEN1" },
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{ R_CFG_GEN2, "FPGAGEN2" },
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{ R_CFG_GEN3, "FPGAGEN3" },
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{ R_CFG_GEN4, "FPGAGEN4" },
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{ R_CFG_GEN5, "FPGAGEN5" },
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{ R_CFG_MODE, "FPGAMODE" },
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{ R_CFG_GWE, "FPGAGWE" },
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{ R_CFG_GTS, "FPGAGTS" },
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{ R_CFG_MFWR, "FPGAMFWR" },
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{ R_CFG_CCLK, "FPGACCLK" },
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{ R_CFG_SEU, "FPGASEU" },
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{ R_CFG_EXP, "FPGAEXP" },
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{ R_CFG_RDBK, "FPGARDBK" },
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{ R_CFG_BOOTSTS, "BOOTSTS" },
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{ R_CFG_EYE, "FPGAEYE" },
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{ R_CFG_CBC, "FPGACBC" },
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//
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//
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{ RAMBASE, "MEM" },
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{ RAMBASE, "MEM" },
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{ SPIFLASH, "FLASH" }
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{ SPIFLASH, "FLASH" }
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};
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};
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