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[/] [s6soc/] [trunk/] [sw/] [zipos/] [resetdump.s] - Diff between revs 27 and 45

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Rev 27 Rev 45
Line 30... Line 30...
;; Creator:     Dan Gisselquist, Ph.D.
;; Creator:     Dan Gisselquist, Ph.D.
;;              Gisselquist Technology, LLC
;;              Gisselquist Technology, LLC
;;
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;//
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;//
;;
;;
;; Copyright (C) 2015-2016, Gisselquist Technology, LLC
;; Copyright (C) 2015-2017, Gisselquist Technology, LLC
;;
;;
;; This program is free software (firmware): you can redistribute it and/or
;; This program is free software (firmware): you can redistribute it and/or
;; modify it under the terms of  the GNU General Public License as published
;; modify it under the terms of  the GNU General Public License as published
;; by the Free Software Foundation, either version 3 of the License, or (at
;; by the Free Software Foundation, either version 3 of the License, or (at
;; your option) any later version.
;; your option) any later version.
Line 60... Line 60...
        .global         _start
        .global         _start
        .type           _start,@function
        .type           _start,@function
_start:
_start:
; Upon reset, we must output our registers to the UART, lest we reset because
; Upon reset, we must output our registers to the UART, lest we reset because
; of a crash
; of a crash
        STO     R0,(DBG)
        SW      R0,(DBG)
        MOV     PC+1,R0
        JSR     internal_kpanic
        BRA     internal_kpanic
 
        LDI     _top_of_stack,SP
        LDI     _top_of_stack,SP
        LDI     kernel_entry,R0
        LDI     kernel_entry,R0
        BRA     bootloader
        BRA     _bootloader
 
 
        .global         kpanic
        .global         kpanic
        .type           kpanic,@function
        .type           kpanic,@function
kpanic:
kpanic:
        STO     R0,(DBG)
        SW      R0,(DBG)
        STO     R1,1(DBG)
        SW      R1,4(DBG)
        STO     R2,2(DBG)
        SW      R2,8(DBG)
        LDI     'P',R1
        LDI     panicstr, R1
        MOV     PC+1,R0
        JSR     raw_put_string
        JMP     raw_put_uart
        LW      4(DBG),R1
        LDI     'a',R1
        LW      8(DBG),R2
        MOV     PC+1,R0
        JSR     internal_kpanic
        JMP     raw_put_uart
 
        LDI     'n',R1
 
        MOV     PC+1,R0
 
        JMP     raw_put_uart
 
        LDI     'i',R1
 
        MOV     PC+1,R0
 
        JMP     raw_put_uart
 
        LDI     'c',R1
 
        MOV     PC+1,R0
 
        JMP     raw_put_uart
 
        LDI     ':',R1
 
        MOV     PC+1,R0
 
        JMP     raw_put_uart
 
        LDI     ' ',R1
 
        MOV     PC+1,R0
 
        JMP     raw_put_uart
 
        LDI     '\r',R1
 
        MOV     PC+1,R0
 
        JMP     raw_put_uart
 
        LDI     '\n',R1
 
        MOV     PC+1,R0
 
        JMP     raw_put_uart
 
        LOD     1(DBG),R1
 
        LOD     2(DBG),R2
 
        MOV     PC+1,R0
 
        JMP     internal_kpanic
 
kpanic_wait_for_button_release:
kpanic_wait_for_button_release:
        LOD     (SPIO),R0
        LW      (SPIO),R0
        TEST    0x010,R0
        TEST    0x010,R0
        BNZ     kpanic_wait_for_button_release
        BNZ     kpanic_wait_for_button_release
kpanic_wait_for_button:
kpanic_wait_for_button:
        LOD     (SPIO),R0
        LW      (SPIO),R0
        TEST    0x010,R0
        TEST    0x010,R0
        BZ      kpanic_wait_for_button
        BZ      kpanic_wait_for_button
        BRA     _start
        BRA     _start
        HALT
        HALT
 
 
internal_kpanic:
internal_kpanic:
        STO     R1,1(DBG)
        ; The original R0 is stored in (DBG)
        STO     R2,2(DBG)
        SW      R1,4(DBG)
        STO     R0,3(DBG)       ; Our return address
        SW      R2,8(DBG)
 
        SW      R0,12(DBG)      ; Our return address
 
 
        ; R0
        ; R0
        LDI     0,R1
        LDI     0,R1
        LOD     (DBG),R2
        LW      (DBG),R2
        MOV     .Lcall0(PC),R0
        JSR     uart_put_reg_value
        JMP     uart_put_reg_value
 
.Lcall0:
 
 
 
        ; R1
        ; R1
        LDI     1,R1
        LDI     1,R1
        LOD     1(DBG),R2
        LW      4(DBG),R2
        MOV     .Lcall1(PC),R0
        JSR     uart_put_reg_value
        JMP     uart_put_reg_value
 
.Lcall1:
 
        ; R2
        ; R2
        LDI     2,R1
        LDI     2,R1
        LOD     2(DBG),R2
        LW      8(DBG),R2
        MOV     PC+1,R0
        JSR     uart_put_reg_value
        JMP     uart_put_reg_value
 
        ; R3
        ; R3
        LDI     3,R1
        LDI     3,R1
        MOV     R3,R2
        MOV     R3,R2
        MOV     PC+1,R0
        JSR     uart_put_reg_value
        JMP     uart_put_reg_value
 
 
 
        ; R4
        ; R4
        LDI     4,R1
        LDI     4,R1
        MOV     R4,R2
        MOV     R4,R2
        MOV     PC+1,R0
        JSR     uart_put_reg_value
        JMP     uart_put_reg_value
 
 
 
        ; R5
        ; R5
        LDI     5,R1
        LDI     5,R1
        MOV     R5,R2
        MOV     R5,R2
        MOV     PC+1,R0
        JSR     uart_put_reg_value
        JMP     uart_put_reg_value
 
 
 
        ; R6
        ; R6
        LDI     6,R1
        LDI     6,R1
        MOV     R6,R2
        MOV     R6,R2
        MOV     PC+1,R0
        JSR     uart_put_reg_value
        JMP     uart_put_reg_value
 
 
 
        ; R7
        ; R7
        LDI     7,R1
        LDI     7,R1
        MOV     R7,R2
        MOV     R7,R2
        MOV     PC+1,R0
        JSR     uart_put_reg_value
        JMP     uart_put_reg_value
 
 
 
        ; R8
        ; R8
        LDI     8,R1
        LDI     8,R1
        MOV     R8,R2
        MOV     R8,R2
        MOV     PC+1,R0
        JSR     uart_put_reg_value
        JMP     uart_put_reg_value
 
 
 
        ; R9
        ; R9
        LDI     9,R1
        LDI     9,R1
        MOV     R9,R2
        MOV     R9,R2
        MOV     PC+1,R0
        JSR     uart_put_reg_value
        JMP     uart_put_reg_value
 
 
 
        ; R10
        ; R10
        LDI     10,R1
        LDI     10,R1
        MOV     R10,R2
        MOV     R10,R2
        MOV     PC+1,R0
        JSR     uart_put_reg_value
        JMP     uart_put_reg_value
 
 
 
        ; R11
        ; R11
        LDI     11,R1
        LDI     11,R1
        MOV     R11,R2
        MOV     R11,R2
        MOV     PC+1,R0
        JSR     uart_put_reg_value
        JMP     uart_put_reg_value
 
 
 
        ; R12
        ; R12
        LDI     12,R1
        LDI     12,R1
        MOV     R12,R2
        MOV     R12,R2
        MOV     PC+1,R0
        JSR     uart_put_reg_value
        JMP     uart_put_reg_value
 
 
 
        ; SP
        ; SP
        LDI     13,R1
        LDI     13,R1
        MOV     R13,R2
        MOV     R13,R2
        MOV     PC+1,R0
        JSR     uart_put_reg_value
        JMP     uart_put_reg_value
 
 
 
        ; uR0
        ; uR0
        LDI     16,R1
        LDI     16,R1
        MOV     uR0,R2
        MOV     uR0,R2
        MOV     PC+1,R0
        JSR     uart_put_reg_value
        JMP     uart_put_reg_value
 
 
 
        ; uR1
        ; uR1
        LDI     17,R1
        LDI     17,R1
        MOV     uR1,R2
        MOV     uR1,R2
        MOV     PC+1,R0
        JSR     uart_put_reg_value
        JMP     uart_put_reg_value
 
 
 
        LDI     18,R1
        LDI     18,R1
        MOV     uR2,R2
        MOV     uR2,R2
        MOV     PC+1,R0
        JSR     uart_put_reg_value
        JMP     uart_put_reg_value
 
 
 
        LDI     19,R1
        LDI     19,R1
        MOV     uR3,R2
        MOV     uR3,R2
        MOV     PC+1,R0
        JSR     uart_put_reg_value
        JMP     uart_put_reg_value
 
 
 
        LDI     20,R1
        LDI     20,R1
        MOV     uR4,R2
        MOV     uR4,R2
        MOV     PC+1,R0
        JSR     uart_put_reg_value
        JMP     uart_put_reg_value
 
 
 
        LDI     21,R1
        LDI     21,R1
        MOV     uR5,R2
        MOV     uR5,R2
        MOV     PC+1,R0
        JSR     uart_put_reg_value
        JMP     uart_put_reg_value
 
 
 
        LDI     22,R1
        LDI     22,R1
        MOV     uR6,R2
        MOV     uR6,R2
        MOV     PC+1,R0
        JSR     uart_put_reg_value
        JMP     uart_put_reg_value
 
 
 
        LDI     23,R1
        LDI     23,R1
        MOV     uR7,R2
        MOV     uR7,R2
        MOV     PC+1,R0
        JSR     uart_put_reg_value
        JMP     uart_put_reg_value
 
 
 
        LDI     24,R1
        LDI     24,R1
        MOV     uR8,R2
        MOV     uR8,R2
        MOV     PC+1,R0
        JSR     uart_put_reg_value
        JMP     uart_put_reg_value
 
 
 
        LDI     25,R1
        LDI     25,R1
        MOV     uR9,R2
        MOV     uR9,R2
        MOV     PC+1,R0
        JSR     uart_put_reg_value
        JMP     uart_put_reg_value
 
 
 
        LDI     26,R1
        LDI     26,R1
        MOV     uR10,R2
        MOV     uR10,R2
        MOV     PC+1,R0
        JSR     uart_put_reg_value
        JMP     uart_put_reg_value
 
 
 
        LDI     27,R1
        LDI     27,R1
        MOV     uR11,R2
        MOV     uR11,R2
        MOV     PC+1,R0
        JSR     uart_put_reg_value
        JMP     uart_put_reg_value
 
 
 
        LDI     28,R1
        LDI     28,R1
        MOV     uR12,R2
        MOV     uR12,R2
        MOV     PC+1,R0
        JSR     uart_put_reg_value
        JMP     uart_put_reg_value
 
 
 
        ; uSP
        ; uSP
        LDI     29,R1
        LDI     29,R1
        MOV     uSP,R2
        MOV     uSP,R2
        MOV     PC+1,R0
        JSR     uart_put_reg_value
        JMP     uart_put_reg_value
 
 
 
        ; uCC
        ; uCC
        LDI     30,R1
        LDI     30,R1
        MOV     uCC,R2
        MOV     uCC,R2
        MOV     PC+1,R0
        JSR     uart_put_reg_value
        JMP     uart_put_reg_value
 
 
 
        ; uPC
        ; uPC
        LDI     31,R1
        LDI     31,R1
        MOV     uPC,R2
        MOV     uPC,R2
        MOV     PC+1,R0
        JSR     uart_put_reg_value
        JMP     uart_put_reg_value
 
 
 
;stack_mem_dump:
;stack_mem_dump:
        ;LDI    0,R4
        ;LDI    0,R4
        ;LDI    _top_of_stack,R5
        ;LDI    _top_of_stack,R5
;stack_mem_dump_loop:
;stack_mem_dump_loop:
        ;MOV    R4,R1
        ;MOV    R4,R1
        ;LOD    (R5),R2
;       LW      (R5),R2
        ;MOV    PC+1,R0
;       JSR     uart_put_stack_value
        ;JMP    uart_put_stack_value
;       ADD     4,R4
        ;ADD    1,R4
;       SUB     4,R5
        ;SUB    1,R5
;       CMP     256,R4
        ;CMP    64,R4
 
        ;BLT    stack_mem_dump_loop
        ;BLT    stack_mem_dump_loop
 
 
; Get prepared for a proper start by setting our stack register
; Get prepared for a proper start by setting our stack register
        LDI     _top_of_stack,SP
        LDI     _top_of_stack,SP
 
 
Line 311... Line 252...
        ; BRA   end_internal_panic
        ; BRA   end_internal_panic
 
 
; Now, do a full dump of all memory--all registers are available to us
; Now, do a full dump of all memory--all registers are available to us
dump_memory:
dump_memory:
        LDI     RAM,R5
        LDI     RAM,R5
        LDI     0x1000,R6
        LDI     0x0fff,R6
        LDI     0x0f8,R7
        LDI     0x0f8,R7
        STO     R7,(SPIO)
        SW      R7,(SPIO)
full_mem_dump_loop:
full_mem_dump_loop:
        MOV     R5,R1
        MOV     R5,R1
        LOD     (R5),R2
        LW      (R5),R2
        MOV     PC+1,R0
        JSR     uart_dump_mem_value
        JMP     uart_dump_mem_value
 
        LDI     0x0f2,R7
        LDI     0x0f2,R7
        STO     R7,(SPIO)
        SW      R7,(SPIO)
 
 
        ADD     1,R5
        ADD     4,R5
        SUB     1,R6
        SUB     1,R6
        BGT     full_mem_dump_loop
        BGE     full_mem_dump_loop
 
 
        LDI     0x0f5,R7
        LDI     0x0f5,R7
        STO     R7,(SPIO)
        SW      R7,(SPIO)
 
 
dump_scope:
dump_scope:
; Finally, do a full dump of the scope--if it had triggered
; Finally, do a full dump of the scope--if it had triggered
;   First, dump the scope control word
;   First, dump the scope control word
        LDI     SCOPE,R7        ; R7 = Debugging scope address
        LDI     SCOPE,R7        ; R7 = Debugging scope address
        MOV     R7,R1
        MOV     R7,R1
        LOD     (R7),R2
        LW      (R7),R2
        MOV     R2,R5           ; R5 will not be changed by a subroutine
        MOV     R2,R5           ; R5 will not be changed by a subroutine
        MOV     PC+1,R0
        JSR     uart_dump_mem_value
        BRA     uart_dump_mem_value
 
;   Then test whether or not the scope has stopped
;   Then test whether or not the scope has stopped
        LDI     0x40000000,R1
        LDI     0x40000000,R1
        TEST    R1,R5
        TEST    R1,R5
;   If not, start our kernel.
;   If not, start our kernel.
        BZ      dump_buserr
        BZ      dump_buserr
;   Otherwise, calculate the size of the scope
;   Otherwise, calculate the size of the scope
        LSR     20,R5
        LSR     20,R5
        AND     0x1f,R5
        AND     0x1f,R5
        LDI     1,R6
        LDI     1,R6
        LSL     R5,R6
        LSL     R5,R6   ; R6 is now the size (number of words) of the scope
 
        SUB     1,R6    ; Now it is one less than the size,2 support the BGE l8r
;   And start dumping
;   And start dumping
        ADD     1,R7    ; Get the scope data address
        ADD     4,R7    ; Get the scope data address
dump_scope_loop:
dump_scope_loop:
        MOV     R7,R1
        MOV     R7,R1
        LOD     (R7),R2
        LW      (R7),R2
        MOV     PC+1,R0
        JSR     uart_dump_mem_value
        BRA     uart_dump_mem_value
 
        SUB     1,R6
        SUB     1,R6
        BGT     dump_scope_loop
        BGE     dump_scope_loop
 
 
dump_buserr:
dump_buserr:
; Dump a bus error address, if used
; Dump a bus error address, if used
        LDI     'B',R1
        LDI     buserr_header, R1
        MOV     PC+1,R0
        JSR     raw_put_string
        BRA     raw_put_uart
 
        LDI     'u',R1
 
        MOV     PC+1,R0
 
        BRA     raw_put_uart
 
        LDI     's',R1
 
        MOV     PC+1,R0
 
        BRA     raw_put_uart
 
        LDI     'E',R1
 
        MOV     PC+1,R0
 
        BRA     raw_put_uart
 
        LDI     'r',R1
 
        MOV     PC+1,R0
 
        BRA     raw_put_uart
 
        LDI     'r',R1
 
        MOV     PC+1,R0
 
        BRA     raw_put_uart
 
        LDI     ':',R1
 
        MOV     PC+1,R0
 
        BRA     raw_put_uart
 
        LDI     ' ',R1
 
        MOV     PC+1,R0
 
        BRA     raw_put_uart
 
        LDI     BUSERR,R1
        LDI     BUSERR,R1
        LOD     (R1),R2
        LW      (R1),R2
        MOV     PC+1,R0
        JSR     uart_dump_mem_value
        BRA     uart_dump_mem_value
 
 
 
end_internal_panic:
end_internal_panic:
        LDI     '\r',R1
        LDI     doublenewline,R1
        MOV     PC+1,R0
        JSR     raw_put_string
        BRA     raw_put_uart
 
        LDI     '\n',R1
 
        MOV     PC+1,R0
 
        BRA     raw_put_uart
 
        LDI     '\r',R1
 
        MOV     PC+1,R0
 
        BRA     raw_put_uart
 
        LDI     '\n',R1
 
        MOV     PC+1,R0
 
        BRA     raw_put_uart
 
        LDI     0x0ff,R7
        LDI     0x0ff,R7
        STO     R7,(SPIO)
        SW      R7,(SPIO)
        LOD     3(DBG),PC
        LW      12(DBG),PC
        JMP     R0
        JMP     R0
 
 
; R0 is return address
; R0 is return address
; R1 is register ID
; R1 is register ID
; R2 is register to output
; R2 is register value to output
uart_put_reg_value:
uart_put_reg_value:
        STO     R0,4(DBG)
        SW      R0,16(DBG)
        STO     R2,5(DBG)
        SW      R2,20(DBG)
        STO     R3,6(DBG)
        SW      R3,24(DBG)
        MOV     R1,R2
        MOV     R1,R2
        LDI     'u',R1
        LDI     'u',R1
        CMP     16,R2
        CMP     16,R2
        LDILO.LT 's',R1
        LDILO.LT 's',R1
        SUB.GE  16,R2
        SUB.GE  16,R2
        MOV     PC+1,R0
        JSR     raw_put_uart
        JMP     raw_put_uart
 
        LDI     '0',R1
        LDI     '0',R1
        CMP     10,R2
        CMP     10,R2
        LDILO.GE '1',R1
        LDILO.GE '1',R1
        SUB.GE  10,R2
        SUB.GE  10,R2
        MOV     PC+1,R0
        JSR     raw_put_uart
        JMP     raw_put_uart
 
        MOV     R2,R1
        MOV     R2,R1
        AND     15,R1
        AND     15,R1
        MOV     PC+1,R0
        JSR     get_hex
        JMP     get_hex
        JSR     raw_put_uart
        MOV     PC+1,R0
        LDI     ':',R1
        JMP     raw_put_uart
        JSR     raw_put_uart
        LDI     58,R1   ; A ':'
        LW      20(DBG),R2
        MOV     PC+1,R0
 
        JMP     raw_put_uart
 
        LOD     5(DBG),R2
 
        LDI     8,R3
        LDI     8,R3
uart_put_loop:
uart_put_loop:
        ROL     4,R2
 
        MOV     R2,R1
        MOV     R2,R1
        AND     15,R1
        LSR     28,R1
        MOV     PC+1,R0
        LSL     4,R2
        JMP     get_hex
        JSR     get_hex
        MOV     PC+1,R0
        JSR     raw_put_uart
        JMP     raw_put_uart
 
        SUB     1,R3
        SUB     1,R3
        BNZ     uart_put_loop
        BNZ     uart_put_loop
        LDI     '\r',R1
        LDI     newline, R1
        MOV     PC+1,R0
        JSR     raw_put_string
        JMP     raw_put_uart
        LW      16(DBG),R0
        LDI     '\n',R1
        LW      20(DBG),R2
        MOV     PC+1,R0
        LW      24(DBG),R3
        JMP     raw_put_uart
 
        LOD     4(DBG),R0
 
        LOD     5(DBG),R2
 
        LOD     6(DBG),R3
 
        JMP     R0
        JMP     R0
 
 
uart_dump_mem_value:
uart_dump_mem_value:
;       R0 = return address
;       R0 = return address
;       R1 = Memory address
;       R1 = Memory address
;       R2 = Memory Value
;       R2 = Memory Value
; Local: R3 = working value
; Local: R3 = working value
        STO     R0,7(DBG)
        SW      R0,28(DBG)
        MOV     R1,R3           ; R3 = Memory address
        MOV     R1,R3           ; R3 = Memory address
        MOV     R2,R4           ; R4 = Memory Value
        MOV     R2,R4           ; R4 = Memory Value
        LDI     77,R1           ; 77 = 'M'
        LDI     memopenstr,R1
        MOV     PC+1,R0
        JSR     raw_put_string
        JMP     raw_put_uart
 
        LDI     91,R1           ; 91 = '['
 
        MOV     PC+1,R0
 
        JMP     raw_put_uart
 
        LDI     48,R1           ; A '0'
 
        MOV     PC+1,R0
 
        JMP     raw_put_uart
 
        LDI     120,R1          ; An 'x'
 
        MOV     PC+1,R0
 
        JMP     raw_put_uart
 
        ; Set up a loop to dump things
        ; Set up a loop to dump things
        ROL     16,R3           ; Ignore the first 16 bits
        LSL     16,R3           ; Ignore the first 16 bits
        LDI     4,R2            ; We're going to do four hex digits here
        LDI     4,R2            ; We're going to do four hex digits here
        ;
        ;
uart_put_mem_address_loop:
uart_put_mem_address_loop:
        ROL     4,R3
 
        MOV     R3,R1
        MOV     R3,R1
        AND     15,R1
        LSR     28,R1
        MOV     PC+1,R0
        LSL     4,R3
        JMP     get_hex
        JSR     get_hex
        MOV     PC+1,R0
        JSR     raw_put_uart
        JMP     raw_put_uart
 
        SUB     1,R2
        SUB     1,R2
        BNZ     uart_put_mem_address_loop
        BNZ     uart_put_mem_address_loop
        ; Put some transition characters
        ; Put some transition characters
        LDI     93,R1           ; 93 = ']'
        LDI     memmidstr,R1
        MOV     PC+1,R0
        JSR     raw_put_string
        JMP     raw_put_uart
 
        LDI     58, R1          ; A semicolon
 
        MOV     PC+1,R0
 
        JMP     raw_put_uart
 
        LDI     32, R1          ; A space
 
        MOV     PC+1,R0
 
        JMP     raw_put_uart
 
 
 
        ; Set up a loop to dump the memory value now
        ; Set up a loop to dump the memory value now
        LDI     8,R2
        LDI     8,R2
uart_put_mem_value_loop:
uart_put_mem_value_loop:
        ROL     4,R4
 
        MOV     R4,R1
        MOV     R4,R1
        AND     15,R1
        LSR     28,R1
        MOV     PC+1,R0
        LSL     4,R4
        JMP     get_hex
        JSR     get_hex
        MOV     PC+1,R0
        JSR     raw_put_uart
        JMP     raw_put_uart
 
        SUB     1,R2
        SUB     1,R2
        BNZ     uart_put_mem_value_loop
        BNZ     uart_put_mem_value_loop
        ; Clear the line
        ; Clear the line
        LDI     '\r', R1
        LDI     newline,R1
        MOV     PC+1,R0
        JSR     raw_put_string
        JMP     raw_put_uart
 
        LDI     '\n', R1
 
        MOV     PC+1,R0
 
        JMP     raw_put_uart
 
        ; And return from our subroutine
        ; And return from our subroutine
        LOD     7(DBG),R0
        LW      28(DBG),R0
        JMP     R0
        JMP     R0
 
 
get_hex:
get_hex:
        ADD     0x30,R1
        ADD     0x30,R1
        CMP     0x39,R1
        CMP     0x3a,R1
        ADD.GT  7,R1    ; Add 'A'-'0'-10
        ADD.GE  7,R1    ; Add 'A'-'0'-10
        JMP     R0
        JMP     R0
 
 
raw_put_uart:   ; R0 is return address, R1 is value to transmit
; R0 is the return address
        STO     R2,8(DBG)
; R1 is the string address
 
raw_put_string:
 
        SW      R0,36(DBG)
 
        SW      R2,40(DBG)
 
        MOV     R1,R2
 
raw_put_string_next:
 
        LB      (R2),R1
 
        CMP     0,R1
 
        LW.Z    36(DBG),R0
 
        LW.Z    40(DBG),R2
 
        RTN.Z
 
        ADD     1,R2
 
        MOV     raw_put_string_next(PC),R0
 
        BRA     raw_put_uart
 
 
 
; R0 is return address,
 
; R1 is value to transmit
 
raw_put_uart:
 
        SW      R2,32(DBG)
        LDI     INT_UARTTX,R2
        LDI     INT_UARTTX,R2
        STO     R2,(PIC)        ; Clear the PIC, turn off interrupts, etc.
        SW      R2,(PIC)        ; Clear the PIC, turn off interrupts, etc.
raw_put_uart_retest:
raw_put_uart_retest:
        LOD     (PIC),R2
        LW      (PIC),R2
        TEST    INT_UARTTX,R2
        TEST    INT_UARTTX,R2
        BZ      raw_put_uart_retest
        BZ      raw_put_uart_retest
        STO     R1,(UART)
        SW      R1,(UART)
        LOD     8(DBG),R2
        LW      32(DBG),R2
        JMP     R0
        JMP     R0
 
 
        .section        .fixdata
        .section        .fixdata
DBG:
DBG:
.byte   0,0,0,0,0,0,0,0,0
.int    0,0,0,0,0,0,0,0,0,0
 
 
.set    INT_UARTRX, 0x040
.set    INT_UARTRX, 0x040
.set    INT_UARTTX, 0x080
.set    INT_UARTTX, 0x080
.set    PIC,     0x0100
.set    PIC,     0x0400
.set    BUSERR,  0x0101
.set    BUSERR,  0x0404
.set    TMRA,    0x0102
.set    TMRA,    0x0408
.set    TMRB,    0x0103
.set    TMRB,    0x040c
.set    PWM,     0x0104
.set    PWM,     0x0410
.set    SPIO,    0x0105
.set    SPIO,    0x0414
.set    GPIO,    0x0106
.set    GPIO,    0x0418
.set    UART,    0x0107
.set    UART,    0x041c
.set    VERSION, 0x0108
.set    VERSION, 0x0420
.set    SCOPE,   0x0200
.set    SCOPE,   0x0800
.set    SCOPED,  0x0201
.set    SCOPED,  0x0804
.set    CLOCK,   0x0800
.set    RAM,     0x8000
.set    CONFIG,  0x0400
        .section        .rodata
.set    TIMER,   0x0801
doublenewline:
.set    STOPWATCH,0x802
        .ascii  "\r\n"
.set    ALARM,   0x0803
newline:
.set    RAM,     0x2000
        .asciz  "\r\n"
 
buserr_header:
 
        .string "BusErr: "
 
panicstr:
 
        .string "Panic: \r\n"
 
memopenstr:
 
        .string "M[0x"
 
memmidstr:
 
        .string "]; "
 
 
 
 
 No newline at end of file
 No newline at end of file

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