URL https://opencores.org/ocsvn/sata_controller_core/sata_controller_core/trunk

Subversion Repositories sata_controller_core

[/] [sata_controller_core/] [trunk/] [sata2_fifo_v1_00_a/] [netlist/] [coregen.cgp] - Diff between revs 2 and 5

Rev 2	Rev 5
?rev1line?	?rev2line?
	`SET addpads = false`
	`SET asysymbol = true`
	`SET busformat = BusFormatAngleBracketNotRipped`
	`SET createndf = false`
	`SET designentry = VHDL`
	`SET device = xc6vlx240t`
	`SET devicefamily = virtex6`
	`SET flowvendor = Other`
	`SET formalverification = false`
	`SET foundationsym = false`
	`SET implementationfiletype = Ngc`
	`SET package = ff1156`
	`SET removerpms = false`
	`SET simulationfiles = Behavioral`
	`SET speedgrade = -1`
	`SET verilogsim = false`
	`SET vhdlsim = true`
	`SET workingdirectory = ./tmp/`