| Line 1... |
Line 1... |
##############################################################
|
##############################################################
|
#
|
#
|
# Xilinx Core Generator version 12.2
|
# Xilinx Core Generator version 12.2
|
# Date: Fri Apr 6 17:06:28 2012
|
# Date: Wed Jun 27 22:54:56 2012
|
#
|
#
|
##############################################################
|
##############################################################
|
#
|
#
|
# This file contains the customisation parameters for a
|
# This file contains the customisation parameters for a
|
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
| Line 37... |
Line 37... |
# BEGIN Parameters
|
# BEGIN Parameters
|
CSET almost_empty_flag=false
|
CSET almost_empty_flag=false
|
CSET almost_full_flag=false
|
CSET almost_full_flag=false
|
CSET component_name=user_fifo
|
CSET component_name=user_fifo
|
CSET data_count=false
|
CSET data_count=false
|
CSET data_count_width=11
|
CSET data_count_width=10
|
CSET disable_timing_violations=false
|
CSET disable_timing_violations=false
|
CSET dout_reset_value=0
|
CSET dout_reset_value=0
|
CSET empty_threshold_assert_value=4
|
CSET empty_threshold_assert_value=4
|
CSET empty_threshold_negate_value=5
|
CSET empty_threshold_negate_value=5
|
CSET enable_ecc=false
|
CSET enable_ecc=false
|
CSET enable_int_clk=false
|
CSET enable_int_clk=false
|
CSET enable_reset_synchronization=true
|
CSET enable_reset_synchronization=true
|
CSET fifo_implementation=Common_Clock_Block_RAM
|
CSET fifo_implementation=Independent_Clocks_Block_RAM
|
CSET full_flags_reset_value=1
|
CSET full_flags_reset_value=1
|
CSET full_threshold_assert_value=256
|
CSET full_threshold_assert_value=512
|
CSET full_threshold_negate_value=255
|
CSET full_threshold_negate_value=511
|
CSET inject_dbit_error=false
|
CSET inject_dbit_error=false
|
CSET inject_sbit_error=false
|
CSET inject_sbit_error=false
|
CSET input_data_width=32
|
CSET input_data_width=32
|
CSET input_depth=1024
|
CSET input_depth=1024
|
CSET output_data_width=32
|
CSET output_data_width=32
|
| Line 79... |
Line 79... |
CSET write_clock_frequency=1
|
CSET write_clock_frequency=1
|
CSET write_data_count=false
|
CSET write_data_count=false
|
CSET write_data_count_width=11
|
CSET write_data_count_width=11
|
# END Parameters
|
# END Parameters
|
GENERATE
|
GENERATE
|
# CRC: b44c501c
|
# CRC: b2115d65
|
# CRC: b2115d65
|
# CRC: b2115d65
|
