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https://opencores.org/ocsvn/sata_controller_core/sata_controller_core/trunk
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# SATA Port J11 #J64 FMC pins
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Net TXN0_OUT LOC = AF2; #A27
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Net TXP0_OUT LOC = AF1; #A26
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Net RXN0_IN LOC = AF6; #A7
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Net RXP0_IN LOC = AF5; #A6
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#Net FMC_HPC_DP2_C2M_N LOC = AF2; #A27
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#Net FMC_HPC_DP2_C2M_P LOC = AF1; #A26
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#Net FMC_HPC_DP2_M2C_N LOC = AF6; #A7
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#Net FMC_HPC_DP2_M2C_P LOC = AF5; #A6
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# GTX Clock Module constraints
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#NET REFCLK_PAD_N_IN LOC=AK5; #FMC_HPC_CLK2_M2C_MGT_C_N
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#NET REFCLK_PAD_P_IN LOC=AK6; #FMC_HPC_CLK2_M2C_MGT_C_P
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#### Module LEDs_8Bit constraints
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NET PLLLKDET_OUT_N LOC= "AC22" |IOSTANDARD=LVCMOS25; #LED 0
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NET DCMLOCKED_OUT LOC= "AC24" |IOSTANDARD=LVCMOS25; #LED 1
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NET LINKUP LOC= "AE22" |IOSTANDARD=LVCMOS25; #LED 2
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################################## Clock Constraints ##########################
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# Change this to the 150 Mhz GTX reference clock
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Net CLKIN_150 TNM_NET = sys_clk_pin;
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TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 200000 kHz;
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Net CLKIN_150 LOC = J9 ;
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#Net CLKIN_150 LOC = J9 | IOSTANDARD=LVDS_25 | DIFF_TERM = TRUE;
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#Net CLKIN_N LOC = H9 | IOSTANDARD=LVDS_25 | DIFF_TERM = TRUE;
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Net reset TIG;
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Net reset LOC = H10 | IOSTANDARD=SSTL15 | PULLUP | TIG;
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