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[/] [sc2v/] [trunk/] [examples/] [dummy1.cpp] - Diff between revs 21 and 22
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Rev 22 |
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#include "systemc.h"
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#include "systemc.h"
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#define HOLA 1
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#define HOLA 1
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#define CONCAT 1
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#define CONCAT 1
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sc_uint<2> fsm::func1(sc_uint<2> a, sc_uint<2> b){
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sc_uint<2> dummy1::func1(sc_uint<2> a, sc_uint<2> b){
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sc_uint<2> c;
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sc_uint<2> c;
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c=a+b;
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c=a+b;
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return c+5;
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return c+5;
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}
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}
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void
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void
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fsm::regs ()
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dummy1::regs ()
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{
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{
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if (rst.read ())
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if (rst.read ())
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{
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{
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state.write (S0);
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state.write (S0);
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}
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}
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else
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else
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state.write (next_state);
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state.write (next_state);
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}
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}
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void
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void
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fsm::fsm_proc ()
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dummy1::fsm_proc ()
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{
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{
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/*Verilog begin
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/*Verilog begin
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cfsm_proc={a[1:0],b[1:0]};
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cfsm_proc={a[1:0],b[1:0]};
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verilog end*/
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verilog end*/
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