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[/] [sc2v/] [trunk/] [src/] [sc2v_step1.y] - Diff between revs 14 and 15

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Rev 14 Rev 15
Line 26... Line 26...
#include 
#include 
#include 
#include 
 
 
#include "sc2v_step1.h"
#include "sc2v_step1.h"
 
 
 
  int lineno=1;
  int processfound = 0;
  int processfound = 0;
  int switchfound = 0;
  int switchfound = 0;
  int switchparenthesis[256];
  int switchparenthesis[256];
  int ifdeffound = 0;
  int ifdeffound = 0;
  char *processname, *processname2;
  char *processname, *processname2;
Line 63... Line 64...
  int verilog;
  int verilog;
  int writemethod;
  int writemethod;
 
 
  void yyerror (const char *str)
  void yyerror (const char *str)
  {
  {
    fprintf (stderr, "error: %s\n", str);
    fprintf (stderr, "line: %d error: %s\n", lineno, str);
  }
  }
 
 
  int yywrap ()
  int yywrap ()
  {
  {
    return 1;
    return 1;
Line 103... Line 104...
 
 
    translate = 1;
    translate = 1;
    verilog = 0;
    verilog = 0;
    writemethod = 0;
    writemethod = 0;
 
 
 
    FILE* yyin = stdin;
 
    FILE* yyout = stdout;
    yyparse ();
    yyparse ();
    fclose (FILE_WRITES);
    fclose (FILE_WRITES);
    fclose (FILE_DEFINES);
    fclose (FILE_DEFINES);
 
 
        fprintf(stderr,"\nDone\n\n");
        fprintf(stderr,"\nDone\n\n");
Line 1075... Line 1078...
translateoff:
translateoff:
TRANSLATEOFF
TRANSLATEOFF
{
{
  defineparenthesis = 0;
  defineparenthesis = 0;
  translate = 0;
  translate = 0;
  fprintf (stderr, "Found Translate off directive \n");
  fprintf (stderr, "line: %d Found Translate off directive \n", lineno);
};
};
 
 
translateon:
translateon:
TRANSLATEON
TRANSLATEON
{
{
  defineparenthesis = 0;
  defineparenthesis = 0;
  translate = 1;
  translate = 1;
  fprintf (stderr, "Found Translate on directive \n");
  fprintf (stderr, "line: %d Found Translate on directive \n", lineno);
};
};
 
 
verilogbegin:
verilogbegin:
VERILOGBEGIN
VERILOGBEGIN
{
{
  defineparenthesis = 0;
  defineparenthesis = 0;
  verilog = 1;
  verilog = 1;
  fprintf (stderr, "Found Verilog Begin directive \n");
  fprintf (stderr, "line: %d Found Verilog Begin directive \n", lineno);
};
};
 
 
verilogend:
verilogend:
VERILOGEND
VERILOGEND
{
{
  defineparenthesis = 0;
  defineparenthesis = 0;
  verilog = 0;
  verilog = 0;
  fprintf (stderr, "Found Verilog End directive \n");
  fprintf (stderr, "line: %d Found Verilog End directive \n", lineno);
};
};
 
 
ifdef:
ifdef:
PIFDEF
PIFDEF
{
{

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