URL
https://opencores.org/ocsvn/sc2v/sc2v/trunk
[/] [sc2v/] [trunk/] [src/] [sc2v_step1.y] - Diff between revs 16 and 18
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
Rev 16 |
Rev 18 |
Line 79... |
Line 79... |
int i;
|
int i;
|
|
|
defineslist = NULL;
|
defineslist = NULL;
|
regslist = NULL;
|
regslist = NULL;
|
|
|
fprintf (stderr, "\nSystemC to Verilog Translator v0.3");
|
fprintf (stderr, "\nSystemC to Verilog Translator v0.4");
|
fprintf (stderr,
|
fprintf (stderr,
|
"\nProvided by OpenSoc http://www.opensocdesign.com\n\n");
|
"\nProvided by OpenSoc http://www.opensocdesign.com\n\n");
|
fprintf (stderr, "Parsing implementation file.......\n\n");
|
fprintf (stderr, "Parsing implementation file.......\n\n");
|
|
|
processname = (char *) malloc (256 * sizeof (char));
|
processname = (char *) malloc (256 * sizeof (char));
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.