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https://opencores.org/ocsvn/sc2v/sc2v/trunk
[/] [sc2v/] [trunk/] [src/] [sc2v_step1.y] - Diff between revs 23 and 24
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| Rev 23 |
Rev 24 |
| Line 190... |
Line 190... |
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case_number
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case_number
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case_hexnumber
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case_hexnumber
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case_hexword
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case_hexnumberword
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case_word
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case_word
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case_default
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case_default
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break
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break
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| Line 777... |
Line 781... |
}
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}
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else if (verilog == 1)
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else if (verilog == 1)
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{
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{
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fprintf (file, "(");
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fprintf (file, "(");
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}
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}
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//If par after a sc_reg declaration the declaration is a type cast
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reg_found=0;
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}
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}
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closepar:
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closepar:
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CLOSEPAR
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CLOSEPAR
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{
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{
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| Line 1043... |
Line 1049... |
};
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};
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case_hexnumber:
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case_hexnumber:
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CASE HEXA NUMBER SYMBOL
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CASE HEXA NUMBER SYMBOL
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{
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{
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//Is a dec number
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defineparenthesis = 0;
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defineparenthesis = 0;
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if (translate == 1 && verilog == 0)
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if (translate == 1 && verilog == 0)
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{
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{
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if (processfound)
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if (processfound)
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{
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{
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| Line 1065... |
Line 1072... |
}
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}
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else if (verilog == 1)
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else if (verilog == 1)
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fprintf (file, "case %d %s", $3, (char *) $4);
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fprintf (file, "case %d %s", $3, (char *) $4);
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};
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};
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case_hexword:
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CASE HEXA WORD SYMBOL
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{
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//Begin with a-F
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defineparenthesis = 0;
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if (translate == 1 && verilog == 0)
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{
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if (processfound)
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{
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if (!openedcase)
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for (i = 0; i < openedkeys; i++)
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fprintf (file, " ");
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if (openedcase)
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fprintf (file, ", 'h%s", (char *)$3);
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else
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fprintf (file, "'h%s", (char *)$3);
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newline = 1;
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openedcase = 1;
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}
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}
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else if (verilog == 1)
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fprintf (file, "case 0x%s %s", (char *)$3, (char *) $4);
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};
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case_hexnumberword:
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CASE HEXA NUMBER WORD SYMBOL
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{
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//Hex number beginning with dec number
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defineparenthesis = 0;
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if (translate == 1 && verilog == 0)
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{
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if (processfound)
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{
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if (!openedcase)
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for (i = 0; i < openedkeys; i++)
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fprintf (file, " ");
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if (openedcase)
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fprintf (file, ", 'h%d%s", $3,(char *)$4);
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else
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fprintf (file, "'h%d%s", $3,(char *)$4);
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newline = 1;
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openedcase = 1;
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}
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}
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else if (verilog == 1)
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fprintf (file, "case %d%s %s", $3, (char *) $4, (char *)$5);
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};
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case_word:
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case_word:
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CASE WORD SYMBOL
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CASE WORD SYMBOL
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{
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{
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defineparenthesis = 0;
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defineparenthesis = 0;
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if (translate == 1 && verilog == 0)
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if (translate == 1 && verilog == 0)
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