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https://opencores.org/ocsvn/sc2v/sc2v/trunk
[/] [sc2v/] [trunk/] [src/] [sc2v_step1.y] - Diff between revs 25 and 27
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| Rev 25 |
Rev 27 |
| Line 125... |
Line 125... |
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%token NUMBER WORD SC_REG BOOL BIGGER LOWER OPENKEY CLOSEKEY WRITE WORD SYMBOL NEWLINE ENUM INCLUDE
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%token NUMBER WORD SC_REG BOOL BIGGER LOWER OPENKEY CLOSEKEY WRITE WORD SYMBOL NEWLINE ENUM INCLUDE
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%token COLON SEMICOLON RANGE OPENPAR CLOSEPAR TWODOUBLEPOINTS OPENCORCH CLOSECORCH SWITCH CASE DEFAULT BREAK
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%token COLON SEMICOLON RANGE OPENPAR CLOSEPAR TWODOUBLEPOINTS OPENCORCH CLOSECORCH SWITCH CASE DEFAULT BREAK
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%token HEXA DEFINE READ TRANSLATEOFF TRANSLATEON VERILOGBEGIN VERILOGEND TAB DOLLAR MINEQ
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%token HEXA DEFINE READ TRANSLATEOFF TRANSLATEON VERILOGBEGIN VERILOGEND TAB DOLLAR MINEQ
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%token VOID TTRUE TFALSE ENDFUNC INC DEC INTEGER EQUALS
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%token VOID TTRUE TFALSE ENDFUNC INC DEC INTEGER EQUALS
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%token PIFDEF PENDDEF PELSE
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%token PIFDEF PIFNDEF PENDDEF PELSE
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%% commands: /* empty */
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%% commands: /* empty */
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|commands command;
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|commands command;
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| Line 220... |
Line 220... |
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verilogend
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verilogend
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ifdef
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ifdef
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ifndef
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endif
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endif
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pelse
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pelse
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ttrue
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ttrue
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| Line 1282... |
Line 1284... |
}
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}
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else if (verilog == 1)
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else if (verilog == 1)
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fprintf (file, "#ifdef");
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fprintf (file, "#ifdef");
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};
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};
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ifndef:
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PIFNDEF
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{
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defineparenthesis = 0;
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if (translate == 1 && verilog == 0)
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{
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if (processfound)
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{
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ifdeffound = 1;
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fprintf (file, "`ifndef");
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}
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else if (definefound)
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{
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fprintf (FILE_DEFINES, "`ifndef");
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}
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}
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else if (verilog == 1)
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fprintf (file, "#ifndef");
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};
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endif:
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endif:
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PENDDEF
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PENDDEF
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{
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{
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defineparenthesis = 0;
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defineparenthesis = 0;
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if (translate == 1 && verilog == 0)
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if (translate == 1 && verilog == 0)
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