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/* -----------------------------------------------------------------------------
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/* -----------------------------------------------------------------------------
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*
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*
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* SystemC to Verilog Translator v0.4
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* SystemC to Verilog Translator v0.4
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* Provided by OpenSoc Design
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* Provided by Universidad Rey Juan Carlos
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*
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* www.opensocdesign.com
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*
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*
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* -----------------------------------------------------------------------------
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* -----------------------------------------------------------------------------
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* This program is free software; you can redistribute it and/or modify
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* the Free Software Foundation; either version 2 of the License, or
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© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.